CN102998614B - System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method - Google Patents
System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method Download PDFInfo
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Abstract
The invention discloses a system capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and a debugging method. The system is provided with a plurality of DSP plates. The DSP plates are provided with input JTAG interfaces, output JTAG interfaces and off-on control circuits connected between the input JTAG interfaces and the output JTAG interfaces, wherein the input JTAG interfaces and the output JTAG interfaces are arranged on the DSP plates. A first one of series-connection DSP chips on the DSP plates is connected with the input JTAG interfaces, and a last one of the series-connection DSP chips on the DSP plates is connected with the output JTAG interfaces. During single-plate debugging, the input JTAG interface of one DSP plate is directly connected with a simulator. During multi-plate debugging, the plurality of DSP plates are connected through JTAG interconnection cables. The JTAG interconnection cables are connected between the DSP plates so as to switch to a multi-plate debugging mode automatically, the JTAG interconnection cables are removed so as to switch to a single-plate mode, and the system is convenient to use. Through hard wiring between the plates, the system and the debugging method can avoid misoperation of users and have high reliability.
Description
Technical field
The present invention relates to the DSP adjustment method based on JTAG standard, relate in particular to system and the adjustment method of a kind of DSP of realization veneer or many plates JTAG debugging.
Background technology
At present, in DSP(Digital Signal Processing digital signal processing) in the debug process of system, with JTAG(Joint Test Action Group combined testing action group) hardware capability debugging and the software algorithm of carrying out DSP verify it is the debugging method of current main flow.Jtag boundary scanning has adopted IEEE1149.1 standard, this testing standard to define hardware configuration and the working mechanism that uses JTAG.Its advantage be by complicated circuit board testing be transformed into have good structural, can simply and flexibly process by software.
The principle of work of JTAG can be summed up as: at a device inside definition TAP (Test AccessPort, test access mouth), by special-purpose jtag test instrument, internal node is tested and debugged.Its basic thought is to increase a shift register cell near on the I/O pin of chip, namely boundary scan register (Boundary-Scan Register).When chip is during in debugging mode, boundary scan register can be kept apart chip and peripheral I/O.By boundary scan register unit, can realize the observation of chip input/output signal and control.For the input pin of chip, can signal (data) be loaded in this pin and be gone by the boundary scan register unit being attached thereto; For the output pin of chip, also can by the boundary scan register being attached thereto, " catch " output signal on this pin.Under normal running status, boundary scan register is transparent to chip, so normal operation can not be affected.Like this, boundary scan register provides a kind of mode easily for observing and control the chip of required debugging.In addition, boundary scan (displacement) register cell on chip I/O pin can be connected with each other, and appoints boundary scan chain of surrounding's formation (Boundary-Scan Chain) of chip.Boundary scan chain is input and output serially, by corresponding clock signal and control signal, just can observe easily and control the chip being under debugging mode.
TAP (Test Access Port) is a general port, all data registers (DR) and the order register (IR) that by TAP, can access chip provide.The control of whole TAP is completed by TAP controller (TAP Controller).In the jtag interface of DSP, mainly contain following 6 signals.Wherein, front 4 signals are mandatory requirements in IEEE1149.1 standard.
◇ TCK: clock signal, for the operation of JTAG provide one independently, basic clock signal.
◇ TMS: mode select signal.
◇ TDI: data input signal.
◇ TDO: data output signal.
◇ TRST: reset signal.
◇ EMU: simulation data signal, this signal is open collector output.
Jtag boundary scanning is a testing standard that is mainly used in on-chip circuit, but in practical application, scope is very extensive.The range of application of JTAG mainly contains two large classes at present: a class is for the electrical specification of test chip, and whether detection chip has problem; Another kind of for to all kinds of chips with and peripherals debug.A DSP who contains JTAG debugging interface module, as long as clock is normal, just can by jtag interface access DSP internal register, hang over equipment on dsp bus and the register of built-in module.
Therefore at present because jtag interface has advantages of above-mentionedly, be widely used in the debugging and test of dsp system.
For one by many plates, every plate comprises the system that a plurality of DSP nodes form, the JTAG daisy chain that traditional JTAG adjustment method can only utilize single emulator to form a plurality of DSP in veneer is debugged, when needs carry out combined debugging to many plates, the mode that can only adopt a plurality of emulators independently to debug, as shown in Figure 1.
But in the dsp system of many plates multinode, jtag interface mainly contains following restriction: limited, the single jtag interface of physical distance of connection is only supported debugging single board.Thereby in the situation that having a plurality of DSP nodes and being distributed on a plurality of circuit boards, single jtag circuit cannot meet the needs of application.No matter being external or domestic at present, is to be generally the modes that adopt a plurality of jtag circuits, use many cover emulation software and hardwares to this way to solve the problem.This mode to realize cost higher, more than reaching the several times of single jtag circuit, and the scope of application is also more limited, cannot meet the application needs that to multi-slab debugging has higher synchronous requirement.
Summary of the invention
The technical problem to be solved in the present invention is for carrying out the defect of combined debugging to many plates multiple DSP system in prior art, and system and the adjustment method of a kind of DSP of realization veneer or many plates JTAG debugging is provided.
The technical solution adopted for the present invention to solve the technical problems is:
The system that a kind of DSP of realization veneer or many plates JTAG debugging are provided, this system comprises a plurality of dsp boards;
On described dsp board, comprise a plurality of dsp chips with daisy chaining series connection; Described dsp board is provided with input jtag interface and output jtag interface, and is connected to the ON-OFF control circuit between described input jtag interface and described output jtag interface; First dsp chip of connecting on described dsp board connects described input jtag interface, and last piece dsp chip connects described output jtag interface;
During debugging single board, the input jtag interface of single dsp board is directly connected with emulator, and described ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and described emulator form JTAG debugging loop;
During many plate debugging, a plurality of dsp boards connect by JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second input jtag interface to last dsp board is connected to the output jtag interface of previous dsp board successively by JTAG interconnect cable, described ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make to form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and described emulator form JTAG debugging loop.
In system of the present invention, described ON-OFF control circuit comprises pull-up resistor and with high level, enables the single channel logic gate of control end;
One end of described pull-up resistor is connected with high level signal, the other end enables control end with the high level of described single channel logic gate and is connected, this high level signal makes described single channel logic gate in enabled state, this other end also with described plate between jtag interface enable control pin and be connected, when many plate debugging, describedly enable to control pin access low level signal, make described single channel logic gate in disabled state;
The input end of described single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
In system of the present invention, described ON-OFF control circuit comprises pull down resistor and with low level, enables the single channel logic gate of control end;
One end of described pull down resistor is connected with low level signal, the other end enables control end with the low level of described single channel logic gate and is connected, this low level signal makes described single channel logic gate in enabled state, this other end also with described plate between jtag interface enable control pin and be connected, when many plate debugging, describedly enable to control pin access high level signal, make described single channel logic gate in disabled state;
The input end of described single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
In system of the present invention, described single channel logic gate is logical device independently, or realizes by FPGA and CPLD device.
In system of the present invention, described input jtag interface comprises signal pins/TRST, TCK, TMS, TDI and the TDO of IEEE1149.1 standard regulation, and pin/EMU, KEY, GND and CTL, wherein pin/EMU is simulation data signal, this output signal is open collector output signal, KEY is avoiding misinsertion pin, and GND is the signal ground in plate, CTL connect previous dsp board ON-OFF control circuit enable control end;
Described output jtag interface comprises signal pins/TRST, TCK, TMS, TDI and the TDO of IEEE1149.1 standard regulation, and pin/EMU, KEY, GND and EN, wherein EN is for enabling to control pin, connect place dsp board ON-OFF control circuit enable control end.
In system of the present invention, on each dsp board, be also provided with clock signal driving circuit, be connected with the clock input pin of each dsp chip.
The present invention solves another technical scheme that its technical matters adopts:
The JTAG adjustment method that the many DSP of a kind of many plates are provided, comprises the following steps:
Mode by the polylith dsp chip in same dsp board with daisy chain is connected in a JTAG link;
Input jtag interface and output jtag interface are set in each dsp board, and between described input jtag interface and described output jtag interface, ON-OFF control circuit is set, first dsp chip of connecting on each dsp board connects described input jtag interface, and last piece dsp chip connects described output jtag interface;
During many plate debugging, a plurality of dsp boards are connected by JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second input jtag interface to last dsp board is connected to the output jtag interface of previous dsp board successively by JTAG interconnect cable, described ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make to form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and described emulator form JTAG debugging loop.
In JTAG adjustment method of the present invention, also comprise step:
During debugging single board, disconnecting described JTAG interconnect cable connects, the input jtag interface of single dsp board is directly connected with described emulator, and described ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and described emulator form JTAG debugging loop.
In JTAG adjustment method of the present invention, also comprise the step of each dsp chip on each dsp board being carried out to clock signal driving.
The beneficial effect that the present invention produces is: the present invention is by interconnected jtag interface between setting up for plate on each DSP, comprise input jtag interface and output jtag interface, between dsp board, connect JTAG interconnect cable and can automatically switch to many plates debud mode, remove JTAG interconnect cable and become again veneer mode, use very convenient.The present invention can also prevent user's maloperation by hard wired mode between plate, has higher reliability.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the debugging structural representation of many plates multiple DSP system in prior art;
Fig. 2 is the structural representation of system when many plates debugging that can realize DSP veneer or many plates JTAG debugging in the embodiment of the present invention;
Fig. 3 is the single plate structure schematic diagram in the embodiment of the present invention;
Fig. 4 be embodiment of the present invention ON-OFF control circuit realize schematic diagram one;
Fig. 5 be embodiment of the present invention ON-OFF control circuit realize schematic diagram two.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
The embodiment of the present invention can realize the system of DSP veneer or many plates JTAG debugging, comprises a plurality of dsp boards, as shown in Figure 2, comprises A plate, B plate and C plate, wherein, comprises four dsp chips, as the S0 on A plate, S1, S2 and S3 on every dsp board.
As shown in Figures 2 and 3, on dsp board, comprise a plurality of dsp chips with daisy chaining series connection; Dsp board is provided with input jtag interface (JTAGIN) and output jtag interface (JTAGOUT), and is connected to the ON-OFF control circuit between input jtag interface and output jtag interface; First dsp chip of connecting on dsp board connects input jtag interface, and last piece dsp chip connects output jtag interface.
During debugging single board, the input jtag interface of single dsp board is directly connected with emulator, and ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and emulator form JTAG debugging loop;
During many plate debugging, a plurality of dsp boards connect by JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second input jtag interface to last dsp board is connected to the output jtag interface of previous dsp board successively by JTAG interconnect cable, ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make to form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and emulator form JTAG debugging loop.
In one embodiment of the invention, the interface definition of input jtag interface (JTAGIN) and output jtag interface (JTAGOUT) is as shown in the table:
The interface definition table of table 1JTAGIN and JTAGOUT
| JTAGIN | Signal name | JTAGOUT | Signal name |
| 2 pin | /EMU | 2 pin | /EMU_OUT |
| 6 pin | TMS | 6 pin | TMS_OUT |
| 8 pin | TCK | 8 pin | TCK_OUT |
| 10 pin | /TRST | 10 pin | /TRST_OUT |
| 12 pin | TDI | 12 pin | TDI_OUT |
| 14 pin | TDO | 14 pin | TDO_OUT |
| 16 pin | CTL | 16 pin | EN |
| 3 pin | KEY (mistake proofing pin) | 5 pin | KEY (mistake proofing pin) |
| Other pin | GND | Other pin | GND |
Wherein pin/TRST of JTAGIN, TCK, TMS, TDI, TDO are the signal of IEEE1149.1 standard regulation; / EMU is simulation data signal, and this signal is open collector output; KEY is avoiding misinsertion pin; GND is the signal ground in plate; The 16 pin CTL of JTAGIN connect previous dsp board ON-OFF control circuit single channel logic gate enable control end.
Pin/TRST_OUT of JTAGIN, TCK_OUT, TMS_OUT, TDI_OUT, TDO_OUT are the signal of IEEE1149.1 standard regulation; / EMU is simulation data signal, and this signal is open collector output; KEY is avoiding misinsertion pin; GND is the signal ground in plate; The 16 pin EN of JTAGOUT are for enabling to control pin, connect place dsp board ON-OFF control circuit single channel logic gate enable control end.The interconnecting relation of JTAGIN and each signal of JTAGOUT as shown in Figure 3.
As shown in Figure 3, in veneer A plate, the jtag interface of 4 dsp chips in plate adopts daisy architecture, i.e. second TDI of the TDO of first access, and the TDO of second accesses the TDI of the 3rd, interconnected between two, forms chain structure, while considering the cascade of many plates, DSP quantity is more, and load is larger, therefore, has adopted special-purpose driver G2, G3 to drive TDI, TDO signal in this embodiment, strengthens its load capacity, during debugging single board, debug machine emulator interface is directly connected with JTAGIN interface, take A plate as example, debug machine emulator interface is connected with A plate by JTAG interconnect cable, now A plate is not connected with the JTAG interconnect cable between B plate, ON-OFF control circuit between its JTAGOUT and JTAGIN is for disconnecting, therefore A plate (or is called most end node state in debugging single board, now the JTAG signal on plate no longer spreads out of from JTAGOUT, but directly return from JTAGIN) state, its TDI, TDO signal automatically switches to self-loop (daisy chain) state in plate, EMU, CLK automatically switches to direct-connected state in plate.The JTAG mode that now, can realize A plate is independently debugged.
According to the requirement of IEEE1149.1 standard, tck signal ,/TRST signal, tms signal should adopt on pull-up resistor and draw, and guarantee that it is in steady state (SS);
Because the tck clock of DSP reaches as high as 50MHz, therefore, in veneer or many plates cascade system, must drive step by step.In one embodiment of the present of invention, on each dsp board, be also provided with clock signal driving circuit, be connected with the clock input pin (TCK) of each dsp chip.If >3 is counted in the cascade of many plates cascade system, when on veneer, DSP>4 is above, for guaranteeing that tck clock can run on highest frequency, and each DSP node has good synchronizing characteristics, need to adopt special clock delay circuit carry out the accurate adjustment that tck clock prolongs, dwindle the JTAG clock skew between the longest DSP of the shortest DSP of tck signal in whole system and tck signal.Therefore, in this embodiment, adopted special-purpose clock signal driving circuit, guaranteed that the TCK input signal of every a slice DSP can meet the demands.
/ TRST, tms signal, in veneer, 4 DSP in this part signal while access board, and in many plates cascade system, this part signal can access all DSP simultaneously, load is larger.Therefore, in this embodiment, adopted special-purpose driver G4, G5 right/TRST, tms signal drive, and strengthens its load capacity;
/ EMU signal, due to DSP /EMU signal is all open collector output, with the logic gate G1 enabling with low level, realizes " line or " and cascade.No matter in veneer or many plates cascade system, any a slice DSP /the G1 door of EMU signal on effectively all can enable link, so just signal is delivered to always to the input of JTAG foremost.
When needs carry out many plates JTAG cascade, as shown in Figure 2, only need to utilize JTAG interconnect cable, the JTAGIN of emulator and A plate is interconnected, and the JTAGIN of the JTAGOUT of A plate and B plate is interconnected, and the JTAGIN of the JTAGOUT of B plate and C plate is interconnected.
In the embodiment of the present invention, as shown in Figure 4, ON-OFF control circuit comprises pull-up resistor and with high level, enables the single channel logic gate of control end;
One end of pull-up resistor is connected with high level signal, and the other end enables control end with the high level of single channel logic gate and is connected, and this high level signal makes single channel logic gate in enabled state.This enables control end and can connect power supply and obtain high level signal, and high level signal also can be realized by FPGA, CPLD or other modes that can be driven to high level.
When debugging single board, by the conducting of this single channel logic gate, plate internal daisy chain is closed, can form debugging loop in plate; This other end also with plate between jtag interface enable control pin (EN pin) and be connected, when many plates debugging, connect after JTAG interconnect cable, enable to control pin access low level signal, make single channel logic gate in disabled state, plate internal daisy chain opens.
The input end of single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
As shown in Figure 4, be a specific embodiment of ON-OFF control circuit of the present invention, utilize a slice band high level to enable between the single channel logic gate G6 of control signal and plate JTAG interconnect cable and realize switch and control;
The input signal of single channel logic gate G6 is the TDI signal in A plate, and this signal comes from the JTAGIN interface in plate, and draws by the 12nd pin (TDI_OUT) of JTAGOUT interface in A plate;
The output signal of single channel logic gate G6 is the TDO signal in A plate, this signal access first DSP(S0) TDI, and draw by the 14th pin (TDO_OUT) of the interior JTAGOUT interface of A plate;
The enable signal of single channel logic gate G6 is pulled to high level by resistance in plate, and draws by the 16th pin (EN) of JTAGOUT interface in A plate;
When not interconnected by JTAG interconnect cable between A plate and B plate, the enable signal of G6 is pulled to high level by pull-up resistor, now logic gate conducting, the TDI signal of A plate accesses first DSP(S0 by G6) TDI, realize JTAG daisy chain closure in plate, now can carry out debugging single board;
When passing through JTAG cable interconnect between A plate and B plate, the enable signal of G6 connects low level (GND) by 16 pins (CTL) of JTAGIN interface in B plate, and now logic gate is closed, and G6 is output as tri-state;
By JTAG interconnect cable, the TDI of the TDI signal of A plate access B plate, the TDO of the TDO signal access A plate of B plate, forms the complete daisy chain between two plates, forms many plates cascade JTAG loop, can carry out the uniting and adjustment of many plates;
The embodiment of the present invention can expand to a plurality of boards, is not restricted between two boards;
The logic gates such as the G6 relating to not only can be realized by logical device independently, also can be realized by devices such as FPGA, CPLD;
G6 enable signal ground connection not only can be realized by ground connection, also can be driven to low level mode by FPGA, CPLD or other and realize.
In another embodiment of the present invention, ON-OFF control circuit comprises pull down resistor and with low level, enables the single channel logic gate of control end;
One end of pull down resistor is connected with low level signal, the other end enables control end with the low level of single channel logic gate and is connected, this low level signal makes single channel logic gate in enabled state, this enables control end can ground connection obtain low level signal, and low level signal also can be driven to low level mode by FPGA, CPLD or other and realize.
When debugging single board, by the conducting of this single channel logic gate, plate internal daisy chain is closed, can form JTAG debugging loop in plate; This other end also with plate between jtag interface enable control pin and be connected, when many plates debugging, enable to control pin access high level signal, make single channel logic gate in disabled state; The input end of single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
The JTAG adjustment method of the many DSP of the many plates of the embodiment of the present invention, based on the above-mentioned system that realizes DSP veneer or many plates JTAG debugging, specifically comprises the following steps:
Mode by the polylith dsp chip in same dsp board with daisy chain is connected in a JTAG link;
Input jtag interface and output jtag interface are set in each dsp board, and between input jtag interface and output jtag interface, ON-OFF control circuit is set, first dsp chip of connecting on each dsp board connects input jtag interface, and last piece dsp chip connects output jtag interface;
During many plate debugging, a plurality of dsp boards are connected by JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second input jtag interface to last dsp board is connected to the output jtag interface of previous dsp board successively by JTAG interconnect cable, ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make to form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and emulator form JTAG debugging loop.
When debugging single board, disconnect JTAG interconnect cable and connect, the input jtag interface of single dsp board is directly connected with emulator, and ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and emulator form JTAG debugging loop.
Because the tck clock of DSP reaches as high as 50MHz, therefore, in veneer or many plates cascade system, must drive step by step, need carry out clock signal driving to each dsp chip on each dsp board.Specifically how to realize clock and drive above and have a detailed description in embodiment, be not repeated herein.
The present invention is by interconnected jtag interface between setting up for plate on each DSP, comprise input jtag interface and output jtag interface, between dsp board, connect JTAG interconnect cable and can automatically switch to many plates debud mode, remove JTAG interconnect cable and become again veneer mode, use very convenient.The present invention can also prevent user's maloperation by hard wired mode between plate, has higher reliability.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improvement and conversion all should belong to the protection domain of claims of the present invention.
Claims (9)
1. the system that can realize DSP veneer or many plates JTAG debugging, is characterized in that, this system comprises a plurality of dsp boards;
On described dsp board, comprise a plurality of dsp chips with daisy chaining series connection; Described dsp board is provided with input jtag interface and output jtag interface, and is connected to the ON-OFF control circuit between described input jtag interface and described output jtag interface; First dsp chip of connecting on described dsp board connects described input jtag interface, and last piece dsp chip connects described output jtag interface;
During debugging single board, the input jtag interface of single dsp board is directly connected with emulator, and described ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and described emulator form JTAG debugging loop;
During many plate debugging, a plurality of dsp boards connect by JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second input jtag interface to last dsp board is connected to the output jtag interface of previous dsp board successively by JTAG interconnect cable, described ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make to form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and described emulator form JTAG debugging loop.
2. system according to claim 1, is characterized in that, described ON-OFF control circuit comprises pull-up resistor and with high level, enables the single channel logic gate of control end;
One end of described pull-up resistor is connected with high level signal, the other end enables control end with the high level of described single channel logic gate and is connected, this high level signal makes described single channel logic gate in enabled state, this other end also with described plate between jtag interface enable control pin and be connected, when many plate debugging, describedly enable to control pin access low level signal, make described single channel logic gate in disabled state;
The input end of described single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
3. system according to claim 1, is characterized in that, described ON-OFF control circuit comprises pull down resistor and with low level, enables the single channel logic gate of control end;
One end of described pull down resistor is connected with low level signal, the other end enables control end with the low level of described single channel logic gate and is connected, this low level signal makes described single channel logic gate in enabled state, this other end also with described plate between jtag interface enable control pin and be connected, when many plate debugging, describedly enable to control pin access high level signal, make described single channel logic gate in disabled state;
The input end of described single channel logic gate connects the TDI of dsp board, and output terminal connects the TDO of dsp board.
4. according to the system described in claim 2 or 3, it is characterized in that, described single channel logic gate is logical device independently, or realizes by FPGA and CPLD device.
5. according to the system described in claim 2 or 3, it is characterized in that, described input jtag interface comprises signal pins/TRST, TCK, TMS, TDI and the TDO of IEEE1149.1 standard regulation, and pin/EMU, KEY, GND and CTL, wherein pin/EMU is simulation data signal, and this output signal is open collector output signal, and KEY is avoiding misinsertion pin, GND is the signal ground in plate, CTL connect previous dsp board ON-OFF control circuit enable control end;
Described output jtag interface comprises signal pins/TRST, TCK, TMS, TDI and the TDO of IEEE1149.1 standard regulation, and pin/EMU, KEY, GND and EN, wherein EN is for enabling to control pin, connect place dsp board ON-OFF control circuit enable control end.
6. system according to claim 5, is characterized in that, is also provided with clock signal driving circuit on each dsp board, is connected with the clock input pin of each dsp chip.
7. a JTAG adjustment method of the many DSP of plate more than, is characterized in that, comprises the following steps:
Mode by the polylith dsp chip in same dsp board with daisy chain is connected in a JTAG link;
Input jtag interface and output jtag interface are set in each dsp board, and between described input jtag interface and described output jtag interface, ON-OFF control circuit is set, first dsp chip of connecting on each dsp board connects described input jtag interface, and last piece dsp chip connects described output jtag interface;
During many plate debugging, a plurality of dsp boards are connected by JTAG interconnect cable, wherein the input jtag interface on first dsp board is connected with emulator, second input jtag interface to last dsp board is connected to the output jtag interface of previous dsp board successively by JTAG interconnect cable, described ON-OFF control circuit on a plurality of dsp boards is controlled the daisy chain of this plate and is opened, make to form daisy chain between plate between a plurality of dsp boards, a plurality of dsp boards and described emulator form JTAG debugging loop.
8. JTAG adjustment method according to claim 7, is characterized in that, also comprises step:
During debugging single board, disconnecting described JTAG interconnect cable connects, the input jtag interface of single dsp board is directly connected with described emulator, and described ON-OFF control circuit is controlled the daisy chain closure of this plate, makes a plurality of dsp chips and described emulator form JTAG debugging loop.
9. JTAG adjustment method according to claim 7, is characterized in that, also comprises the step of each dsp chip on each dsp board being carried out to clock signal driving.
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| CN104237772A (en) * | 2013-06-24 | 2014-12-24 | 英业达科技有限公司 | Debugging system |
| CN103376340B (en) * | 2013-07-04 | 2016-12-28 | 曙光信息产业(北京)有限公司 | A kind of keyset, multi-platform serial test system and method |
| CN103490757B (en) * | 2013-08-28 | 2018-10-30 | 华为技术有限公司 | A kind of signal output method and device based on I/O interfaces |
| CN104111400A (en) * | 2014-06-19 | 2014-10-22 | 中国航天科工集团第三研究院第八三五七研究所 | JTAG link interconnection method |
| CN104216747A (en) * | 2014-09-03 | 2014-12-17 | 中国电子科技集团公司第三十四研究所 | Multi-JTAG (joint test action group) interface electronic equipment upgrading system |
| CN106326058A (en) * | 2015-06-16 | 2017-01-11 | 中兴通讯股份有限公司 | JTAG debugging method and system of FPGA system |
| CN105548863B (en) * | 2015-12-29 | 2018-04-17 | 广州慧睿思通信息科技有限公司 | A kind of structure and method of the interconnection of plate level multi-chip JTAG chains |
| WO2017128181A1 (en) * | 2016-01-28 | 2017-08-03 | 华为技术有限公司 | Single board, electronic apparatus and method for channel selection |
| CN107391321B (en) * | 2016-05-17 | 2021-10-12 | 中兴通讯股份有限公司 | Electronic computer single board and server debugging system |
| CN107943734B (en) * | 2017-12-14 | 2021-06-29 | 郑州云海信息技术有限公司 | Multi-FPGA heterogeneous accelerator card debugging system and interface connection method and system thereof |
| CN109613421A (en) * | 2018-12-21 | 2019-04-12 | 郑州云海信息技术有限公司 | A kind of jtag circuit and measure and control device |
| CN112445663B (en) * | 2019-09-02 | 2022-05-03 | 瑞昱半导体股份有限公司 | Test access port circuit |
| CN110659037B (en) * | 2019-09-25 | 2021-03-09 | 苏州浪潮智能科技有限公司 | JTAG-based burning device |
| CN112422113A (en) * | 2020-11-09 | 2021-02-26 | 上海国微思尔芯技术股份有限公司 | Multi-PCB JTAG (joint test action group) cascade circuit and cascade method |
| CN114580329B (en) * | 2022-05-07 | 2022-07-22 | 湖南大学 | Real-time debugging method for digital signal processor chip |
| CN117728899A (en) * | 2024-02-06 | 2024-03-19 | 北京东远润兴科技有限公司 | Equipment joint debugging method and device, terminal equipment and storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010028070A (en) * | 1999-09-17 | 2001-04-06 | 김종수 | single/multi emulating device |
| KR20070059327A (en) * | 2005-12-06 | 2007-06-12 | 엘지노텔 주식회사 | An apparatus of jtag daisy chain for board testing |
| CN101140298A (en) * | 2007-02-27 | 2008-03-12 | 中兴通讯股份有限公司 | Reset device of test accesses terminal port of JTAG chain circuit used on board |
| CN101360245A (en) * | 2008-09-19 | 2009-02-04 | 中国人民解放军国防科学技术大学 | Large capacity image data real-time compressing apparatus and method based on multi-DSP parallel processing |
| CN102043879A (en) * | 2010-10-29 | 2011-05-04 | 中兴通讯股份有限公司 | Device and method for improving integrity of signals in JTAG chain with a plurality of devices |
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
| CN102135920A (en) * | 2011-01-17 | 2011-07-27 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault injection system for embedded spaceborne computer and injection method thereof |
-
2012
- 2012-12-14 CN CN201210549002.7A patent/CN102998614B/en not_active Expired - Fee Related
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010028070A (en) * | 1999-09-17 | 2001-04-06 | 김종수 | single/multi emulating device |
| KR20070059327A (en) * | 2005-12-06 | 2007-06-12 | 엘지노텔 주식회사 | An apparatus of jtag daisy chain for board testing |
| CN101140298A (en) * | 2007-02-27 | 2008-03-12 | 中兴通讯股份有限公司 | Reset device of test accesses terminal port of JTAG chain circuit used on board |
| CN101360245A (en) * | 2008-09-19 | 2009-02-04 | 中国人民解放军国防科学技术大学 | Large capacity image data real-time compressing apparatus and method based on multi-DSP parallel processing |
| CN102043879A (en) * | 2010-10-29 | 2011-05-04 | 中兴通讯股份有限公司 | Device and method for improving integrity of signals in JTAG chain with a plurality of devices |
| CN102135920A (en) * | 2011-01-17 | 2011-07-27 | 中国航天科技集团公司第九研究院第七七一研究所 | Fault injection system for embedded spaceborne computer and injection method thereof |
| CN102103535A (en) * | 2011-03-07 | 2011-06-22 | 北京大学深圳研究生院 | Multicore processor, and system and method for debugging multicore processor |
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