CN101140298A - Reset device of test accesses terminal port of JTAG chain circuit used on board - Google Patents
Reset device of test accesses terminal port of JTAG chain circuit used on board Download PDFInfo
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- CN101140298A CN101140298A CNA2007101115500A CN200710111550A CN101140298A CN 101140298 A CN101140298 A CN 101140298A CN A2007101115500 A CNA2007101115500 A CN A2007101115500A CN 200710111550 A CN200710111550 A CN 200710111550A CN 101140298 A CN101140298 A CN 101140298A
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Abstract
The present invention discloses a JTAG link testing access port resetting device on a veneer, which comprises an isolating module and a daisy-chain of a JTAG socket and a JTAG element on the veneer connected with an external element through the isolating module. Wherein, the isolating module prevents resetting error of the external element due to level variation of a TRST interface of the JTAG element while the JTAG socket debugs the veneer. In addition, a resetting circuit provides effective resetting pulses to the external element and transmits the resetting pulses to the daisy-chain of the JTAG element. The present invention can make a TAP port of a JTAG chip reliably enter into a correct state in two states, viz. BST testing state and normal power supply resetting state.
Description
Technical field
The present invention relates to electronic device field, relate more specifically to a kind of resetting means that is used for the test access port of the JTAG link on the veneer.
Background technology
The pin of large scale integrated circuit is more and more, all there are the difficulty of certain degree in traditional probe method of testing and nail bed formula method of testing in the production test of PCB layout and veneer, may cause that as the adding of test point line impedance is discontinuous, the chip testing point of BGA encapsulation is provided with problems such as difficulty.In order to solve the problem that PCB test aspect faces, the movable group of joint test (Joint Test Action Group, be called for short JTAG) in the nineteen ninety IEEE1149.1 standard of having drawn up, the required hardware resources of function such as some tests and the download of programmable chip program are integrated in the chip, and the problem that solves test and chip program download for the user is provided convenience.Existing jtag boundary sweep test of JTAG cause for gossip (Boundary Scan Test is called for short BST) and download function that several standard supporting chips such as IEEE1149.4, IEEE1149.6 are arranged again afterwards.At present increasing veneer can adopt JTAG mouth BST function.If have the chip (below abbreviate the JTAG chip as) of a plurality of JTAG mouths on veneer, then the JTAG daisy chain is formed in the method for attachment that can provide according to standard, by the test to the JTAG daisy chain, understands the quality of hardware of veneer.
Yet it should be noted that, the JTAG chip is (non-test mode) when operate as normal, the moment that is powering on, comprise that power supply is restarted or veneer carries out situations such as hot plug, (or abbreviate the JTAG mouth as reset) need effectively reset to the test port of JTAG mouth (TEST ACCESS PORT is called for short TAP), otherwise may make chip enter a kind of unsure state, veneer can't operate as normal, and there is certain probability in the generation of this situation.In order to solve the problem that these probabilistic take place, improve the job stability of veneer, do not enable the JTAG chip of JTAG mouth BST boundary scan testing function in the past, be used for directly ground connection or by low resistance grounding, the JTAG chip can not enter non-steady state because of the problem of JTAG mouth like this of reseting pin (TRST) that the JTAG mouth resets.But its shortcoming is, resistance in this method selects can limit when unreasonable the use of BST boundary scan testing function, the JTAG chip can not enter unstable state when the veneer in the directly grounded method normally moved, but will make the BST disabler of test usefulness like this, the too small driving force of BST testing apparatus that then requires of resistance is very strong, resistance is excessive, can not cause the problem of BST test function, but the JTAG mouth proper reset surely that differs may make the JTAG chip enter non-steady state when operate as normal powered on.The TRST port of general JTAG device all has a pull-up resistor at chip internal, and when the length (that is, the quantity of JTAG device on the JTAG daisy chain) of daisy chain was different, the selection of this pull down resistor was difficult to unified.
For under JTAG mouth BST test mode and two kinds of situations of operate as normal electrification reset, the TAP mouth of JTAG chip can both enter the reliability of correct status separately, the present invention proposes a kind of resetting means that is used for the test access port of the JTAG link on the veneer.
Summary of the invention
In view of above-mentioned one or more problems, the invention provides a kind of resetting means that is used for the test access port of the JTAG link on the veneer.
The resetting means that is used for the test access port of the JTAG link on the veneer according to the present invention comprises: isolation module, the JTAG socket on the veneer and the daisy chain of JTAG device are connected to external devices by isolation module, when isolation module was used to make JTAG socket debugging veneer, the level variation of the TRST interface of JTAG device did not miss external devices and resets; And reset circuit, be used to provide effective reset pulse to external devices, and reset pulse offered the daisy chain of JTAG device by isolation module.
Wherein, isolation module comprises: first resistor, and its first end is connected to power Vcc, and second end is connected to the negative pole of first diode; First diode, its negative pole are connected to the JTAG device
Interface, its positive pole is connected to the positive pole of second diode: and second diode, its negative pole are connected to the JTAG socket
Interface.
Wherein, reset circuit is the RC circuit.The pulse width that the RC circuit produces is greater than predetermined pulse width.The resistor in the RC circuit and first resistor are same resistors.
Alternatively, reset circuit is the special use chip that resets.The special use chip that resets is MAX706/704.Under the situation of quantity greater than predetermined quantity of JTAG device, will at predetermined space
Signal wire is by little capacity earth.Veneer is the veneer that does not have the hot plug requirement.
By the present invention, make the TAP mouth of JTAG chip under the situation that is in BST test mode and operate as normal electrification reset state two states, can enter correct status reliably.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the synoptic diagram that the method for attachment of JTAG daisy chain is shown;
Fig. 2 illustrates the resetting means of JTAG daisy chain and the synoptic diagram of the annexation of element around it;
Fig. 3 is the synoptic diagram that illustrates according to the reset circuit of the resetting means of the test access port that is used for the JTAG link on the veneer of the embodiment of the invention; And
Fig. 4 is the synoptic diagram that illustrates according to the another reset circuit of the resetting means of the test access port that is used for the JTAG link on the veneer of the embodiment of the invention.
Embodiment
Below with reference to accompanying drawing, describe the specific embodiment of the present invention in detail.
The IEEE1149.1-1990 standard code, the device detection with jtag test function is visited the hardware of mouthful TAP by TDI, TDO, TMS and four pins of TCK and alternative test reset pin
Constitute.The function of these several test signals is described as follows successively:
TCK: test clock (Test Clock) is an input signal, and the clock of it and system is irrelevant, is a clock source independently.
TMS: test pattern is selected (Test Mode Select).
TDO: test data output (Test Date Output).
TDI: test data input (Test Date input).
As shown in Figure 1, if several JTAG chips are arranged on the veneer, all these JTAG chips can be linked to be the mode of JTAG daisy chain according to the requirement of standard so, and promptly the TAP mouth TDI and the TDO of each chip are end to end, TCK and TMS,
Bus is shared, prepares the JTAG socket of an external test/download on veneer, for the jtag boundary sweep chanalyst veneer is carried out hardware testing and downloads public to programming device on the veneer.
Usually,
Be ' 1 ', during asynchronous reset,
Produce sufficiently long ' a 0 ' signal of duration on the incoming line, carry out asynchronous reset with TAP mouth to each JTAG device.Concrete pulse width has certain difference according to the requirement of chip handbook, roughly all is to be not less than 100～500ns.
As shown in Figure 2, the resetting means of the test access port that is used for the JTAG link on the veneer of the present invention's proposition comprises reset circuit, AND circuit two parts.The effect of reset circuit provides effective reset pulse; The effect of AND circuit is to guarantee when adopting the JTAG socket debugging veneer of externally test/download, on the jtag interface
The level of (reset pulse) changes can not cause that the mistake of chips such as CPU resets.That is to say that reset circuit is used to provide effective reset pulse to external devices, and by reset pulse being offered the daisy chain of JTAG device as the AND circuit of isolation module.AND circuit is when being used to make JTAG socket debugging veneer, the JTAG device
The level variation of interface does not miss the isolation module that resets to external devices.The JTAG socket on the veneer and the daisy chain of JTAG device are connected to external devices by isolation module.
Wherein, isolation module comprises: first resistor, and its first end is connected to power Vcc, and second end is connected to the negative pole of first diode; First diode, its negative pole are connected to the JTAG device
Interface, its positive pole is connected to the positive pole of second diode; And second diode, its negative pole is connected to the JTAG socket
Interface.
Wherein,
(reset pulse) pulse can be produced by the RC circuit, also can be produced by the chip that resets of special use.
Consider requirement low-cost, high reliability, the present invention has further proposed to realize with the AND circuit that two resistance and diode are barricaded as the reset circuit (as shown in Figure 3, Figure 4) of JTAG chain.
Fig. 3 is the JTAG chain reset circuit of realizing with the AND circuit that RC circuit and resistance, diode are barricaded as.The reset signal of RC circuit herein, should be noted that and regulate the RC parameter, so that can be exported the low level signal that requires greater than reseting pulse width when powering on.Wherein, resistor in the RC circuit and first resistor in the isolation module are same resistors.But will also it is noted that at the JTAG chip more for a long time, may increase the complicacy in the PCB layout,
When signal lead was longer, every 8cm need place the over the ground little electric capacity of a 1000P～0.1 μ.Test shows, this circuit can both guarantee all JTAG chip operate as normal on the JTAG chain on the veneer at every turn in the process that power supply repeats to open, but in the hot plug process of veneer, exist the JTAG chip normally not to be reset, enter the possibility of labile state.Therefore, this circuit can be used for not having on the veneer of hot plug requirement.
Fig. 4 is the JTAG chain reset circuit of realizing with the AND circuit that special-purpose reset chip, resistance and diode are barricaded as.The veneer of considering a lot of communication apparatus is all done the cpu reset circuit with special uses such as the MAX706/704 chip that resets, and therefore can utilize the reset pulse of this circuit JTAG chip that resets
With MAX704T is example, no matter be electrification reset, or the MR that hand push button causes is low resetting of triggering, all can produce one greater than the low pulse (as shown in Figure 4) of 200ms at this output pin of rst_out*, can guarantee TAP mouth reliable reset the JTAG device on the JTAG daisy chain with the low pulse of this broad.Wherein, under the situation of quantity greater than predetermined quantity of JTAG device, will at predetermined space
Signal wire is by little capacity earth.Test shows, this circuit can both guarantee all JTAG chip operate as normal on the JTAG chain on the veneer at every turn in power supply repeats to open repetition hot plug process with veneer.Therefore, this circuit can be used for having on the veneer of hot plug requirement.
By the present invention, make the TAP mouth of JTAG chip under the situation that is in BST test mode and operate as normal electrification reset state two states, can enter correct status reliably.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. resetting means that is used for the test access port of the JTAG link on the veneer, its
Be characterised in that, comprise:
Isolation module, the JTAG socket on the described veneer and the chrysanthemum of JTAG device
Chain is connected to external devices by described isolation module, when described isolation module is used to make described JTAG socket to debug veneer, the JTAG device
The level of interface changes
Described external devices is not missed and resetted; And
Reset circuit is used to provide effective reset pulse to described external devices,
And described reset pulse is offered described JTAG device by described isolation module
Daisy chain.
2. resetting means according to claim 1 is characterized in that, described isolation module comprises:
First resistor, its first end is connected to power Vcc, and second end is connected to the negative pole of first diode;
Described first diode, its negative pole are connected to described JTAG device
Interface, its positive pole is connected to the positive pole of second diode; And
Described second diode, its negative pole are connected to described JTAG socket
Interface.
3. resetting means according to claim 1 and 2 is characterized in that, described reset circuit is the RC circuit.
4. resetting means according to claim 3 is characterized in that, the pulse width that described RC circuit produces is greater than predetermined pulse width.
5. resetting means according to claim 3 is characterized in that, resistor in the described RC circuit and described first resistor are same resistors.
6. resetting means according to claim 1 and 2 is characterized in that, described reset circuit is the described special use chip that resets.
7. resetting means according to claim 6 is characterized in that, the described special use chip that resets is MAX706/704.
8. resetting means according to claim 7 is characterized in that, under the situation of quantity greater than predetermined quantity of described JTAG device, and will at predetermined space
Signal wire
By little capacity earth.
9. resetting means according to claim 8 is characterized in that, described veneer is the veneer that does not have the hot plug requirement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101115500A CN100529765C (en) | 2007-02-27 | 2007-06-19 | Reset device of test accesses terminal port of JTAG chain circuit used on board |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710079938.7 | 2007-02-27 | ||
| CN200710079938 | 2007-02-27 | ||
| CNB2007101115500A CN100529765C (en) | 2007-02-27 | 2007-06-19 | Reset device of test accesses terminal port of JTAG chain circuit used on board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101140298A true CN101140298A (en) | 2008-03-12 |
| CN100529765C CN100529765C (en) | 2009-08-19 |
Family
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|---|---|---|---|
| CNB2007101115500A Expired - Fee Related CN100529765C (en) | 2007-02-27 | 2007-06-19 | Reset device of test accesses terminal port of JTAG chain circuit used on board |
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| CN (1) | CN100529765C (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183139B (en) * | 2007-11-02 | 2010-12-08 | 中兴通讯股份有限公司 | Board based on JTAG interface and design method thereof |
| CN101621293B (en) * | 2009-07-23 | 2012-09-26 | 中兴通讯股份有限公司 | JTAG device and method for realizing JTAG data downloading through isolating circuit |
| CN102831934A (en) * | 2011-06-14 | 2012-12-19 | 芯成半导体（上海）有限公司 | Method for entering into internal test mode of ASRAM chip |
| CN102998614A (en) * | 2012-12-14 | 2013-03-27 | 中船重工（武汉）凌久电子有限责任公司 | System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method |
| CN103593626A (en) * | 2013-11-11 | 2014-02-19 | 杭州晟元芯片技术有限公司 | Method for protecting chip test mode and debugging mode |
| CN103842970A (en) * | 2011-09-30 | 2014-06-04 | 高通股份有限公司 | Dynamically self-reconfigurable daisy-chain of tap controllers |
| CN105676981A (en) * | 2014-11-19 | 2016-06-15 | 湖南南车时代电动汽车股份有限公司 | Reset circuit, working method and reset method |
| CN113626310A (en) * | 2021-07-09 | 2021-11-09 | 芯来智融半导体科技(上海)有限公司 | Development and debugging system, device to be tested and debugging method |
-
2007
- 2007-06-19 CN CNB2007101115500A patent/CN100529765C/en not_active Expired - Fee Related
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101183139B (en) * | 2007-11-02 | 2010-12-08 | 中兴通讯股份有限公司 | Board based on JTAG interface and design method thereof |
| CN101621293B (en) * | 2009-07-23 | 2012-09-26 | 中兴通讯股份有限公司 | JTAG device and method for realizing JTAG data downloading through isolating circuit |
| CN102831934A (en) * | 2011-06-14 | 2012-12-19 | 芯成半导体（上海）有限公司 | Method for entering into internal test mode of ASRAM chip |
| CN103842970A (en) * | 2011-09-30 | 2014-06-04 | 高通股份有限公司 | Dynamically self-reconfigurable daisy-chain of tap controllers |
| CN102998614A (en) * | 2012-12-14 | 2013-03-27 | 中船重工（武汉）凌久电子有限责任公司 | System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method |
| CN102998614B (en) * | 2012-12-14 | 2014-08-06 | 中船重工（武汉）凌久电子有限责任公司 | System capable of achieving digital signal processor (DSP) single-plate or multi-plate joint test action group (JTAG) debugging and debugging method |
| CN103593626A (en) * | 2013-11-11 | 2014-02-19 | 杭州晟元芯片技术有限公司 | Method for protecting chip test mode and debugging mode |
| CN103593626B (en) * | 2013-11-11 | 2017-02-01 | 杭州晟元数据安全技术股份有限公司 | Method for protecting chip test mode and debugging mode |
| CN105676981A (en) * | 2014-11-19 | 2016-06-15 | 湖南南车时代电动汽车股份有限公司 | Reset circuit, working method and reset method |
| CN105676981B (en) * | 2014-11-19 | 2022-06-21 | 湖南南车时代电动汽车股份有限公司 | Reset circuit, working method and reset method |
| CN113626310A (en) * | 2021-07-09 | 2021-11-09 | 芯来智融半导体科技(上海)有限公司 | Development and debugging system, device to be tested and debugging method |
| CN113626310B (en) * | 2021-07-09 | 2023-11-24 | 芯来智融半导体科技(上海)有限公司 | Development and debugging system, equipment to be tested and debugging method |
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| Publication number | Publication date |
|---|---|
| CN100529765C (en) | 2009-08-19 |
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Effective date of registration: 20151222 Address after: Yuhuatai District of Nanjing City, Jiangsu province 210012 Bauhinia Road No. 68 Patentee after: Nanjing Zhongxing New Software Co., Ltd. Address before: 518057 Nanshan District science and Technology Industrial Park, Guangdong high tech Industrial Park, ZTE building Patentee before: ZTE Corporation |
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