CN110085625B

CN110085625B - Top-emission type display device and manufacturing method thereof

Info

Publication number: CN110085625B
Application number: CN201810628250.8A
Authority: CN
Inventors: 史文; 陈亚文; 宋晶尧; 付东
Original assignee: Guangdong Juhua Printing Display Technology Co Ltd
Current assignee: Guangdong Juhua Printing Display Technology Co Ltd
Priority date: 2018-06-19
Filing date: 2018-06-19
Publication date: 2021-12-21
Anticipated expiration: 2038-06-19
Also published as: CN110085625A

Abstract

The invention relates to a top-emission display device and a manufacturing method thereof, the top-emission display device comprises a substrate with a TFT driving array, an insulating layer, a circuit layer, a flat layer and a pixel electrode layer, wherein the insulating layer is arranged on the substrate, the circuit layer is embedded in the insulating layer, the upper surface of the circuit layer is basically flush with the upper surface of the insulating layer, the flat layer is arranged on the insulating layer and the circuit layer, and the pixel electrode layer is arranged on the flat layer. According to the top-emission display device and the manufacturing method thereof, the circuit layer is embedded in the insulating layer, the upper surface of the circuit layer is basically flush with the upper surface of the insulating layer, the flat layer can be flatly arranged on the insulating layer and the circuit layer, the effect of flattening is better achieved, the flatness of the pixel electrode layer is effectively improved, and the uniformity of light emission in the sub-pixels of the top-emission display device is further improved.

Description

Top-emission type display device and manufacturing method thereof

Technical Field

The invention relates to the field of display devices, in particular to a top-emission type display device and a manufacturing method thereof.

Background

Organic Light Emitting Diodes (OLEDs) have the advantages of self-luminescence, fast response, wide viewing angle, high brightness, lightness, thinness, etc., and quantum dot light emitting diodes (QLEDs) have the advantages of high light color purity, high light emission quantum efficiency, easy adjustment of light emission color, long service life, etc., and thus become two main research directions of current display devices. The solution processing method is adopted to manufacture the OLED and the QLED display, and has the advantages of low cost, high productivity, easy realization of large size and the like, so that the solution processing method is an important direction for the development of future display technology. Among them, printing technology is considered to be the most effective way to achieve low cost and large area full color display of OLEDs as well as QLEDs.

At present, an OLED display panel needs to adopt a relatively complex driving circuit for compensation, and most of a TFT backboard of the OLED display panel is covered by the driving circuit, so that the aperture opening ratio of the display panel adopting a bottom-emitting device structure is relatively small, the power consumption is increased, and the service life of the device is relatively low; when the top emission type device structure is adopted, the aperture opening ratio of the display panel can be greatly improved, and the problems of power consumption increase, short service life of the device and the like caused by the over-small aperture opening ratio are avoided.

However, when a printing process is used to prepare a top-emission display device, the requirement on the flatness of the pixel electrode is much higher than that of an evaporation-type device, and since the pixel electrode of the top-emission display panel covers a driving circuit, the lower end of the pixel electrode is complicated to route, so that the pixel electrode is difficult to flatten. In addition, for a large-sized display panel, due to insufficient conductivity of the top electrode, an additional auxiliary electrode needs to be introduced, which further increases the complexity of routing at the lower end of the pixel electrode. As shown in fig. 1, in a conventional top emission type display device 100, an insulating layer 120 is provided over a substrate 110, a circuit layer 130 including source and drain wirings (and an auxiliary electrode) of a TFT is provided on the upper surface of the insulating layer 120, and planarization is still difficult even by further providing a planarization layer 140 thereon, so that a step (height difference) of several tens to hundreds of nanometers still exists in a pixel electrode layer 150 provided over the planarization layer 140. The step difference can cause a phenomenon of obvious nonuniform luminescence inside the sub-pixels (pixels) in the pixel defining layer 160 of the device when an OLED device is prepared by a subsequent printing process.

Disclosure of Invention

In view of the above, it is necessary to provide a top emission type display device and a method for fabricating the same to solve the problem that the pixel electrode of the conventional top emission type display device is difficult to be planarized.

A top emission type display device, comprising:

a substrate having a TFT drive array;

an insulating layer disposed on the substrate;

the circuit layer is embedded in the insulating layer, and the upper surface of the circuit layer is basically flush with the upper surface of the insulating layer;

a planarization layer disposed on the insulating layer and the circuit layer; and the number of the first and second groups,

and the pixel electrode layer is arranged on the flat layer.

A manufacturing method of a top-emission type display device comprises the following steps:

providing a substrate with a TFT drive array;

manufacturing an insulating layer on the substrate;

patterning the insulating layer to form a groove on the insulating layer;

filling conductive metal in the groove to enable the upper surface of the conductive metal to be basically flush with the upper surface of the insulating layer so as to form a circuit layer in the insulating layer;

manufacturing a flat layer on the insulating layer and the circuit layer;

and manufacturing a pixel electrode layer on the flat layer.

Compared with the prior art, the invention has the following beneficial effects:

according to the top-emission display device and the manufacturing method thereof, the circuit layer is embedded in the insulating layer, the upper surface of the circuit layer is basically flush with the upper surface of the insulating layer, the flat layer can be flatly arranged on the insulating layer and the circuit layer, the effect of flattening is better achieved, the flatness of the pixel electrode layer is effectively improved, and the uniformity of light emission in the sub-pixels of the top-emission display device is further improved.

Drawings

Fig. 1 is a schematic view of a structure of a conventional top emission type display device;

fig. 2 is a schematic structural view of a top emission type display device according to an embodiment of the present invention;

fig. 3 is a schematic view of a fabrication structure of an insulating layer in a fabrication process in the top emission type display device shown in fig. 2;

fig. 4 is a schematic diagram illustrating a manufacturing structure of a mask layer in a manufacturing process of the top emission type display device shown in fig. 2;

fig. 5 is a schematic diagram illustrating a structure of fabricating a groove in an insulating layer in a fabrication process in the top emission type display device shown in fig. 2;

fig. 6 is a schematic view of a fabrication structure of a full-surface deposited conductive metal in a fabrication process in the top emission type display device shown in fig. 2;

fig. 7 is a schematic diagram of a manufacturing structure of a lift-off mask layer in a manufacturing process in the top emission type display device shown in fig. 2;

fig. 8 is a schematic view of a fabrication structure of a planarization layer in a fabrication process in the top emission type display device shown in fig. 2;

fig. 9 is a schematic view of a fabrication structure of a pixel electrode layer in a fabrication process in the top emission type display device shown in fig. 2.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 2, the top emission type display device 200 according to an embodiment of the present invention includes a substrate 210, an insulating layer 220, a circuit layer 230, a planarization layer 240, and a pixel electrode layer 250.

The substrate 210 has a TFT driving array thereon for driving the light emitting device to realize image display. Alternatively, the substrate 210 may be a rigid substrate or a flexible substrate. The rigid substrate can be made of ceramic materials or various glass materials. The flexible substrate may be a polyimide film (PI) and its derivatives, polyethylene naphthalate (PEN), phosphoenolpyruvate (PEP), a diphenylene ether resin, or the like. The TFT driver array may include an amorphous silicon TFT array, a poly TFT array, a metal oxide TFT array, and the like.

An insulating layer 220 is disposed on the substrate 210. Alternatively, the insulating layer 220 may be formed of a gate insulating layer or an etching stopper layer, and the material may be SiO_xOr SiN_xAnd the like.

The circuit layer 230 is buried in the insulating layer 220, and the upper surface of the circuit layer 230 is substantially flush with the upper surface of the insulating layer 220. The circuit layer 230 is made of a conductive metal, such as Al, a Cu/Mo alloy, or an Al/Mo alloy, etc. In one embodiment, the circuit layer 230 includes source and drain electrode wirings. Further, in one of the embodiments, the circuit layer 230 includes source and drain electrode wirings and an auxiliary electrode wiring. The upper surface of the circuit layer 230 and the upper surface of the insulating layer 220 refer to a surface away from the substrate 210. The upper surface of the circuit layer 230 is substantially flush with the upper surface of the insulating layer 220, which means that the height difference between the upper surface of the circuit layer 230 and the upper surface of the insulating layer 220 is not more than 1% of the thickness of the insulating layer 220, and preferably, the upper surface of the circuit layer 230 is flush with the upper surface of the insulating layer 220.

The planarization layer 240 is disposed on the insulating layer 220 and the circuit layer 230 to perform a planarization function. In the present embodiment, the planarization layer 240 is an organic mask layer, and the planarization layer 240 has a connection hole for connecting the circuit layer 230 and the pixel electrode layer 250. Preferably, the planarization layer 240 has a thickness of 1 μm to 2 μm, such as 1 μm, 1.5 μm.

The pixel electrode layer 250 is disposed on the planarization layer 240. In the present embodiment, the pixel electrode layer 250 is a flat reflective conductive film, such as a metal Ag, Al or a semiconductor oxide ITO, which is equivalent to a metal stack structure. The pixel electrode layer 250 is a patterned electrode layer, and has a pattern region (i.e., a portion having an electrode material) and a blank region (a portion where the electrode material is removed by etching or the like).

Further, the top emission type display device 200 further includes a pixel defining layer 260, and the pixel defining layer 260 is disposed on the planarization layer 240 having the patterned pixel electrode layer 250. The pixel defining layer 260 is used to define the light emitting area of the adjacent sub-pixel unit, and the thickness thereof can be selected to be in the range of 800 nm-1500 nm. In one embodiment, the surface of the pixel defining layer 260 is lyophobic to prevent color mixing caused by ink overflow during the printing process.

In the top emission type display device 200, the circuit layer 230 is embedded in the insulating layer 220, and the upper surface of the circuit layer 230 is substantially flush with the upper surface of the insulating layer 220, so that the flat layer 240 can be flatly arranged on the insulating layer 220 and the circuit layer 230, and the flat layer 240 can better perform a flattening function, thereby effectively improving the flatness of the pixel electrode layer 250, and further improving the uniformity of light emission in the sub-pixels of the top emission type display device 200.

Referring to fig. 3 to 9, the method for manufacturing the top emission type display device 200 includes the following steps:

providing a substrate 210 having a TFT drive array;

forming an insulating layer 220 on a substrate 210;

patterning the insulating layer 220 to form a groove 222 on the insulating layer 220;

filling the groove 222 with a conductive metal 400 so that the upper surface of the conductive metal 400 is substantially flush with the upper surface of the insulating layer 220, thereby forming a circuit layer 230 in the insulating layer 220;

fabricating a planarization layer 240 on the insulating layer 220 and the circuit layer 230;

a pixel electrode layer 250 is formed on the planarization layer 240.

The method for manufacturing the top emission type display device 200 of one embodiment includes the following steps:

in step S1, a substrate 210 having a TFT drive array is provided.

In step S2, referring to fig. 3, an insulating layer 220 is formed on the substrate 210.

In the present embodiment, the gate electrode is formed by depositing SiO on the substrate 210 having the TFT driving array_xOr SiN_xEtc. to obtain the insulating layer 220.

In step S3, please further refer to fig. 4, a mask layer 300 is formed on the insulating layer 220.

In the present embodiment, the mask layer 300 is a photoresist layer.

In step S4, please refer to fig. 4, the mask layer 300 is patterned.

In this embodiment, a design pattern including source and drain electrode wirings is provided, the mask layer 300 is developed according to the design pattern, and a part of the mask layer 300 is removed to form a mask opening area 232.

In the case where an auxiliary electrode needs to be added to a large-sized display device, a design pattern including source and drain electrode wirings and an auxiliary electrode wiring is provided, the mask layer 300 is developed according to the design pattern, and a portion of the mask layer 300 is removed to form a mask opening area 232.

In step S5, please further refer to fig. 5, the patterned mask layer 300 is used as a mask to etch the portion of the insulating layer 220 not covered by the mask layer 300 to form the recess 222.

In the present embodiment, a portion of the insulating layer 220 is etched away by a laser etching technique to form a groove 222 on the insulating layer 220, and the depth of the groove 222 is controlled according to the designed height of the source and drain electrode wirings (and the auxiliary electrode wiring).

In step S6, with further reference to fig. 6, a conductive metal 400 is deposited in the groove 222 and on at least a portion of the mask layer 300 surrounding the groove 222 on the side of the insulating layer 220 covered with the patterned mask layer 300, such that the upper surface of the conductive metal 400 deposited in the groove 222 is substantially flush with the upper surface of the insulating layer 220, thereby forming the circuit layer 230 in the insulating layer 220.

In the present embodiment, the conductive metal 400 is deposited on the whole surface, that is, the conductive metal 400 is deposited on the mask layer 300, and a part of the conductive metal 400 falls into the mask opening area 232 and further enters the groove 222 on the insulating layer 220 until the groove 222 on the insulating layer 220 is filled to form the circuit layer 230 in the insulating layer 220, so that the upper surface of the insulating layer 220 and the upper surface of the circuit layer 230 form a flat surface together. Alternatively, the conductive metal may be selected from, but not limited to, Al, Cu/Mo alloys, Al/Mo alloys, or the like.

In step S7, please further refer to fig. 7, the mask layer 300 is stripped, the excess conductive metal 400 surrounding the recess 222 is removed, and the conductive metal 400 in the recess 222 is retained to form the circuit layer 230.

In the present embodiment, the mask layer 300 is peeled off by a lift-off process, and the conductive metal 400 including the conductive metal deposited on the upper surface of the mask layer 300 is also peeled off together, exposing the upper surface of the insulating layer 220 and the upper surface of the circuit layer 230.

In step S8, please further refer to fig. 8, a planarization layer 240 is formed on the insulating layer 220 and the circuit layer 230.

In this embodiment, a planarization layer 240 is deposited over the insulating layer 220 and the circuit layer 230 to perform planarization.

In step S9, please further refer to fig. 9, a pixel electrode layer 250 is formed on the planarization layer 240.

Specifically, in the present embodiment, a connection hole is formed by drilling a hole in the planarization layer 240, and the pixel electrode layer 250 electrically connected to the circuit layer 230 through the connection hole is formed on the planarization layer 240.

In the present embodiment, the pixel electrode layer 250 is a flat reflective conductive film, such as a metal Ag, Al or a semiconductor oxide ITO, which is equivalent to a metal stack structure.

In one embodiment, the method for manufacturing the top emission type display device 200 further includes the following steps:

the pixel electrode layer 250 is patterned, and a pixel defining layer 260 is formed on the planarization layer 240 having the patterned pixel electrode layer 250.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A top emission type display device, comprising:

a substrate having a TFT drive array;

the insulating layer is arranged on the substrate and is a grid insulating layer;

the flat layer is directly arranged on the insulating layer and the circuit layer and is an organic mask layer;

the pixel electrode layer is directly arranged on the flat layer, so that the sub-pixels are positioned on the flat layer; and the number of the first and second groups,

a pixel defining layer disposed on the planarization layer having the pixel electrode layer, the pixel defining layer for defining a light emitting area of an adjacent sub-pixel unit.

2. The top emission type display device according to claim 1, wherein the circuit layer includes source and drain electrode wirings.

3. The top emission type display device according to claim 2, wherein the circuit layer further includes an auxiliary electrode wiring.

4. The top emission type display device according to any one of claims 1 to 3, wherein the thickness of the planarization layer is 1 μm to 2 μm.

5. A manufacturing method of a top-emission type display device is characterized by comprising the following steps:

providing a substrate with a TFT drive array;

manufacturing an insulating layer on the substrate, wherein the insulating layer is a grid electrode insulating layer;

patterning the insulating layer to form a groove on the insulating layer;

directly manufacturing a flat layer on the insulating layer and the circuit layer, wherein the flat layer is an organic mask layer;

directly manufacturing a pixel electrode layer on the flat layer to enable sub-pixels to be located on the flat layer;

and manufacturing a pixel defining layer on the flat layer with the pixel electrode layer, wherein the pixel defining layer is used for defining a light emitting area of an adjacent sub-pixel unit.

6. The method of manufacturing a top emission type display device according to claim 5, wherein the method of patterning the insulating layer comprises the steps of:

manufacturing a mask layer on the insulating layer;

patterning the mask layer;

and etching the part, which is not covered by the mask layer, on the insulating layer by using the mask layer subjected to the patterning treatment as a mask to form the groove.

7. The method for manufacturing a top emission type display device according to claim 6, wherein the method for filling the conductive metal in the recess comprises the steps of:

depositing a conductive metal on the side, covered with the patterned mask layer, of the insulating layer in the groove and at least on the part of the mask layer surrounding the groove, so that the upper surface of the conductive metal is basically flush with the upper surface of the insulating layer;

and stripping the mask layer, removing the redundant conductive metal surrounding the groove, and reserving the conductive metal in the groove to form the circuit layer.

8. The method of manufacturing a top emission type display device according to claim 6, wherein the step of patterning the mask layer includes:

providing a design pattern comprising source and drain electrode wiring, developing the mask layer according to the design pattern, and removing part of the mask layer to form a mask opening area.

9. The method of manufacturing a top emission type display device according to claim 6, wherein the step of patterning the mask layer includes:

providing a design pattern comprising a source electrode wiring, a drain electrode wiring and an auxiliary electrode wiring, developing the mask layer according to the design pattern, and removing part of the mask layer to form a mask opening area.

10. The method of manufacturing a top emission type display device according to any one of claims 5 to 9, wherein the step of manufacturing a pixel electrode layer on the planarization layer includes:

and digging a hole on the flat layer to form a connecting hole, and manufacturing a pixel electrode layer which is electrically connected with the circuit layer through the connecting hole on the flat layer.