CN1740882A - Array base plate for liquid crystal display and producing method thereof - Google Patents
Array base plate for liquid crystal display and producing method thereof Download PDFInfo
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- CN1740882A CN1740882A CN 200510106454 CN200510106454A CN1740882A CN 1740882 A CN1740882 A CN 1740882A CN 200510106454 CN200510106454 CN 200510106454 CN 200510106454 A CN200510106454 A CN 200510106454A CN 1740882 A CN1740882 A CN 1740882A
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Abstract
The array baseplate includes a glass baseplate, a groove positioned in said glass baseplate, a grid and a grid dielectric layer positioned in said groove, a semiconductor layer at least for covering said grid dielectric layer, said semiconductor layer at least includes a channel, a source and a drain which are respectively electrically-connected with array baseplate of partial semiconductor layer liquid crystal display of two sides of said channel.
Description
[technical field]
The invention relates to array base palte of LCD and preparation method thereof, particularly relevant for LCD (Liquid Crystal Display) array substrate than flat type thin film transistor (TFT) of high penetration (high transmittance) and preparation method thereof.
[background technology]
LCD (liquid crystal display, hereinafter to be referred as LCD) be the main flow of present flat-panel screens development, its displaying principle is dielectric anisotropy and the conduction anisotropy that utilizes liquid crystal molecule to have, when extra electric field, make the ordered state conversion of liquid crystal molecule, cause liquid crystal film to produce various photoelectric effect.The panel construction of LCD is generally by two plate bases and is formed by stacking, and the space of certain distance is left in order to the perfusion liquid crystal in the centre, and is being formed with counter electrode respectively on the two substrates up and down, turning to and arranging in order to the control liquid crystal molecule.
The common thin-film transistor structure that is applied to film transistor plane indicator as shown in Figure 1, its manufacturing process is as described below.On substrate 10, have a transistor area, in transistor area, form the first metal layer, utilize the first road micro image etching procedure the first metal layer to be defined as the gate line 12 of landscape configuration.It is then square thereon that dielectric layer 14, semiconductor layer (are often referred to amorphous silicon layer in regular turn, amorphous silicon layer) 16, the n type doped silicon layer 18 and second metal level 20, and carry out the second road micro image etching procedure, the pattern of amorphous silicon layer 16, n type doped silicon layer 18 and second metal level 20 in the definition transistor, until the surface that exposes dielectric layer 14, and outside transistor area, make second metal level 20 ad-hoc location on substrate 10 form the signal wire (not shown) of vertical configuration.Then, carry out the 3rd road micro image etching procedure, in transistor area, will define a passage (channel) 19 in second metal level 20 and the n type doped silicon layer 18, and the surface that makes amorphous silicon layer 16 is exposed in the passage 19, uses amorphous silicon layer 16 and second metal level 20 further defined to form source electrode and drain electrode.
The thin film transistor (TFT) (hereinafter to be referred as TFT) that above-mentioned known techniques is made, because the excessive height that each layer piles up, it can influence liquid crystal arrangement direction arround the element.The unevenness that protrusion produced on the substrate also produces harmful effect for liquid crystal friction (Rubbing) orientation effect.In addition, the picture element viewing area is that multilayer film are set, and it influences the light transmittance of display panel, and reduces the brightness of display panel.
In addition, when forming second metal level 20, in source electrode and drain electrode two electrode places, because of ladder covers the bad defective that produces, the discontinuous of this second metal level sidewall easily caused short circuit, and it also can't effectively provide the protection of its lower floor easily.
[summary of the invention]
Therefore, according to above-mentioned problem, the object of the present invention is to provide a kind of array base palte and manufacture method thereof of LCD, can improve when making display panel, in pixel display area multilayer film are set, influence the phenomenon of the light transmittance of display panel, and solve the problem that the array base palte unevenness is caused because of TFT.
The invention provides a kind of array base palte of LCD, it is characterized in that: comprising:
One glass substrate; One groove is arranged in this glass substrate; One grid and a gate dielectric are arranged in this groove; Semi-conductor layer covers this gate dielectric at least, and this semiconductor layer comprises a passage at least; Reach an one source pole and a drain electrode, electrically connect the array base palte of the part semiconductor layer LCD of these passage both sides respectively.
The present invention also provides a kind of manufacture method of array base palte of LCD, it is characterized in that: comprise the steps: at first, a glass substrate is provided; On this glass substrate, form a patterning photoresist layer, with this substrate of expose portion; With this patterning photoresist layer is this glass substrate of cover curtain etching, to form a groove in this substrate; On this photoresist layer, deposit one first conductive layer and a gate dielectric in regular turn, and insert in this groove; Remove this photoresist layer, and use this first conductive layer and gate dielectric of peeling off on this photoresist layer, wherein first conductive layer in this groove is the grid for a thin film transistor (TFT); On this gate dielectric, form a semi-conductor layer and a doping semiconductor layer in regular turn; Deposition one second conductive layer on this doping semiconductor layer and this glass substrate; And
Graphical this second conductive layer and of one source pole and the drain electrode of this doping semiconductor layer, and this semiconductor layer of expose portion to form this thin film transistor (TFT).
The present invention also provides a kind of manufacture method of array base palte of LCD, comprises the steps: to provide a substrate; On this substrate, form a patterning photoresist layer, with this substrate of expose portion; With this patterning photoresist layer is this substrate of cover curtain etching, to form a groove in this substrate; On this photoresist layer, deposit in regular turn one first conductive layer, a gate dielectric, semi-conductor layer and a doping semiconductor layer in, and insert in this groove; Remove this photoresist layer, and use this first conductive layer, this gate dielectric, this semiconductor layer and this doping semiconductor layer of peeling off on this photoresist layer, wherein first conductive layer in this groove is the grid for a thin film transistor (TFT); Deposition one second conductive layer on this doping semiconductor layer and this substrate; And graphical this second conductive layer and of one source pole and the drain electrode of this doping semiconductor layer, and this semiconductor layer of expose portion to form this thin film transistor (TFT).
The present invention also provides a kind of manufacture method of array base palte of LCD, comprises the steps: to provide a glass substrate; On this glass substrate, form a patterning first photoresist layer, with this substrate of expose portion; With this patterning first photoresist layer is this glass substrate of cover curtain etching, to form one first groove in this substrate; On this first photoresist layer, deposit one first conductive layer, a gate dielectric, semi-conductor layer and a dielectric layer in regular turn, and insert in this first groove; Remove this first photoresist layer, and use this first conductive layer, this gate dielectric, this semiconductor layer and this dielectric layer of peeling off on this first photoresist layer, wherein first conductive layer in this first groove is the grid for a thin film transistor (TFT); On this substrate, form one second photoresist layer, the part substrate outside this this dielectric layer of second photoresist layer cover part and this first groove both sides;
With this second photoresist layer is cover curtain, the part substrate of this dielectric layer of etching and both sides thereof, and forming one second groove on this first groove, and reserve part is positioned at the dielectric layer on the passage of this semiconductor layer substantially; Deposit a doping semiconductor layer and one second conductive layer in regular turn on this second groove and this second photoresist layer; And remove this second photoresist layer, and use this doping semiconductor layer and this second conductive layer of peeling off on it.
[description of drawings]
Fig. 1 is the thin-film transistor structure that shows the common TFT of being applied to flat-panel screens.
Fig. 2 A～2H is the schematic flow sheet that illustrates one embodiment of the invention thin film transistor (TFT) tft array substrate.
Fig. 3 A～3F is the schematic flow sheet that illustrates one embodiment of the invention thin film transistor (TFT) tft array substrate.
Fig. 4 A～4G is the schematic flow sheet that illustrates one embodiment of the invention thin film transistor (TFT) tft array substrate.
[embodiment]
Fig. 2 A～2H is the schematic flow sheet that illustrates one embodiment of the invention thin film transistor (TFT) tft array substrate.At first, please refer to Fig. 2 A, a substrate 200 is provided, glass substrate for example, the preferably, this substrate 200 is an alkali-free glass substrate or glass with lower alkali content substrate.With a coating process form a photoresist layer 202 in substrate 200 on thereafter.Make this photoresist layer 202 on substrate 200 form specific pattern with known exposure and developing method, the preferably, the photoresist layer 202 after the development comprises that an opening exposes substrate.Then, be the cover curtain with the photoresist layer, with an engraving method (for example dry ecthing method) etching substrates, in substrate, to form a groove 204.
Next, shown in Fig. 2 B, deposit one first conductive layer 206a on photoresist layer 202, and insert in the groove 204.The first conductive layer 206a only fills up the groove 204 of part.The first conductive layer 206a can be Ta, Mo, W, Ti, Cr, Al, Au, Ag, its combination of Pt, Cu or its stack layer.The method of above-mentioned deposition one first conductive layer 206a can be a sputtering method PVD or electricity slurry enhancing chemical vapour deposition technique PECVD.Next, deposit a gate dielectric 206b on the first conductive layer 206a, and insert in the groove 204.This gate dielectric 206b can be monox, silicon nitride, silicon oxynitride or its combination.Follow-up, shown in Fig. 2 C, carry out peeling off (lift-off) step.In this step, be to adopt an engraving method to remove photoresist layer 202, and because photoresist layer 202 is removed, it is the first conductive layer 206a and the gate dielectric 206b on the stripping resistance layer 202 in the lump.In one embodiment, removing the method for photoresist layer 202 can be for removing photoresistance with photoresistance remover (stripper), for example: remove photoresistance, remove propyl alcohol and with the washed with de-ionized water substrate with methyl alcohol with propyl alcohol., carry out a cleaning step, to remove the first conductive layer 206a and gate dielectric 206b remaining on the substrate 200 thereafter.In the present embodiment, the first conductive layer 206a in the groove 204 are grids as thin film transistor (TFT) in the substrate 200.Preferably, the gate dielectric 206b in the groove 204 are about and substrate 200 coplines.
Then, shown in Fig. 2 D, deposit semi-conductor layer 210 on gate dielectric 206b and substrate 200, and deposit a doping semiconductor layer 212 on semiconductor layer 210.In one embodiment, semiconductor layer 210 can be formed by silicon, germanium, polysilicon or compound crystal silicon.In addition, doping semiconductor layer 212 can be in for example silicon or germanium semiconductor Doping Phosphorus or arsenic, makes its semiconductor layer that becomes n-, so that the subsequent metal layer excellent contact to be provided.Then, shown in Fig. 2 E,, remove gate dielectric 206b goes up and adjacent domain is outer doping semiconductor layer 212 and semiconductor layer 210 with known little shadow and graphical doping semiconductor layer 212 of engraving method and semiconductor layer 210.
Follow-up, shown in Fig. 2 F, deposit one second conductive layer 214 on doping semiconductor layer 212 and substrate 200.In one embodiment, second conductive layer 214 can be Ta, Mo, W, Ti, Cr, Al, Au, Ag, its combination of Pt, Cu or its stack layer.Next, shown in 2G figure, with known little shadow and graphical second conductive layer 214 of engraving method and doping semiconductor layer 212, to form an opening 216 exposed semiconductor layer 210.In this embodiment, patterned second conductive layer 214 is as source electrode 218 and drain electrode 220.As 2H figure shown in, deposit a protective seam 222 in second conductive layer 214 on, and insert opening 216 thereafter.
According to this embodiment, it is that grid and gate dielectric are formed in the groove of substrate, and its formed thin film transistor (TFT) on array base palte is smooth than known techniques.In addition, because the gate dielectric of present embodiment is not to be arranged in the viewing area, can promote the light transmittance of display panel.
Fig. 3 A～3F is the schematic flow sheet that illustrates one embodiment of the invention thin film transistor (TFT) tft array substrate.At first, please refer to Fig. 3 A, substrate 300, for example a glass substrate is provided.The preferably, this substrate 300 is an alkali-free glass substrate or glass with lower alkali content substrate.With a coating process form a photoresist layer 302 in substrate 300 on thereafter.Make this photoresist layer 302 on substrate 300 form specific pattern with known exposure and developing method, the preferably, the photoresist layer after the development comprises that an opening exposes substrate 300.Then, serve as the cover curtain with photoresist layer 302, with an engraving method (for example dry ecthing method) etching substrates 300, in substrate 300, to form a groove 304.
Next, shown in Fig. 3 B, deposit first conductive layer 306, gate dielectric 308, semiconductor layer 310 and doping semiconductor layer 312 in regular turn on photoresist layer 302, and insert in the groove 304.First conductive layer 306 can be Ta, Mo, W, Ti, Cr, Al, Au, Ag, its combination of Pt, Cu or its stack layer.The method of above-mentioned deposition one first conductive layer 306 can be a sputtering method or electricity slurry enhancing chemical vapour deposition technique.Gate dielectric 308 can be monox, silicon nitride, silicon oxynitride or its combination.Semiconductor layer 310 can be formed by silicon, germanium, polysilicon or compound crystal silicon.Doping semiconductor layer 312 can be in for example silicon or germanium semiconductor Doping Phosphorus or arsenic, makes its semiconductor layer that becomes n-, so that the subsequent metal layer excellent contact to be provided.
Next, shown in Fig. 3 C, carry out peeling off (lift-off) step.In this step, be to adopt an engraving method to remove photoresist layer 302, and because photoresist layer 302 is removed, it is first conductive layer 306, gate dielectric 308, semiconductor layer 310 and the doping semiconductor layer 312 on the stripping resistance layer 302 in the lump.In one embodiment, remove photoresist layer 302 method can for remover (stripper) for example propyl alcohol remove photoresistance, remove propyl alcohol and with the washed with de-ionized water substrate with methyl alcohol., carry out a cleaning step, to remove above-mentioned layer remaining on the substrate 300 thereafter.In the present embodiment, first conductive layer 306 in the groove is grid 306a as thin film transistor (TFT) in the substrate 300.The preferably, the doping semiconductor layer 312 in the groove 304 is about and substrate 300 coplines.
Follow-up, shown in Fig. 3 D, deposit one second conductive layer 314 on doping semiconductor layer 312 and substrate 300.In one embodiment, second conductive layer 314 can be Ta, Mo, W, Ti, its combination of Cr, Al or its stack layer.Next, shown in Fig. 3 E, with the doping semiconductor layer 312 in known little shadow and graphical second conductive layer 314 of engraving method and the groove 304, to form an opening 316 exposed semiconductor layer 310.In this embodiment, patterned second conductive layer 314 is as source electrode 318 and drain electrode 320.As Fig. 3 F shown in, deposit a protective seam 322 in source electrode 318 and drain electrode 320 in, and insert opening 316 thereafter.
According to this embodiment, it is that grid and semiconductor layer are formed in the groove of substrate, so that more smooth thin-film transistor structure to be provided.In addition, the gate dielectric of present embodiment also is not arranged in the viewing area, can promote the light transmittance of display panel.
Fig. 4 A～4G is the schematic flow sheet that illustrates one embodiment of the invention thin film transistor (TFT) tft array substrate.At first, please refer to Fig. 4 A, substrate 400, for example a glass substrate is provided.The preferably, this substrate 400 is an alkali-free glass substrate or glass with lower alkali content substrate.With a coating process form one first photoresist layer 402 in substrate 400 on thereafter.Make this first photoresist layer 402 on substrate 400 form specific pattern with known exposure and developing method, the preferably, first photoresist layer 402 after the development comprises that an opening exposes substrate 400.Then, serve as the cover curtain with first photoresist layer 402, with an engraving method (for example dry ecthing method) etching substrates 400, in substrate 400, to form one first groove 404.
Next, shown in Fig. 4 B, deposit first conductive layer 406, gate dielectric 408, semiconductor layer 410 and dielectric layer 412 in regular turn on first photoresist layer 402, and insert in first groove 404.First conductive layer 406 can be Ta, Mo, W, Ti, Cr, Al, Au, Ag, its combination of Pt, Cu or its stack layer.The method of above-mentioned deposition one first conductive layer 406 can be a sputtering method or electricity slurry enhancing chemical vapour deposition technique.Gate dielectric 408 can be monox, silicon nitride, silicon oxynitride or its combination.Semiconductor layer 410 can be formed by silicon, germanium, polysilicon or compound crystal silicon.Dielectric layer 412 can be monox, silicon nitride, silicon oxynitride or its combination.
As Fig. 4 C shown in, carry out peel off (lift-off) step thereafter.In this step, be to adopt an engraving method to remove first photoresist layer 402, and because first photoresist layer 402 is removed, it peel off first conductive layer 406, gate dielectric 408, semiconductor layer 410 and dielectric layer 412 on first photoresist layer 402 in the lump.In one embodiment, removing the method for first photoresist layer 402 can be for removing photoresistance with photoresistance remover (stripper), for example: remove photoresistance, remove propyl alcohol and with the washed with de-ionized water substrate with methyl alcohol with propyl alcohol., carry out a cleaning step, to remove above-mentioned layer remaining on the substrate 400 thereafter.In the present embodiment, first conductive layers 406 in the groove 404 are grid 406a as thin film transistor (TFT) in the substrate 400.
Next, shown in Fig. 4 D, be coated with one second photoresist layer 414 on dielectric layer 412 and substrate 400.Make this second photoresist layer 414 on substrate 400 form specific pattern with known exposure and developing method, particularly, second photoresist layer, 414 cover part dielectric layers 412 after the development and the part substrate 400 outside groove 404 both sides.Follow-up, shown in Fig. 4 E, serve as the cover curtain with second photoresist layer 414, the dielectric layer 412 of etch exposed and the part substrate 400 of both sides thereof are up to exposing semiconductor layer 410, to form one second groove 416 on this first groove 404.In one embodiment, be roughly to be positioned on semiconductor layer 410 passages via the dielectric layer 412 that stays after the etching, and the area of second groove 416 is big than first groove 404.Shown in 4E figure, its first groove 404 and second groove 416 roughly form the structure (dual damascene) of dual damascene.
Follow-up, shown in Fig. 4 F, deposit a doping semiconductor layer 418 and one second conductive layer 420 in regular turn on the semiconductor layer 410, second groove 416 and second photoresist layer 414 that expose.In one embodiment, second conductive layer 420 can be Ta, Mo, W, Ti, Cr, Al, Au, Ag, its combination of Pt, Cu or its stack layer.The preferably, second conductive layer 420 in second groove 416 is about and substrate 400 and dielectric layer 412 coplines.
Then, shown in Fig. 4 G, remove second photoresist layer 414, and use the doping semiconductor layer 418 and second conductive layer of peeling off on it 420, so in second groove, form source electrode 422 and be positioned at dielectric layer 412 both sides with drain electrode 424.In this embodiment, be that the structure with TFT is formed in first groove 404 and second groove 416 of substrate 400, it can provide smooth array base-plate structure.And the gate dielectric of present embodiment also is not arranged in the viewing area, can promote the light transmittance of display panel.
Please refer to Fig. 2 H, it is the thin film transistor (TFT) sectional view that shows one embodiment of the invention.One groove 204 is to be arranged in a substrate 200.An one grid 206a and a gate dielectric 206b are in being arranged in groove 204.The preferably, grid 206a and gate dielectric 206b approximately fill up groove 204.Semi-conductor layer 210 is to be positioned at substantially on the gate dielectric 206b.This semiconductor layer 210 comprises a passage and is positioned at the source region and the drain region of passage both sides.One doping semiconductor layer 212 is to be positioned at substantially on the source region and drain region of semiconductor layer 210.One source pole 218 is doping semiconductor layers 212 that part covers the top, source region of semiconductor layer 210.One drain electrode 220 is doping semiconductor layers 212 that part covers top, semiconductor layer 210 drain regions.One protective seam 222 covers source electrode 218 and drain electrode 220, electrically completely cuts off source electrode 218 and drain electrode 220, and covers the passage of semiconductor layer 210 substantially.
Please refer to Fig. 3 F, it is the thin film transistor (TFT) sectional view that shows another embodiment of the present invention.One groove 304 is to be arranged in a substrate 300.One grid 306a is in being positioned at groove 304 bottoms.One brake-pole dielectric layer 308 is to be arranged in groove 304, and cover gate 306a.Semi-conductor layer 310 is to be arranged in groove 304, and cover gate dielectric layer 308.This semiconductor layer 310 comprises a passage and is positioned at the source region and the drain region of passage both sides.One doping semiconductor layer 312 is arranged in groove 304, and covers substantially on the source region and drain region that semiconductor layer 310 is positioned at the passage both sides.One source pole 318 covers the doping semiconductor layer 312 and the contiguous substrate 300 thereof of top, semiconductor layer 310 source regions.One drain electrode 320 covers the doping semiconductor layer 312 and the contiguous substrate 300 thereof of top, semiconductor layer 310 drain regions.One protective seam 322 covers source electrode 318 and drain electrode 320, electrically completely cuts off source electrode 318 and drain electrode 320, and covers the passage of semiconductor layer 310 substantially.
Please refer to Fig. 4 G, it is to show the present invention's thin film transistor (TFT) sectional view of another embodiment again.One first groove 404 and one second groove 416 are arranged in a substrate 400.First groove 404 is to be positioned at this second groove 416 times, and the area of second groove 416 is big than the area of this first groove 404.One grid 406a covers first groove, 404 bottoms.One gate dielectric 408 is to be arranged in first groove 404, and cover gate 406a.Semi-conductor layer 410 is to be arranged in first groove 404, and cover gate dielectric layer 408.Semiconductor layer 410 comprises the source region and the drain region of a passage and both sides thereof.One dielectric layer 412 is positioned on the passage of semiconductor layer 410 substantially.One doping semiconductor layer 418 is positioned at dielectric layer 412 both sides, and the source of covering semiconductor layer 410 passage both sides is drawn on zone and the drain region and the bottom of second groove 416.An one source pole 422 and a drain electrode 424 are to be arranged in second groove 416, and lay respectively on the doping semiconductor layer 418 of dielectric layer 412 both sides.
According to the foregoing description, the present invention is produced on part or all of TFT in the substrate, can solve the problem that the array base palte unevenness is caused because of TFT.In addition, the present invention adopts to peel off (lift-off) technology, can simplify fabrication steps, has the advantage that reduces manufacturing time and manufacturing cost.Respectively imbed conductive layer, semiconductor layer and the dielectric layer of substrate again and can adjust etch depth and each layer thickness according to design requirement elasticity.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of a little change and the retouching that this skill person does, and must belong to protection scope of the present invention.
[symbol description]
Known techniques
10～substrate; 12～gate line;
14～insulating barrier; 16～semiconductor layer;
18～N-shaped doped silicon layer; 19～passage;
20～metal level.
The technology of the present invention
200～substrate; 202～photoresist layer;
204～groove; 206a～first conductive layer;
206b～gate dielectric; 210～semiconductor layer;
212～doping semiconductor layer; 214～the second conductive layers;
216～opening; 218～source electrode;
220～drain electrode;
300～substrate; 302～photoresist layer;
304～groove; 306～the first conductive layers;
306a～grid; 308～gate dielectric;
310～semiconductor layer; 312～doping semiconductor layer;
314～the second conductive layers; 316～opening;
318～source electrode; 320～drain electrode;
400～substrate; 402～the first photoresist layers;
404～the first grooves; 406～the first conductive layers;
406a～grid; 408～gate dielectric;
410～semiconductor layer; 412～doping semiconductor layer;
414～the second photoresist layers; 416～the second grooves;
418～doping semiconductor layer; 420～the second conductive layers;
422～source electrode; 424～drain electrode.
Claims (21)
1. the array base palte of a LCD is characterized in that: comprising:
One glass substrate;
One groove is arranged in this glass substrate;
One grid and a gate dielectric are arranged in this groove;
Semi-conductor layer covers this gate dielectric at least, and this semiconductor layer comprises a passage at least; And
One source pole and one drains, and electrically connects the part semiconductor layer of these passage both sides respectively.
2. the array base palte of LCD as claimed in claim 1 is characterized in that:
This gate dielectric is to be positioned on this grid; And
This source electrode is to be connected this semiconductor layer of part that is positioned at the passage both sides via a doping semiconductor layer respectively with this drain electrode.
3. the array base palte of LCD as claimed in claim 2 is characterized in that: more comprise a protective seam and cover this source electrode and this drain electrode, and this source electrode and this drain electrode are electrically insulated.
4. the array base palte of LCD as claimed in claim 1, it is characterized in that: this semiconductor layer is to be arranged in this groove, and covers this gate dielectric;
More comprise a doping semiconductor layer and be arranged in this groove, and cover the part that this semiconductor layer is positioned at the passage both sides; And
This source electrode and this drain electrode are to electrically connect this semiconductor layer via this doping semiconductor layer that is positioned at the passage both sides respectively.
5. the array base palte of LCD as claimed in claim 4 is characterized in that: more comprise a protective seam and cover this source electrode and this drain electrode, and this source electrode and this drain electrode are electrically insulated.
6. the array base palte of LCD as claimed in claim 1, it is characterized in that: this groove comprises one first groove and one second groove, this first groove is to be positioned under this second groove, and the area of this second groove is big than the area of this first groove;
This grid is to cover this first channel bottom;
This gate dielectric is to be arranged in this first groove, and covers this grid;
This semiconductor layer is to be arranged in this first groove, and covers this gate dielectric;
More comprise on the passage that a dielectric layer is positioned at this semiconductor layer substantially, and a doping semiconductor layer is positioned at this dielectric layer both sides, and covers this semiconductor layer of part of these semiconductor layer passage both sides; And
This source electrode and this drain electrode are to be arranged in this second groove, and lay respectively on the doping semiconductor layer of these dielectric layer both sides.
7. the array base palte of LCD as claimed in claim 6 is characterized in that: more comprise a protective seam and cover this source electrode, this drain electrode and this dielectric layer.
8. the array base palte of LCD as claimed in claim 6, it is characterized in that: the surface of this dielectric layer, this source electrode, this drain electrode and this substrate is coplane substantially.
9. the array base palte of LCD as claimed in claim 1, it is characterized in that: this substrate is a glass substrate.
10. the manufacture method of the array base palte of a LCD is characterized in that: comprise the steps:
One glass substrate is provided;
On this glass substrate, form a patterning photoresist layer, with this substrate of expose portion;
With this patterning photoresist layer is this glass substrate of cover curtain etching, to form a groove in this substrate;
On this photoresist layer, deposit one first conductive layer and a gate dielectric in regular turn, and insert in this groove;
Remove this photoresist layer, and use this first conductive layer and gate dielectric of peeling off on this photoresist layer, wherein first conductive layer in this groove is the grid for a thin film transistor (TFT);
On this gate dielectric, form a semi-conductor layer and a doping semiconductor layer in regular turn;
Deposition one second conductive layer on this doping semiconductor layer and this glass substrate; And
Graphical this second conductive layer and of one source pole and the drain electrode of this doping semiconductor layer, and this semiconductor layer of expose portion to form this thin film transistor (TFT).
11. the manufacture method of the array base palte of LCD as claimed in claim 10 is characterized in that: more comprise deposition one protective seam, to cover this source electrode, this drain electrode and this semiconductor layer of exposed portions.
12. the manufacture method of the array base palte of LCD as claimed in claim 10 is characterized in that: removing this photoresist layer is to comprise with the photoresistance remover removing this photoresistance.
13. the manufacture method of the array base palte of LCD as claimed in claim 12 is characterized in that: removing this photoresistance with the photoresistance remover is to comprise:
Remove photoresistance with propyl alcohol;
Remove propyl alcohol with methyl alcohol; And
With the washed with de-ionized water substrate.
14. the manufacture method of the array base palte of a LCD is characterized in that: comprise the steps:
One substrate is provided;
On this substrate, form a patterning photoresist layer, with this substrate of expose portion;
With this patterning photoresist layer is this substrate of cover curtain etching, to form a groove in this substrate;
On this photoresist layer, deposit in regular turn one first conductive layer, a gate dielectric, semi-conductor layer and a doping semiconductor layer in, and insert in this groove;
Remove this photoresist layer, and use this first conductive layer, this gate dielectric, this semiconductor layer and this doping semiconductor layer of peeling off on this photoresist layer, wherein first conductive layer in this groove is the grid for a thin film transistor (TFT);
Deposition one second conductive layer on this doping semiconductor layer and this substrate; And
Graphical this second conductive layer and of one source pole and the drain electrode of this doping semiconductor layer, and this semiconductor layer of expose portion to form this thin film transistor (TFT).
15. the manufacture method of the array base palte of LCD as claimed in claim 14 is characterized in that: more comprise deposition one protective seam, to cover this source electrode, this drain electrode and this semiconductor layer of exposed portions.
16. the manufacture method of the array base palte of LCD as claimed in claim 14 is characterized in that: remove this photoresist layer and comprise with the photoresistance remover and remove this photoresistance.
17. the manufacture method of the array base palte of LCD as claimed in claim 16 is characterized in that: remove this photoresistance with the photoresistance remover and comprise:
Remove photoresistance with propyl alcohol;
Remove propyl alcohol with methyl alcohol; And
With the washed with de-ionized water substrate.
18. the manufacture method of the array base palte of a LCD is characterized in that: comprise the steps:
One glass substrate is provided;
On this glass substrate, form a patterning first photoresist layer, with this substrate of expose portion;
With this patterning first photoresist layer is this glass substrate of cover curtain etching, to form one first groove in this substrate;
On this first photoresist layer, deposit one first conductive layer, a gate dielectric, semi-conductor layer and a dielectric layer in regular turn, and insert in this first groove;
Remove this first photoresist layer, and use this first conductive layer, this gate dielectric, this semiconductor layer and this dielectric layer of peeling off on this first photoresist layer, wherein first conductive layer in this first groove is the grid for a thin film transistor (TFT);
On this substrate, form one second photoresist layer, the part substrate outside this this dielectric layer of second photoresist layer cover part and this first groove both sides;
With this second photoresist layer is cover curtain, the part substrate of this dielectric layer of etching and both sides thereof, and forming one second groove on this first groove, and reserve part is positioned at the dielectric layer on the passage of this semiconductor layer substantially;
Deposit a doping semiconductor layer and one second conductive layer in regular turn on this second groove and this second photoresist layer; And
Remove this second photoresist layer, and use this doping semiconductor layer and this second conductive layer of peeling off on it.
19. the manufacture method of the array base palte of LCD as claimed in claim 18 is characterized in that: more comprise deposition one protective seam, to cover this source electrode, this drain electrode and this dielectric layer.
20. the manufacture method of the array base palte of LCD as claimed in claim 18 is characterized in that: remove this first photoresist layer and comprise with the photoresistance remover and remove this first photoresist layer.
21. the manufacture method of the array base palte of LCD as claimed in claim 20 is characterized in that: remove this first photoresist layer and comprise:
Remove photoresistance with propyl alcohol;
Remove propyl alcohol with methyl alcohol; And
With the washed with de-ionized water substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101064548A CN100368917C (en) | 2005-09-27 | 2005-09-27 | Array base plate for liquid crystal display and producing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101064548A CN100368917C (en) | 2005-09-27 | 2005-09-27 | Array base plate for liquid crystal display and producing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1740882A true CN1740882A (en) | 2006-03-01 |
| CN100368917C CN100368917C (en) | 2008-02-13 |
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| CNB2005101064548A Active CN100368917C (en) | 2005-09-27 | 2005-09-27 | Array base plate for liquid crystal display and producing method thereof |
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| CN (1) | CN100368917C (en) |
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| CN102306652A (en) * | 2011-09-19 | 2012-01-04 | 深圳莱宝高科技股份有限公司 | Array substrate, manufacturing method thereof, and display panel using same |
| CN105720105A (en) * | 2014-12-02 | 2016-06-29 | 昆山国显光电有限公司 | Bottom gate type thin film transistor and preparation method thereof |
| CN106876260A (en) * | 2017-03-03 | 2017-06-20 | 惠科股份有限公司 | Gate electrode structure, manufacturing method thereof and display device |
| CN109659315A (en) * | 2018-11-21 | 2019-04-19 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN110085625A (en) * | 2018-06-19 | 2019-08-02 | 广东聚华印刷显示技术有限公司 | Top emissive displays part and preparation method thereof |
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| JPS62190762A (en) * | 1986-02-18 | 1987-08-20 | Oki Electric Ind Co Ltd | Thin-film transistor and manufacture thereof |
| JPH10268343A (en) * | 1997-03-24 | 1998-10-09 | Sharp Corp | Liquid crystal display device and its manufacture |
| CN1151405C (en) * | 2000-07-25 | 2004-05-26 | 友达光电股份有限公司 | Thin-film transistor LCD and its manufacture |
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| CN102306652B (en) * | 2011-09-19 | 2014-10-22 | 深圳莱宝高科技股份有限公司 | Array substrate, manufacturing method thereof, and display panel using same |
| CN105720105A (en) * | 2014-12-02 | 2016-06-29 | 昆山国显光电有限公司 | Bottom gate type thin film transistor and preparation method thereof |
| CN106876260B (en) * | 2017-03-03 | 2020-03-27 | 惠科股份有限公司 | Gate electrode structure, manufacturing method thereof and display device |
| WO2018157573A1 (en) * | 2017-03-03 | 2018-09-07 | 惠科股份有限公司 | Gate electrode structure and manufacturing method therefor, and display device |
| US10388678B2 (en) | 2017-03-03 | 2019-08-20 | HKC Corporation Limited | Gate structure, method for manufacturing gate structure, and display device |
| CN106876260A (en) * | 2017-03-03 | 2017-06-20 | 惠科股份有限公司 | Gate electrode structure, manufacturing method thereof and display device |
| CN110085625A (en) * | 2018-06-19 | 2019-08-02 | 广东聚华印刷显示技术有限公司 | Top emissive displays part and preparation method thereof |
| WO2019242384A1 (en) * | 2018-06-19 | 2019-12-26 | 广东聚华印刷显示技术有限公司 | Backplane structure of display panel and preparation method therefor, and top-emitting display panel |
| CN110085625B (en) * | 2018-06-19 | 2021-12-21 | 广东聚华印刷显示技术有限公司 | Top-emission type display device and manufacturing method thereof |
| CN109659315A (en) * | 2018-11-21 | 2019-04-19 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
| CN111785737A (en) * | 2020-07-15 | 2020-10-16 | Tcl华星光电技术有限公司 | Array substrate, manufacturing method thereof and display panel |
| CN113611739A (en) * | 2020-10-12 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Method for forming grid oxide layer |
| CN113611739B (en) * | 2020-10-12 | 2022-08-30 | 联芯集成电路制造(厦门)有限公司 | Method for forming grid oxide layer |
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