JPS62190762A - Thin-film transistor and manufacture thereof - Google Patents
Thin-film transistor and manufacture thereofInfo
- Publication number
- JPS62190762A JPS62190762A JP3187786A JP3187786A JPS62190762A JP S62190762 A JPS62190762 A JP S62190762A JP 3187786 A JP3187786 A JP 3187786A JP 3187786 A JP3187786 A JP 3187786A JP S62190762 A JPS62190762 A JP S62190762A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- groove
- substrate
- forming
- resist pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000010408 film Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 17
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 7
- 239000012212 insulator Substances 0.000 abstract description 4
- 239000003960 organic solvent Substances 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 11
- 239000007789 gas Substances 0.000 description 6
- 239000011651 chromium Substances 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000007738 vacuum evaporation Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
この発明は、薄膜トランジスタ(以下TPTと略す)お
よびその製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a thin film transistor (hereinafter abbreviated as TPT) and a manufacturing method thereof.
(従来の技術) 従来のTPTの平面図および断面図を第3図(a)。(Conventional technology) FIG. 3(a) shows a plan view and a cross-sectional view of a conventional TPT.
(b)に示す。このTPTの製造方法としては、まず、
ガラス基板または石英基板などの透光性絶縁物基板1上
にr−ト電極2を形成する。このゲート電極2はニクロ
ム(NiCr)、タングステン(W)、モリブデン(M
O)またはクロム(Cr)などからなる金属層を前記基
板1上に200〜1000人の厚さで真空蒸着法または
スノ母ツタ法などによシ被着形成した後、該金属層を所
定のパターンに加工することによ多形成される。次に、
それらの上に、r −上絶縁層3を形成するためのシリ
コン窒化膜(Si Nx)を、NH8とSi&を主成分
ガスとしてグロー放電法によ#)0.3〜0.6μmの
膜厚で堆積させる。さらに、その上に、活性層4を形成
するだめのアモルファスシリコン層を、SiH4ガスの
グロー放電法によシ0.1〜0.3μm厚で堆積させる
。その後、アモルファスシリコン層とシリコン窒化膜の
TPTとなる部分以外を除去加工して島状にノソターニ
ングすることによシ、残った島状シリコン窒化膜パター
ンおヨヒアモルファスシリコン層パターンによシ前記r
−ト絶縁層3および活性層4を形成する。その後、活性
層4上に一部重なるようにして、0.8〜1.0μmの
厚みのアル層からなるドレイン電極5とソース電極6を
、A/の真空蒸着と加工により形成する。以上でTPT
が完成する。Shown in (b). As for the manufacturing method of this TPT, first,
An r-to-electrode 2 is formed on a transparent insulating substrate 1 such as a glass substrate or a quartz substrate. This gate electrode 2 is made of nichrome (NiCr), tungsten (W), molybdenum (M
After forming a metal layer made of O) or chromium (Cr) or the like to a thickness of 200 to 1000 layers on the substrate 1 by vacuum evaporation method, snow ivy method, etc., the metal layer is deposited in a predetermined manner. Polymers are formed by processing into patterns. next,
On top of them, a silicon nitride film (SiNx) for forming the r-upper insulating layer 3 is deposited with a film thickness of 0.3 to 0.6 μm using a glow discharge method using NH8 and Si as main component gases. Deposit with. Furthermore, an amorphous silicon layer for forming the active layer 4 is deposited thereon to a thickness of 0.1 to 0.3 .mu.m by a glow discharge method using SiH4 gas. After that, by removing the amorphous silicon layer and the silicon nitride film other than the part that will become the TPT and turning it into an island shape, the remaining island-like silicon nitride film pattern is formed into the amorphous silicon layer pattern described above.
- forming the insulating layer 3 and the active layer 4; Thereafter, a drain electrode 5 and a source electrode 6 made of an Al layer having a thickness of 0.8 to 1.0 μm are formed by vacuum evaporation and processing of A/ so as to partially overlap the active layer 4. That's all TPT
is completed.
このTPTは、その後、ソース電極6に接続するように
透明電極7を形成し、TPTと透明電極を二次元に配置
すると、液晶表示装置のTFTアレイとして利用される
。This TPT is then used as a TFT array of a liquid crystal display device by forming a transparent electrode 7 so as to be connected to the source electrode 6, and arranging the TPT and the transparent electrode two-dimensionally.
(発明′が解決しようとする問題点)
しかしながら、上記従来の技術では、r−上絶縁層3お
よび活性層4の膜厚による0、6〜0.9μmの段差の
ため、第3図(b)の円内で示すように、ドレイン電極
5が加工時に断線しやすいという問題点があった。これ
を防止するためには、ドレイン電極5の膜厚を厚くする
、または電極幅を広くするなどが考えられるが、これら
はTPT素子自体の寸法を大きくしてしまう・したがっ
て、高密度にTPTを配置したTPTパネルを作成する
ことは困難となる。(Problems to be Solved by the Invention') However, in the above conventional technique, there is a step difference of 0.6 to 0.9 μm depending on the film thickness of the r-upper insulating layer 3 and the active layer 4, as shown in FIG. ), there was a problem in that the drain electrode 5 was easily broken during processing. In order to prevent this, it is possible to increase the thickness of the drain electrode 5 or widen the electrode width, but these would increase the dimensions of the TPT element itself. It becomes difficult to create a TPT panel that has been arranged.
この発明は上記の点に鑑みなされたもので、その目的は
、ドレイン電極の断線を防止できるTPTおよびその製
造方法を提供することにある。The present invention has been made in view of the above points, and an object thereof is to provide a TPT and a method for manufacturing the same that can prevent disconnection of the drain electrode.
(問題点を解決するだめの手段)
この発明では、絶縁物基板に溝を形成し、この溝にゲー
ト電極、P−ト絶縁層、活性層およびオーミック層を埋
め込む。(Another Means to Solve the Problems) In the present invention, a groove is formed in an insulating substrate, and a gate electrode, a P-to insulating layer, an active layer, and an ohmic layer are embedded in the groove.
また、この発明では、絶縁物基板に溝を形成した後、該
溝形成のマスクとしてのレジスト/臂ターンを残したま
ま、前記ゲート電極、r−)絶縁層。Further, in the present invention, after forming a groove in the insulating substrate, the gate electrode and the r-) insulating layer are formed while leaving the resist/arm turn as a mask for forming the groove.
活性層およびオーミック層を形成するための金属層、絶
縁膜、半導体層および高濃度不純物ドープ半導体層を全
面に形成し、その後、前記レジストノぐターンを除去す
る。A metal layer, an insulating film, a semiconductor layer, and a highly impurity-doped semiconductor layer for forming an active layer and an ohmic layer are formed on the entire surface, and then the resist groove is removed.
(作用)
上記レジストパターンを除去すると、該レジストパター
ン上の不要部分の金属層、絶縁膜、半導体層および高濃
度不純物ドープ半導体層も除去され、金属層から高濃度
不純物ドープ半導体層までの多層構造は基板の溝内にの
み残る。すなわち、r−ト電極、グート絶縁層、活性層
およびオーミック層が、溝形成時のマスクとしてのンジ
ストノ9ターンを利用してリフトオフ法によ多形成され
る。(Function) When the resist pattern is removed, unnecessary portions of the metal layer, insulating film, semiconductor layer, and highly impurity-doped semiconductor layer on the resist pattern are also removed, resulting in a multilayer structure from the metal layer to the highly impurity-doped semiconductor layer. remains only in the groove of the substrate. That is, the r-to-electrode, the groove insulating layer, the active layer, and the ohmic layer are formed by a lift-off method using a nine-turn resistor as a mask during groove formation.
また、このようにしてゲート電極+l’ l’絶縁層
、活性層およびオーミック層が溝内に埋め込み形成され
ると、ドレイン電極およびソース電極を形成する直前の
表面状態が平担となる。Further, when the gate electrode+l'l' insulating layer, active layer, and ohmic layer are buried in the trench in this manner, the surface state immediately before forming the drain electrode and source electrode becomes flat.
(実施例) 以下この発明の一実施例を第1図を参照して説明する。(Example) An embodiment of the present invention will be described below with reference to FIG.
5
まず、第1図(&)に示すように、ガラス基板または石
英基板などからなる透光性絶縁物基板11上に、所定の
レジストパターン12を形成する。そして、同図に示す
ように、レジストパターン12をマスクとして、フッ酸
(HF )系のエツチング液を用いて、深さ0.5〜0
.9μmの溝13を基板11の表面の一部に形成する。5. First, as shown in FIG. 1 (&), a predetermined resist pattern 12 is formed on a transparent insulating substrate 11 made of a glass substrate, a quartz substrate, or the like. Then, as shown in the figure, using the resist pattern 12 as a mask, a hydrofluoric acid (HF)-based etching solution is used to remove the etchant to a depth of 0.5 to 0.
.. A groove 13 of 9 μm is formed in a part of the surface of the substrate 11.
次いで、第1図(b)に示すように、前記溝形成時のマ
スクとしてのレジストパターン12を残したまま、溝1
3内を含む基板11上の全面に、r−ト電極を形成する
ためのニクロム(NiCr)、クロム(Cr)、または
タングステン(W’)よ〕なる金属層14を200〜1
000大の厚みで真空蒸着法またはマグネトロンスパッ
タ法にょ)被着する。Next, as shown in FIG. 1(b), the grooves 1 are formed while leaving the resist pattern 12 as a mask for forming the grooves.
A metal layer 14 made of nichrome (NiCr), chromium (Cr), or tungsten (W') for forming an r-t electrode is formed on the entire surface of the substrate 11 including the inside of the substrate 11 by 200~1.
The film is deposited to a thickness of 0.000 mm by vacuum evaporation or magnetron sputtering.
続いて、その上に、r−上絶縁層を形成するための絶縁
膜としてのシリコ:/ 窒化膜(SiNx ) 15を
、NH,とSiH4を主成分ガスとしてグロー放電法ま
たは光CVD法によ!00.3〜0.4μmの膜厚で堆
積させる。Subsequently, a silicon/nitride film (SiNx) 15 as an insulating film for forming an r-upper insulating layer is formed thereon by a glow discharge method or a photo-CVD method using NH and SiH4 as main component gases. ! The film is deposited to a thickness of 00.3 to 0.4 μm.
さらに、その上に、活性層を形成するための半導体層と
してのアモルファスシリコン層16を、5IH4ガスの
グロー放電法または光CVD法にょシ0.1〜0.3μ
mの膜厚で堆積させる。Furthermore, an amorphous silicon layer 16 as a semiconductor layer for forming an active layer is formed on the amorphous silicon layer 16 using a glow discharge method using 5IH4 gas or a photo-CVD method.
The film is deposited to a film thickness of m.
さらに、そのアモルファスシリコン層16上K、オーミ
ック層を形成するための高濃度不純物ドープ半導体層と
してのN+アそルファスシリコン、117を、SiH,
とPH,ガスのグロー放電法または光CVD法によfi
O,05〜0.1μmの膜厚で堆積させる。Further, on the amorphous silicon layer 16, N+ amorphous silicon 117 as a highly doped semiconductor layer for forming an ohmic layer is formed of SiH,
and PH, fi by gas glow discharge method or photo-CVD method.
The film is deposited to a thickness of 0.05 to 0.1 μm.
ここで、N+アモルファスシリコン層17および前記ア
モルファスシリコン層16.シリコン窒化膜15ならび
に金属層14の谷膜厚は前述の通りであるが、それらの
合計膜厚は溝13の深さに一致するようにする。Here, the N+ amorphous silicon layer 17 and the amorphous silicon layer 16. Although the valley thicknesses of the silicon nitride film 15 and the metal layer 14 are as described above, their total thickness is made to match the depth of the groove 13.
しかる後、有機溶済(アセトン)などによってレジスト
パターン12を除去する。すると、レジ、7. ) /
#ターン12上の金属層14.シリコン窒化Jlu15
.アモルファスシリコン層16およびN十アモルファス
シリコン層17も除去され(リフトオフされ)、金属層
14からN+アモルファスシリコン層′17までの多層
構造は、第1図(e)に示すように溝13内にのみ、r
−計電極14a、ゲート絶縁層15a、活性層16&お
よびオーミック層17aとして残る。ここで、オーミッ
ク層17aの表面は、周囲の基板11表面と同一平面と
なる。Thereafter, the resist pattern 12 is removed using an organic solution (acetone) or the like. Then, the cash register, 7. ) /
#Metal layer 14 on turn 12. Silicon nitride Jlu15
.. The amorphous silicon layer 16 and the N+ amorphous silicon layer 17 are also removed (lifted off), and the multilayer structure from the metal layer 14 to the N+ amorphous silicon layer '17 is left only in the trench 13, as shown in FIG. 1(e). , r
- Remains as meter electrode 14a, gate insulating layer 15a, active layer 16 & and ohmic layer 17a. Here, the surface of the ohmic layer 17a is flush with the surface of the surrounding substrate 11.
しかる後、 A/またはNiCr −Au またはTi
−Auよりなる金属層を基板11全面に真空蒸着また
はスフ9ツタなどによ勺被着し、それを所定の形状に加
工することによシ、前記第1図(C)に示すようにソー
ス電極18とドレイン電極19を、一部前記オーミツク
層17a上に重なるようにして基板11上に形成する。After that, A/or NiCr-Au or Ti
- A metal layer made of Au is deposited on the entire surface of the substrate 11 by vacuum evaporation or by vacuum deposition, and is processed into a predetermined shape to form a source as shown in FIG. 1(C). An electrode 18 and a drain electrode 19 are formed on the substrate 11 so as to partially overlap the ohmic layer 17a.
その後、ソース電極18とドレイン電極19間の不要の
オーミック層17aを第1図(d)に示すようにドライ
エツチング(CF4ガスを主成分とする)法により除去
する。以上でTPTが完成する。Thereafter, the unnecessary ohmic layer 17a between the source electrode 18 and the drain electrode 19 is removed by dry etching (using CF4 gas as the main component) as shown in FIG. 1(d). With the above steps, TPT is completed.
この完成したTPTを第2図に示し、(a)は平面図、
(b)は(&)のb−b線断面図である。このTPTは
、第2図(a)および前記第1図(d)に示すごとくソ
ース電極18と接続するように透明電極20を形成し、
TPTと透明電極を2次元に配置すると、液晶表示装置
の一部品(T F T /4ネル)として利用できる。This completed TPT is shown in Figure 2, where (a) is a plan view;
(b) is a sectional view taken along line bb of (&). This TPT has a transparent electrode 20 formed so as to be connected to the source electrode 18 as shown in FIG. 2(a) and FIG. 1(d),
When TPT and transparent electrodes are arranged two-dimensionally, it can be used as one component of a liquid crystal display device (T F T /4 channel).
(発明の効果)
以上詳細に説明したように、この発明によれば、絶縁物
基板に形成した溝にゲート電極、ゲート絶縁層、活性層
およびオーミック層1に埋め込むようにしたので、ソー
ス・ドレイン電極は平坦面に形成できる。したがって、
ドレイン電極の断線を防止でき、信頼性の高い素子を得
ることができる。(Effects of the Invention) As described in detail above, according to the present invention, the gate electrode, the gate insulating layer, the active layer, and the ohmic layer 1 are embedded in the groove formed in the insulating substrate. The electrode can be formed on a flat surface. therefore,
Disconnection of the drain electrode can be prevented and a highly reliable device can be obtained.
また、この発明によれば、絶縁物基板に溝を形成する際
にマスクとして用いたレジスト/4′ターンヲ利用して
リフトオフ法によシ、ゲート電極、r−ト絶縁層、活性
層およびオーミック層を溝内に形成したので、製造に際
して高価な装置は必要なく、通常の工程で製造でき、素
子コストが安価となる。Further, according to the present invention, the gate electrode, the r-to insulating layer, the active layer, and the ohmic layer can be formed by a lift-off method using the resist/4' turn used as a mask when forming the groove in the insulating substrate. Since it is formed in the groove, no expensive equipment is required for manufacturing, and the device can be manufactured using normal processes, resulting in low device costs.
第1図はこの発明の一実施例を示す工程断面図、第2図
はこの発明の一実施例による薄膜トランジスタを示す平
面図および断面図、第3図は従来の薄膜トランジスタの
平面図および断面図である。
11・・・透光性絶縁物基板、12・・・レジストパタ
ーン、13・・・溝、14・・・金属層、15・・・シ
リコン窒(IJi、 16・・・アモルファスシリコン
層、17・・・N”アモルファスシリコン層、14 a
・・・ゲート電極、15a・・・ゲート絶縁層、16a
・・・活性層、17a・・・オーミック層、18・・・
ソース電極、19・・・ドレイン電極。FIG. 1 is a process sectional view showing an embodiment of the present invention, FIG. 2 is a plan view and a sectional view showing a thin film transistor according to an embodiment of the invention, and FIG. 3 is a plan view and a sectional view of a conventional thin film transistor. be. DESCRIPTION OF SYMBOLS 11... Transparent insulator substrate, 12... Resist pattern, 13... Groove, 14... Metal layer, 15... Silicon nitride (IJi), 16... Amorphous silicon layer, 17... ...N” amorphous silicon layer, 14 a
...Gate electrode, 15a...Gate insulating layer, 16a
...Active layer, 17a... Ohmic layer, 18...
Source electrode, 19... drain electrode.
Claims (2)
たゲート電極、ゲート絶縁層、活性層およびオーミック
層と、 (c)このオーミック層に一部重なり合うようにして前
記基板表面に形成されたソース・ドレイン電極とを具備
してなる薄膜トランジスタ。(1) (a) An insulating substrate with a groove formed in a part of its surface; (b) a gate electrode, a gate insulating layer, an active layer, and an ohmic layer embedded in the groove of this substrate in order from the bottom; (c) A thin film transistor comprising source/drain electrodes formed on the surface of the substrate so as to partially overlap the ohmic layer.
ンをマスクとして溝を形成する工程と、 (b)その後、前記レジストパターンを残したまま、前
記溝内を含む基板上の全面に、ゲート電極形成用の金属
層、ゲート絶縁層形成用の絶縁膜、活性層形成用の半導
体層、オーミック層形成用の高濃度不純物ドープ半導体
層を順次、全体の厚さが前記溝の深さと一致するように
形成する工程と、 (c)その後、前記レジストパターンを除去し、同時に
その上の前記金属層、絶縁膜、半導体層および高濃度不
純物ドープ半導体層を除去することにより、金属層から
高濃度不純物ドープ半導体層までの多層構造を前記基板
の溝内にのみ残す工程と、 (d)その後、溝内に残存する高濃度不純物ドープ半導
体層上に一部重なるようにしてソース・ドレイン電極を
前記基板上に形成する工程とを具備してなる薄膜トラン
ジスタの製造方法。(2) (a) Forming a groove on a part of the surface of the insulating substrate using a resist pattern as a mask; (b) After that, while leaving the resist pattern, the entire surface of the substrate including the inside of the groove is formed. , a metal layer for forming a gate electrode, an insulating film for forming a gate insulating layer, a semiconductor layer for forming an active layer, and a highly impurity-doped semiconductor layer for forming an ohmic layer are sequentially formed so that the total thickness is equal to the depth of the groove. (c) then removing the resist pattern and simultaneously removing the metal layer, insulating film, semiconductor layer and heavily impurity-doped semiconductor layer thereon; (d) leaving the multilayer structure up to the highly impurity-doped semiconductor layer only in the groove of the substrate; (d) then forming source/drain electrodes so as to partially overlap the highly impurity-doped semiconductor layer remaining in the groove; forming a thin film transistor on the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3187786A JPS62190762A (en) | 1986-02-18 | 1986-02-18 | Thin-film transistor and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3187786A JPS62190762A (en) | 1986-02-18 | 1986-02-18 | Thin-film transistor and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62190762A true JPS62190762A (en) | 1987-08-20 |
Family
ID=12343263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3187786A Pending JPS62190762A (en) | 1986-02-18 | 1986-02-18 | Thin-film transistor and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62190762A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100368917C (en) * | 2005-09-27 | 2008-02-13 | 广辉电子股份有限公司 | Array base plate for liquid crystal display and producing method thereof |
JP2008098606A (en) * | 2006-10-14 | 2008-04-24 | Au Optronics Corp | Thin film transistor array substrate of liquid crystal display device and method of manufacturing same |
US7786479B2 (en) | 2005-08-04 | 2010-08-31 | Au Optronics Corp. | Array substrate for LCD and method of fabrication thereof |
US8216891B2 (en) | 2006-10-14 | 2012-07-10 | Au Optronics Corp. | LCD TFT array plate and fabricating method thereof |
-
1986
- 1986-02-18 JP JP3187786A patent/JPS62190762A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7786479B2 (en) | 2005-08-04 | 2010-08-31 | Au Optronics Corp. | Array substrate for LCD and method of fabrication thereof |
CN100368917C (en) * | 2005-09-27 | 2008-02-13 | 广辉电子股份有限公司 | Array base plate for liquid crystal display and producing method thereof |
JP2008098606A (en) * | 2006-10-14 | 2008-04-24 | Au Optronics Corp | Thin film transistor array substrate of liquid crystal display device and method of manufacturing same |
US8216891B2 (en) | 2006-10-14 | 2012-07-10 | Au Optronics Corp. | LCD TFT array plate and fabricating method thereof |
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