JPS62190762A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To form source-drain electrodes in a plane, to prevent disconnections and to obtain an element having high reliability by burying a gate electrode, a gate insulating film, an active layer and an ohmic layer into a groove shaped to an insulator substrate. CONSTITUTION:A resist pattern 12 is formed onto a light-transmitting insulator substrate 11. A groove 13 is shaped to one part of the surface of the substrate 11, using the resist pattern 12 as a mask. An N<+> amorphous silicon layer 17, an amorphous silicon layer 16, an silicon nitride film 15 and a metallic layer 14 are applied or deposited so that total film thickness thereof coincides with the depth of the groove 13. The resist pattern 12 is removed by an organic solvent. Accordingly, multilayer structure up to the N<+> amorphous silicon layer 17 from the metallic layer 14 is left as a gate electrode 14a, a gate insulator 15a, an active layer 16a and an ohmic layer 17a only in the groove 13, and the surface of the ohmic layer 17a is shaped in the same plane as the surface of the peripheral substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a thin film transistor (hereinafter abbreviated as TPT) and a manufacturing method thereof.

(Conventional technology) FIG. 3(a) shows a plan view and a cross-sectional view of a conventional TPT.

Shown in (b). As for the manufacturing method of this TPT, first,
An r-to-electrode 2 is formed on a transparent insulating substrate 1 such as a glass substrate or a quartz substrate. This gate electrode 2 is made of nichrome (NiCr), tungsten (W), molybdenum (M
After forming a metal layer made of O) or chromium (Cr) or the like to a thickness of 200 to 1000 layers on the substrate 1 by vacuum evaporation method, snow ivy method, etc., the metal layer is deposited in a predetermined manner. Polymers are formed by processing into patterns. next,
On top of them, a silicon nitride film (SiNx) for forming the r-upper insulating layer 3 is deposited with a film thickness of 0.3 to 0.6 μm using a glow discharge method using NH8 and Si as main component gases. Deposit with. Furthermore, an amorphous silicon layer for forming the active layer 4 is deposited thereon to a thickness of 0.1 to 0.3 .mu.m by a glow discharge method using SiH4 gas. After that, by removing the amorphous silicon layer and the silicon nitride film other than the part that will become the TPT and turning it into an island shape, the remaining island-like silicon nitride film pattern is formed into the amorphous silicon layer pattern described above.
- forming the insulating layer 3 and the active layer 4; Thereafter, a drain electrode 5 and a source electrode 6 made of an Al layer having a thickness of 0.8 to 1.0 μm are formed by vacuum evaporation and processing of A/ so as to partially overlap the active layer 4. That's all TPT
is completed.

This TPT is then used as a TFT array of a liquid crystal display device by forming a transparent electrode 7 so as to be connected to the source electrode 6, and arranging the TPT and the transparent electrode two-dimensionally.

(Problems to be Solved by the Invention') However, in the above conventional technique, there is a step difference of 0.6 to 0.9 μm depending on the film thickness of the r-upper insulating layer 3 and the active layer 4, as shown in FIG. ), there was a problem in that the drain electrode 5 was easily broken during processing. In order to prevent this, it is possible to increase the thickness of the drain electrode 5 or widen the electrode width, but these would increase the dimensions of the TPT element itself. It becomes difficult to create a TPT panel that has been arranged.

The present invention has been made in view of the above points, and an object thereof is to provide a TPT and a method for manufacturing the same that can prevent disconnection of the drain electrode.

(Another Means to Solve the Problems) In the present invention, a groove is formed in an insulating substrate, and a gate electrode, a P-to insulating layer, an active layer, and an ohmic layer are embedded in the groove.

Further, in the present invention, after forming a groove in the insulating substrate, the gate electrode and the r-) insulating layer are formed while leaving the resist/arm turn as a mask for forming the groove.

A metal layer, an insulating film, a semiconductor layer, and a highly impurity-doped semiconductor layer for forming an active layer and an ohmic layer are formed on the entire surface, and then the resist groove is removed.

(Function) When the resist pattern is removed, unnecessary portions of the metal layer, insulating film, semiconductor layer, and highly impurity-doped semiconductor layer on the resist pattern are also removed, resulting in a multilayer structure from the metal layer to the highly impurity-doped semiconductor layer. remains only in the groove of the substrate. That is, the r-to-electrode, the groove insulating layer, the active layer, and the ohmic layer are formed by a lift-off method using a nine-turn resistor as a mask during groove formation.

Further, when the gate electrode+l'l' insulating layer, active layer, and ohmic layer are buried in the trench in this manner, the surface state immediately before forming the drain electrode and source electrode becomes flat.

(Example) An embodiment of the present invention will be described below with reference to FIG.

5. First, as shown in FIG. 1 (&), a predetermined resist pattern 12 is formed on a transparent insulating substrate 11 made of a glass substrate, a quartz substrate, or the like. Then, as shown in the figure, using the resist pattern 12 as a mask, a hydrofluoric acid (HF)-based etching solution is used to remove the etchant to a depth of 0.5 to 0.
．． A groove 13 of 9 μm is formed in a part of the surface of the substrate 11.

Next, as shown in FIG. 1(b), the grooves 1 are formed while leaving the resist pattern 12 as a mask for forming the grooves.
A metal layer 14 made of nichrome (NiCr), chromium (Cr), or tungsten (W') for forming an r-t electrode is formed on the entire surface of the substrate 11 including the inside of the substrate 11 by 200~1.
The film is deposited to a thickness of 0.000 mm by vacuum evaporation or magnetron sputtering.

Subsequently, a silicon/nitride film (SiNx) 15 as an insulating film for forming an r-upper insulating layer is formed thereon by a glow discharge method or a photo-CVD method using NH and SiH4 as main component gases. ! The film is deposited to a thickness of 00.3 to 0.4 μm.

Furthermore, an amorphous silicon layer 16 as a semiconductor layer for forming an active layer is formed on the amorphous silicon layer 16 using a glow discharge method using 5IH4 gas or a photo-CVD method.
The film is deposited to a film thickness of m.

Further, on the amorphous silicon layer 16, N+ amorphous silicon 117 as a highly doped semiconductor layer for forming an ohmic layer is formed of SiH,
and PH, fi by gas glow discharge method or photo-CVD method.
The film is deposited to a thickness of 0.05 to 0.1 μm.

Here, the N+ amorphous silicon layer 17 and the amorphous silicon layer 16. Although the valley thicknesses of the silicon nitride film 15 and the metal layer 14 are as described above, their total thickness is made to match the depth of the groove 13.

Thereafter, the resist pattern 12 is removed using an organic solution (acetone) or the like. Then, the cash register, 7. ) /
#Metal layer 14 on turn 12. Silicon nitride Jlu15
．． The amorphous silicon layer 16 and the N+ amorphous silicon layer 17 are also removed (lifted off), and the multilayer structure from the metal layer 14 to the N+ amorphous silicon layer '17 is left only in the trench 13, as shown in FIG. 1(e). , r
- Remains as meter electrode 14a, gate insulating layer 15a, active layer 16 & and ohmic layer 17a. Here, the surface of the ohmic layer 17a is flush with the surface of the surrounding substrate 11.

After that, A/or NiCr-Au or Ti
- A metal layer made of Au is deposited on the entire surface of the substrate 11 by vacuum evaporation or by vacuum deposition, and is processed into a predetermined shape to form a source as shown in FIG. 1(C). An electrode 18 and a drain electrode 19 are formed on the substrate 11 so as to partially overlap the ohmic layer 17a.

Thereafter, the unnecessary ohmic layer 17a between the source electrode 18 and the drain electrode 19 is removed by dry etching (using CF4 gas as the main component) as shown in FIG. 1(d). With the above steps, TPT is completed.

This completed TPT is shown in Figure 2, where (a) is a plan view;
(b) is a sectional view taken along line bb of (&). This TPT has a transparent electrode 20 formed so as to be connected to the source electrode 18 as shown in FIG. 2(a) and FIG. 1(d),
When TPT and transparent electrodes are arranged two-dimensionally, it can be used as one component of a liquid crystal display device (T F T /4 channel).

(Effects of the Invention) As described in detail above, according to the present invention, the gate electrode, the gate insulating layer, the active layer, and the ohmic layer 1 are embedded in the groove formed in the insulating substrate. The electrode can be formed on a flat surface. therefore,
Disconnection of the drain electrode can be prevented and a highly reliable device can be obtained.

Further, according to the present invention, the gate electrode, the r-to insulating layer, the active layer, and the ohmic layer can be formed by a lift-off method using the resist/4' turn used as a mask when forming the groove in the insulating substrate. Since it is formed in the groove, no expensive equipment is required for manufacturing, and the device can be manufactured using normal processes, resulting in low device costs.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention, FIG. 2 is a plan view and a sectional view showing a thin film transistor according to an embodiment of the invention, and FIG. 3 is a plan view and a sectional view of a conventional thin film transistor. be. DESCRIPTION OF SYMBOLS 11... Transparent insulator substrate, 12... Resist pattern, 13... Groove, 14... Metal layer, 15... Silicon nitride (IJi), 16... Amorphous silicon layer, 17... ...N” amorphous silicon layer, 14 a
...Gate electrode, 15a...Gate insulating layer, 16a
...Active layer, 17a... Ohmic layer, 18...
Source electrode, 19... drain electrode.

Claims (2)

[Claims] (1) (a) An insulating substrate with a groove formed in a part of its surface; (b) a gate electrode, a gate insulating layer, an active layer, and an ohmic layer embedded in the groove of this substrate in order from the bottom; (c) A thin film transistor comprising source/drain electrodes formed on the surface of the substrate so as to partially overlap the ohmic layer. (2) (a) Forming a groove on a part of the surface of the insulating substrate using a resist pattern as a mask; (b) After that, while leaving the resist pattern, the entire surface of the substrate including the inside of the groove is formed. , a metal layer for forming a gate electrode, an insulating film for forming a gate insulating layer, a semiconductor layer for forming an active layer, and a highly impurity-doped semiconductor layer for forming an ohmic layer are sequentially formed so that the total thickness is equal to the depth of the groove. (c) then removing the resist pattern and simultaneously removing the metal layer, insulating film, semiconductor layer and heavily impurity-doped semiconductor layer thereon; (d) leaving the multilayer structure up to the highly impurity-doped semiconductor layer only in the groove of the substrate; (d) then forming source/drain electrodes so as to partially overlap the highly impurity-doped semiconductor layer remaining in the groove; forming a thin film transistor on the substrate.