WO2019242384A1 - Backplane structure of display panel and preparation method therefor, and top-emitting display panel - Google Patents

Abstract

A top-emitting display panel (2000), comprising a substrate (10) having a TFT drive array, an insulating layer (70), a circuit layer (60), a flat layer (50), a pixel electrode (200), and a pixel definition layer (300). The circuit layer (60) is embedded in the insulating layer (70), and the upper surface of the circuit layer (60) is substantially flush with the upper surface of the insulating layer (70). The top-emitting display panel (2000) can avoid the problem that the surface of the pixel electrode (200) is uneven due to a driving circuit, so as to effectively improve the luminous uniformity of the top-emitting display panel (2000), and improve the display effect.

Description

Back panel structure of display panel, preparation method thereof and top emission display panel

Related applications

This application requires a Chinese patent application filed with the Chinese Patent Office on July 13, 2018, with application number 201810776556.8, and the invention name is "Display Panel Backplane Structure, Method of Making and Top Emission Display Panel", and 06.2018 The priority of a Chinese patent application filed with the Chinese Patent Office on May 19, with an application number of 201810628250.8, and the invention name is "top emission display device and manufacturing method thereof", the entire contents of which are incorporated herein by reference.

Technical field

The present invention relates to the technical field of organic light-emitting electronic devices, and in particular, to a back panel structure of a display panel, a preparation method thereof, and a top emission display panel.

Background technique

Organic light-emitting diodes (OLEDs) have become one of the main research directions of displays at present due to their advantages such as self-emission, fast response, wide viewing angle, high brightness, and thinness. OLED displays are mainly made by solution processing. They have the advantages of low cost, high production capacity, and easy realization of large sizes, and have become an important direction for the development of display technology in the future. Among them, printing technology is considered to be the most effective way to achieve OLED's low cost and large area full color display.

Because OLED display panels need to use more complicated driver circuits for compensation, a large part of their TFT backplanes are covered by the driver circuits, resulting in a smaller aperture ratio of display panels with bottom-emitting device structures, which leads to increased power consumption Large, shortened device life. The use of the top emission device structure can greatly increase the aperture ratio of the display panel, avoiding problems such as increased power consumption and shortened device life caused by the aperture ratio being too small.

However, when the top emission device is prepared by a printing process, the flatness requirements of the pixel electrode are much higher than those of the evaporation type device. The pixel electrode of a top-emitting display panel covers a driving circuit, and the driving circuit is difficult to planarize during the pre-production process. Therefore, the flatness of the surface of the pixel electrode is poor, resulting in uneven emission of the top-emitting OLED.

Summary of the Invention

Based on this, it is necessary to provide a top-emission type display panel with a flat pixel electrode surface.

In addition, the present application also provides a display panel backplane structure and a manufacturing method thereof.

A display panel backplane structure includes:

A substrate with a TFT driving array;

An insulating layer disposed on the substrate;

A circuit layer buried in the insulating layer, and an upper surface of the circuit layer is substantially flush with an upper surface of the insulating layer;

A flat layer is disposed on the insulating layer and the circuit layer.

In one embodiment, the insulating layer includes:

A first layer provided on the substrate, a gate embedded in the first layer, a surface of the gate far from the substrate being substantially flush with a surface of the first layer far from the substrate;

A second layer provided on the first layer, an active layer embedded in the second layer, a surface of the active layer far from the first layer and a distance of the second layer from the first layer The surface of the layer is substantially flush; and

A third layer provided on the second layer, the third layer is embedded with a circuit layer, the circuit layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are far from the surface of the second layer Are substantially flush with the surface of the third layer away from the second layer, and the source and drain electrodes are at least partially in contact with the active layer,

The flat layer is provided with a flat layer opening penetrating the flat layer to expose at least part of the drain.

In one embodiment, the circuit layer is further provided with at least one auxiliary electrode, and a surface of each of the auxiliary electrodes remote from the second layer is substantially flush with a surface of the third layer remote from the second layer. .

In one embodiment, the circuit layer includes source and drain electrode wiring.

In one embodiment, the circuit layer further includes an auxiliary electrode wiring.

In one embodiment, the insulating layer is a gate insulating layer or an etch stop layer.

A method for preparing a display panel backplane structure includes the following steps:

Providing a substrate with a TFT drive array;

Forming an insulating layer on the substrate;

Patterning the insulating layer to form an insulating layer opening on the insulating layer;

Depositing a metal material in the opening of the insulating layer so that the upper surface of the metal material is substantially flush with the upper surface of the insulating layer to form a circuit layer in the insulating layer;

A flat layer is made on the insulating layer and the circuit layer.

In one embodiment, forming the insulating layer on the substrate further includes:

Forming a first layer of the insulating layer on the substrate;

A first layer opening is formed in the first layer, and a gate material is deposited in the first layer opening to form a gate, so that the surface of the gate away from the substrate and the first layer away from the substrate The surface is substantially flush;

Forming a second layer of an insulating layer on a surface of the gate and the first layer remote from the substrate;

A second layer opening is formed on the second layer, and an active material is deposited in the second layer opening to form an active layer, so that the active layer is far from the surface of the first layer and the second layer. The surface of the layer far from the first layer is substantially flush;

Forming a third layer of an insulating layer on a surface of the active layer and the second layer remote from the first layer;

A circuit layer opening penetrating the third layer is formed in the third layer, and the circuit layer opening includes a source opening and a drain opening, respectively, and at least a part of the source opening and the drain opening is exposed. In the source layer, a metal material is deposited in the source opening and the drain opening to form a source and a drain, so that the surfaces of the source and drain away from the second layer are separated from the surface of the second layer. A surface of the three layers far from the second layer is substantially flush, and the source and drain electrodes are at least partially in contact with the active layer; and

Forming the flat layer on a surface of the source, drain, and the third layer remote from the second layer, and forming a flat layer opening penetrating the flat layer in the flat layer, the flat layer opening being at least A portion of the drain is exposed.

In one embodiment, the method of forming a first layer opening in the first layer, and depositing a gate material in the first layer opening to form a gate is:

Forming a patterned first photoresist layer on a surface of the first layer remote from the substrate, and etching the first layer at a position corresponding to the patterned area of the first photoresist layer to form the first A layer of openings

A gate material is deposited on a surface of the first photoresist layer away from the first layer and in the opening of the first layer to a thickness at which the gate material is deposited to the same depth as the opening of the first layer. The first photoresist layer and the gate material deposited on the surface of the first photoresist layer are peeled off, and the gate material deposited in the opening of the first layer forms a gate.

In one embodiment, the method of forming a second layer opening in the second layer, and depositing an active material in the second layer opening to form an active layer is:

Forming a patterned second photoresist layer on a surface of the second layer remote from the first layer, and etching the position of the second layer corresponding to the patterned area of the second photoresist layer to form the Mentioned second layer opening;

An active material is deposited on a surface of the second photoresist layer away from the second layer and in the opening of the second layer to a thickness where the thickness of the active material is the same as the depth of the opening of the second layer. The second photoresist layer and the active material deposited on the surface of the second photoresist layer are peeled off, and the active material deposited in the opening of the second layer forms an active layer.

In one embodiment, the circuit layer openings penetrating through the third layer are respectively formed in the third layer, and the circuit layer openings respectively include a source opening and a drain opening, and within the source opening and A method of depositing a metal material in the drain opening to form a source and a drain is:

Forming a patterned third photoresist layer on a surface of the third layer remote from the second layer, and etching the positions of the third layer corresponding to the patterned areas of the third photoresist layer to form the respective portions The source opening and the drain opening;

A metal material is deposited on a surface of the third photoresist layer away from the third layer, in the source opening and the drain opening to a thickness at which the metal material is deposited to be the same as the thickness of the third layer Removing the third photoresist layer and the metal material deposited on the surface of the third photoresist layer, the metal material deposited in the source opening forms a source, and the metal deposited in the drain opening The material forms a drain.

In one embodiment, the method for forming a circuit layer in the third layer further includes the following steps:

Forming at least one auxiliary electrode opening through the third layer in the third layer, and depositing a metal material in each of the auxiliary electrode openings to form an auxiliary electrode so that each of the auxiliary electrodes is far from the second layer The surface of is substantially flush with the surface of the third layer away from the second layer.

In one embodiment, the method of forming at least one auxiliary electrode opening through the third layer in the third layer, and depositing a metal material in each of the auxiliary electrode openings to form the auxiliary electrode is:

Etching the position of the third layer corresponding to the patterned region of the third photoresist layer, and further forming at least one auxiliary electrode opening;

A metal material is deposited in each of the auxiliary electrode openings, the metal material is deposited to a thickness equal to the thickness of the third layer, and the metal material deposited in the auxiliary electrode openings forms an auxiliary electrode.

In one embodiment, the method for patterning the insulating layer includes the following steps:

Making a mask layer on the insulating layer;

Patterning the mask layer;

With the mask layer subjected to the patterning process as a mask, etching is performed on a portion of the insulating layer not covered by the mask layer to form the insulating layer opening.

In one embodiment, the method for depositing a metal material in the opening of the insulating layer includes the following steps:

On the side of the insulating layer that is covered with the patterned masking layer, a metal material is deposited on the insulating layer opening and at least a part of the masking layer surrounding the opening of the insulating layer, so that the upper surface of the metal material is The surface is substantially flush with the upper surface of the insulating layer;

The mask layer is peeled off to remove excess metal material surrounding the opening of the insulating layer, and the metal material in the opening of the insulating layer is retained to form the circuit layer.

In one embodiment, the step of patterning the mask layer includes:

Provide a design pattern including source and drain electrode wiring, develop the mask layer according to the design pattern, and remove a part of the mask layer to form a mask opening area.

In one embodiment, the step of patterning the mask layer includes:

Provide a design pattern including source, drain electrode wiring, and auxiliary electrode wiring, develop the mask layer according to the design pattern, and remove a part of the mask layer to form a mask opening area.

A top emission display panel includes a display panel backplane structure and pixel electrodes and pixel definition layers provided on the display panel backplane structure. The display panel backplane structure includes:

A substrate with a TFT driving array;

An insulating layer disposed on the substrate;

A circuit layer buried in the insulating layer, and an upper surface of the circuit layer is substantially flush with an upper surface of the insulating layer;

A flat layer is disposed on the insulating layer and the circuit layer.

In the above top emission type display panel, the circuit layer is buried in the insulating layer, and the upper surface of the circuit layer is substantially flush with the upper surface of the insulating layer, so that the flat layer can be evenly disposed on the insulating layer and the circuit layer. It plays a role of flattening, thereby effectively improving the flatness of the surface of the pixel electrode, and further improving the uniformity of light emission of the top emission display panel.

In one embodiment, the insulating layer includes:

A first layer provided on the substrate, a gate embedded in the first layer, a surface of the gate far from the substrate being substantially flush with a surface of the first layer far from the substrate;

A second layer provided on the first layer, an active layer embedded in the second layer, a surface of the active layer far from the first layer and a distance of the second layer from the first layer The surface of the layer is substantially flush; and

A third layer provided on the second layer, the third layer is embedded with a circuit layer, the circuit layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are far from the surface of the second layer Are substantially flush with the surface of the third layer away from the second layer, and the source and drain electrodes are at least partially in contact with the active layer,

The flat layer is provided with a flat layer opening penetrating the flat layer to expose at least part of the drain,

The pixel electrode is disposed in the flat layer opening and on the flat layer, and the pixel electrode is in contact with the drain,

The pixel definition layer is provided on the flat layer, and the pixel definition layer is provided with a sub-pixel opening to expose at least a part of the pixel electrode.

In one embodiment, the top emission display panel further includes a sub-pixel, and the sub-pixel is disposed in the sub-pixel opening of the pixel definition layer.

In the above top-emitting display panel, the gate and the first layer form a flat surface, the active layer and the second layer form a flat surface, and the source and drain layers form a flat surface, so that the entire substrate surface is completed after the TFT driving circuit process is completed. The flat surface is formed to avoid the problem of uneven surface of the pixel electrode due to the driving circuit in the top emission type display panel, effectively improving the light emission uniformity of the top emission type display panel, thereby improving the display effect.

BRIEF DESCRIPTION OF THE DRAWINGS

1 is a schematic structural diagram of a top emission display panel according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram corresponding to step S110;

FIG. 3 is a schematic structural diagram corresponding to step S112;

4 and 5 are schematic structural diagrams corresponding to step S113;

FIG. 6 is a schematic structural diagram corresponding to step S115;

7 and 8 are schematic structural diagrams corresponding to step S116;

FIG. 9 is a schematic structural diagram corresponding to step S118;

FIG. 10 is a schematic structural diagram corresponding to step S119;

FIG. 11 is a schematic structural diagram corresponding to step S120;

FIG. 12 is a schematic structural diagram corresponding to step S121;

13 is a schematic structural diagram of a top emission display panel according to another embodiment of the present invention;

14 is a schematic diagram of a manufacturing structure of an insulating layer in a manufacturing process of the top emission display panel shown in FIG. 13;

FIG. 15 is a schematic diagram of a manufacturing structure of a mask layer in the manufacturing process of the top emission display panel shown in FIG. 13; FIG.

FIG. 16 is a schematic diagram of a manufacturing structure of an insulating layer opening in an insulating layer during a manufacturing process of the top emission display panel shown in FIG. 13; FIG.

FIG. 17 is a schematic diagram of a manufacturing structure of a whole-side deposited metal material during the manufacturing process of the top emission display panel shown in FIG. 13; FIG.

FIG. 18 is a schematic diagram of a manufacturing structure of a peeling mask layer during the manufacturing process of the top emission display panel shown in FIG. 13; FIG.

19 is a schematic diagram of a manufacturing structure of a flat layer in the manufacturing process of the top emission display panel shown in FIG. 13;

FIG. 20 is a schematic diagram of a manufacturing structure of a pixel electrode in a manufacturing process of the top emission display panel shown in FIG. 13.

detailed description

In order to facilitate understanding of the present invention, a more comprehensive description of the present invention will be given below, and preferred embodiments of the present invention will be given. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and comprehensive understanding of the disclosure of the present invention.

It should be noted that when an element is referred to as being “fixed to” another element, it may be directly on the other element or there may be a centered element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or intervening elements may be present concurrently.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the present invention is only for the purpose of describing specific embodiments, and is not intended to limit the present invention. The term "and / or" as used herein includes any and all occurrences of one or more of the associated listed items.

Referring to FIG. 1, a top emission display panel 1000 according to an embodiment of the present invention includes a display panel backplane structure 100 and a pixel electrode 200 and a pixel definition layer 300 disposed on the display panel backplane structure 100. The display panel backplane structure 100 includes a substrate 10, a first layer 20, a gate 22, a second layer 30, an active layer 32, a third layer 40, a source 42, a drain 44, an auxiliary electrode 46, and a flat layer. 50. Wherein, in this embodiment, the first layer 20, the second layer 30, and the third layer 40 constitute an insulating layer, and may also be provided to function as a buffer layer, an insulating layer, and a protective layer, respectively.

Further, the substrate 10 has a TFT driving array for driving light-emitting components to realize image display.

Further, the first layer 20 is laminated on the substrate 10, and the gate 22 is embedded in the first layer 20. The surface of the gate 22 far from the substrate 10 and the surface of the first layer 20 far from the substrate 10 are substantially flush with each other to form a flat surface. .

It should be noted that the surface of the gate 22 that is far from the substrate 10 and the surface of the first layer 20 that is far from the substrate 10 mean that the height difference between the upper surface of the gate 22 and the upper surface of the first layer 20 does not exceed the first 1% of the thickness of the layer 20.

Further, the upper surface of the gate electrode 22 is flush with the upper surface of the first layer 20.

The material of the first layer 20 is selected from at least one of silicon oxide (SiO _x ) and nitrogen silicide (SiN _x ). The first layer 20 can function as a buffer layer.

It can be understood that, in other embodiments, the material of the first layer 20 may also be any existing material that can be used as a buffer layer.

Further, the material of the gate electrode 22 is a conductive metal. In this embodiment, the material of the gate electrode 22 is selected from at least one of a copper-molybdenum alloy, aluminum, and an aluminum-molybdenum alloy.

It can be understood that the material of the gate electrode 22 may also be any existing material that can be used as the gate electrode 22.

In this embodiment, the surface of the gate electrode 22 near the substrate 10 is located in the first layer 20, as shown in FIG. 1.

It can be understood that, in other embodiments, the surface of the gate electrode 22 near the substrate 10 may be substantially flush with the surface of the first layer 20 near the substrate 10 to form a flat surface.

Further, the second layer 30 is stacked on the first layer 20. An active layer 32 is embedded in the second layer 30. The surface of the active layer 32 far from the first layer 20 and the surface of the second layer 30 far from the first layer 20 are substantially flush, forming a flat surface.

It should be noted that the surface of the active layer 32 far from the first layer 20 and the surface of the second layer 30 far from the first layer 20 are substantially flush with each other, which means that the upper surface of the active layer 32 and the upper surface of the second layer 30 The height difference does not exceed 1% of the thickness of the second layer 30.

Further, the upper surface of the active layer 32 is flush with the upper surface of the second layer 30.

In this embodiment, the surface of the active layer 32 near the first layer 20 is located in the second layer 30, as shown in FIG. 1.

The material of the second layer 30 is selected from at least one of silicon oxide (SiO _x ) and nitrogen silicide (SiN _x ), and the second layer 30 can function as an insulating layer.

It can be understood that, in other embodiments, the material of the second layer 30 may be other gate insulating materials.

Further, the material of the active layer 32 is a semiconductor material, such as a metal oxide semiconductor.

Further, the third layer 40 is stacked on the second layer 30. The third layer 40 is embedded with a source electrode 42, a drain electrode 44 and at least one auxiliary electrode 46.

It is understood that the auxiliary electrode 46 may be omitted.

Further, the material of the third layer 40 is selected from at least one of silicon oxide (SiO _x ) and nitrogen silicide (SiN _x ), and the third layer 40 may function as a protective layer.

It can be understood that, in other embodiments, the material of the third layer 40 may also be any existing material that can be used as a protective layer.

Further, the material of the source electrode 42, the drain electrode 44 and the auxiliary electrode 46 is a conductive metal. In this embodiment, a material of the source electrode 42, the drain electrode 44, and the auxiliary electrode 46 is selected from at least one of a copper molybdenum alloy, aluminum, and an aluminum molybdenum alloy.

Further, the surfaces of the source electrode 42, the drain electrode 44, and the auxiliary electrode 46 far from the second layer 30 are substantially flush with the surfaces of the third layer 40 far from the second layer 30, forming a flat surface.

It should be noted that the surfaces of the source electrode 42, the drain electrode 44, and the auxiliary electrode 46 that are far from the second layer 30 are substantially flush with the surface of the third layer 40 that is far from the second layer 30. This means that the upper surface of the source electrode 42, The height difference between the upper surface of the drain electrode 44, the upper surface of the auxiliary electrode 46, and the upper surface of the third layer 40 does not exceed 1% of the thickness of the third layer 40.

Further, the upper surface of the source electrode 42, the upper surface of the drain electrode 44, and the upper surface of the auxiliary electrode 46 are all flush with the upper surface of the third layer 40.

Further, both the source electrode 42 and the drain electrode 44 are at least partially in contact with the active layer 32. The auxiliary electrode 46 is connected to a power circuit.

Further, the flat layer 50 is stacked on the third layer 40. The flat layer 50 is provided with a flat layer opening 52 penetrating the flat layer 50 to expose at least part of the drain electrode 44 as shown in FIG. 12.

Further, the flat layer 50 is an organic photoresist layer with a thickness of 1 μm and plays a flat role.

Further, the pixel electrode 200 is disposed in the flat layer opening 52 and on the flat layer 50. The pixel electrode 200 is in contact with the drain 44.

Further, the pixel electrode 200 is a conductive film layer, and the conductive film layer is a reflective conductive film layer, such as a highly conductive metal thin film such as aluminum, silver, and aluminum-silver alloy; or a reflective conductive layer including a multilayer structure such as ITO, Ag, and ITO. film.

Further, the pixel definition layer 300 is disposed on the flat layer 50, and the pixel definition layer 300 is provided with a sub-pixel opening (not shown) to expose a portion of the pixel electrode 200.

In this embodiment, all the pixel electrodes 200 are exposed through the sub-pixel openings.

Further, the thickness of the pixel definition layer 300 is 800 nm to 1500 nm, which is used to define the size of the light-emitting area of each pixel, and the surface is liquid-repellent, preventing the ink from overflowing and causing color mixing during the printing process.

In the above top-emitting display panel, the gate 22 and the first layer 20 form a flat surface, the active layer 32 and the second layer 30 form a flat surface, and the source 42, the drain 44, the auxiliary electrode 46, and the third layer 40 form a flat surface. The surface makes the entire substrate surface a flat surface after the TFT driving circuit process is completed, avoiding the problem of uneven surface of the pixel electrode caused by the driving circuit of the top emission display panel, effectively improving the light emitting uniformity of the top emission display panel, thereby improving display effect.

Please refer to FIGS. 1 to 12. A method for manufacturing a top emission display panel according to an embodiment includes the following steps:

S110: A substrate 10 is provided, and a first layer 20 is formed on the substrate 10, as shown in FIG.

Specifically, materials such as silicon oxide and nitrogen silicide are deposited on the substrate 10 to form the first layer 20.

S112: A first layer opening 23 is formed in the first layer 20.

Specifically, a patterned first photoresist layer 21 is formed on the surface of the first layer 20 away from the substrate 10, and the patterned area of the first layer 20 corresponding to the first photoresist layer 21 is etched to form a first layer opening 23 ,As shown in Figure 3.

Specifically, a photoresist material is coated on the surface of the first layer 20 away from the substrate 10 and subjected to photolithography to form a patterned first photoresist layer 21.

S113: The gate material 25 is deposited in the first layer opening 23 to form the gate 22, so that the surface of the gate 22 far from the substrate 10 and the surface of the first layer 20 far from the substrate 10 are substantially flush.

Specifically, the gate material 25 is deposited on the surface of the first photoresist layer 21 away from the first layer 20 and in the first layer opening 23 to a thickness of the gate material 25 that is the same as the depth of the first layer opening 23, as shown in FIG. 4 shown.

The first photoresist layer 21 and the gate material 25 deposited on the surface of the first photoresist layer 21 are peeled off, and the gate material deposited in the first layer opening 23 forms the gate 22 as shown in FIG. 5.

It can be understood that the gate electrode 22 is the gate material 25 deposited in the first layer opening 23.

S114: A second layer 30 is formed on a surface of the gate 22 and the first layer 20 away from the substrate 10.

Specifically, a gate insulating material is deposited on a surface of the gate 22 and the first layer 20 away from the substrate 10 to form a second layer 30.

S115: A second layer opening 33 is formed in the second layer 30.

Specifically, a patterned second photoresist layer 31 is formed on the surface of the second layer 30 away from the first layer 20, and the position of the second layer 30 corresponding to the patterned area of the second photoresist layer 31 is etched to form a first The two-layer opening 33 is shown in FIG. 6.

Specifically, a photoresist is coated on the surface of the second layer 30 away from the first layer 20 and photolithography is performed to form a patterned second photoresist layer 31.

S116: An active material 35 is deposited in the second layer opening 33 to form an active layer 32, so that the surface of the active layer 32 far from the first layer 20 and the surface of the second layer 30 far from the first layer 20 are substantially flush.

Specifically, an active material 35 is deposited on the surface of the second photoresist layer 31 away from the second layer 30 and in the second layer opening 33, and the thickness of the active material 35 is the same as the depth of the second layer opening 33, as shown in FIG. 7 is shown.

The second photoresist layer 31 and the active material 35 deposited on the surface of the second photoresist layer 31 are peeled off, and the active material deposited in the second layer opening 33 forms an active layer 32, as shown in FIG. 8.

It can be understood that the active layer 32 is the active material 35 deposited on the second layer opening 33.

It should be noted that the active material 35 is a material forming the active layer 32, such as a semiconductor material such as a metal oxide semiconductor.

S117: A third layer 40 is formed on a surface of the active layer 32 and the second layer 30 that is far from the first layer 20.

S118: A source opening 43, a drain opening 45, and an auxiliary electrode opening 47 penetrating through the third layer 40 are formed in the third layer 40, respectively. The source opening 43 and the drain opening 45 all expose at least part of the active layer 32.

Specifically, a patterned third photoresist layer 41 is formed on a surface of the third layer 40 away from the second layer 30, and a position of the third layer 40 corresponding to the patterned area of the third photoresist layer 41 is etched to form a source. The electrode opening 43, the drain opening 45, and the auxiliary electrode opening 47, wherein the source opening 43 and the drain opening 45 all expose at least part of the active layer 32, as shown in FIG.

It can be understood that, if an auxiliary electrode is not needed, the auxiliary electrode opening 47 may not be etched.

Specifically, a photoresist is coated on the surface of the third layer 40 away from the second layer 30 and photolithography is performed to form a patterned third photoresist layer 41.

S119: Deposit a metal material 49 in the source opening 43, the drain opening 45, and the auxiliary electrode opening 47 to form the source 42, drain 44 and auxiliary electrode 46, so as to keep the source 42, drain 44 and auxiliary electrode 46 away from each other. The surface of the second layer 30 is substantially flush with the surface of the third layer 40 away from the second layer 30, and the source electrode 42 and the drain electrode 44 are at least partially in contact with the active layer 32.

Specifically, a metal material 49 is deposited on the surface of the third photoresist layer 41 away from the third layer 40, in the source opening 43, the drain opening 45, and the auxiliary electrode opening 47. The deposition thickness of the metal material 49 is the same as that of the third The thickness of the layer 40 is the same, as shown in FIG. 10.

It should be noted that the metal material 49 is a conductive metal material such as copper-molybdenum alloy, aluminum, and aluminum-molybdenum alloy.

The third photoresist layer 41 and the metal material 49 deposited on the surface of the third photoresist layer 41 are peeled off. The metal material deposited in the source opening 43 forms the source electrode 42 and the metal material deposited in the drain opening 45 forms a drain electrode. The electrode 44 and the metal material 49 deposited in the auxiliary electrode opening 47 form the auxiliary electrode 46 as shown in FIG. 11.

S120: A flat layer 50 is formed on a surface of the source electrode 42, the drain electrode 44, the auxiliary electrode 46, and the third layer 40 away from the second layer 30.

S121: A flat layer opening 52 penetrating the flat layer 50 is formed in the flat layer 50, and the flat layer opening 52 exposes at least part of the drain electrode 44.

Specifically, the flat layer 50 is subjected to photolithography to form a flat layer opening 52 that exposes at least part of the drain electrode 44 as shown in FIG. 12.

S122: A pixel electrode 200 is formed in the flat layer opening 52 and the surface of the flat layer 50 away from the third layer 40. The pixel electrode 200 is in contact with the drain electrode 44. An overlaid pixel electrode is formed on the surface of the flat layer 50 away from the third layer 40. The pixel definition layer 300 of 200 is provided with a sub-pixel opening (not shown) on the pixel definition layer 300 to expose at least part of the pixel electrode 200, as shown in FIG. 1.

Specifically, highly conductive metal materials such as aluminum, silver, aluminum-silver alloy, etc. are deposited in the flat layer opening 52 and the surface of the flat layer 50 away from the third layer 40; or materials such as ITO and Ag are alternately deposited sequentially, and then photolithography is performed, To form a patterned pixel electrode 200.

Specifically, a pixel definition layer material is deposited at a position of the flat layer 50 corresponding to the patterned area of the pixel electrode 200 and a surface of the pixel electrode 200 away from the flat layer 50, and then photolithography is performed to form a pixel definition layer 300 having a sub-pixel opening.

In this embodiment, all the pixel electrodes 200 are exposed from the sub-pixel openings.

The preparation method of the above top-emitting display panel is simple and feasible, which can prepare a back plate structure with a flat surface of the pixel electrode, avoiding the problem of unevenness of the surface of the pixel electrode due to the driving circuit of the top-emitting display panel, and effectively improving the top-emitting display panel. Uniform light emission, thereby improving the display effect.

As shown in FIG. 13, a top emission display panel 2000 according to another embodiment of the present invention includes a substrate 10, an insulating layer 70, a circuit layer 60, a flat layer 50, a pixel electrode 200, and a pixel definition layer 300. The insulating layer 70, the circuit layer 60, and the flat layer 50 constitute a display panel backplane structure.

The substrate 10 has a TFT driving array for driving light-emitting components to realize image display. Alternatively, the substrate 10 may be a rigid substrate or a flexible substrate. The rigid substrate can be made of ceramic or various types of glass. The flexible substrate may be a polyimide film (PI) and its derivatives, polyethylene naphthalate (PEN), phosphoenolpyruvate (PEP), or a diphenylene ether resin. The TFT driving array may include an amorphous silicon TFT array, a polycrystalline TFT array, a metal oxide TFT array, and the like.

An insulating layer 70 is provided on the substrate 10. Optionally, the insulating layer 70 is composed of a gate insulating layer or an etch stop layer, and the material may be selected from SiO _x or SiN _x .

The circuit layer 60 is buried in the insulating layer 70, and the upper surface of the circuit layer 60 is substantially flush with the upper surface of the insulating layer 70. The circuit layer 60 is made of a metal material, such as Al, Cu / Mo alloy, or Al / Mo alloy, and the like. In one embodiment, the circuit layer 60 includes source and drain electrode wiring. Further, in one of the embodiments, the circuit layer 60 includes source, drain electrode wiring, and auxiliary electrode wiring. It should be noted that the upper surface of the circuit layer 60 and the upper surface of the insulating layer 70 refer to a side away from the substrate 10. The upper surface of the circuit layer 60 is substantially flush with the upper surface of the insulating layer 70, which means that the height difference between the upper surface of the circuit layer 60 and the upper surface of the insulating layer 70 does not exceed 1% of the thickness of the insulating layer 70. Preferably, the The upper surface is flush with the upper surface of the insulating layer 70.

The flat layer 50 is provided on the insulating layer 70 and the circuit layer 60 and plays a flat role. In this embodiment, the flat layer 50 is an organic mask layer, and the flat layer 50 has a connection hole for connecting the circuit layer 60 and the pixel electrode 200. Preferably, the thickness of the flat layer 50 is 1 μm to 2 μm, such as 1 μm or 1.5 μm.

The pixel electrode 200 is disposed on the flat layer 50. In this embodiment, the pixel electrode 200 is a flat reflective conductive film, such as a stacked structure of metal Ag, Al, or semiconductor oxide ITO equal to metal. The pixel electrode 200 is a patterned electrode layer, and has a pattern region (that is, a portion having an electrode material) and a blank region (a portion where the electrode material is removed by etching or the like).

Further, the top emission display panel 2000 further includes a pixel definition layer 300, which is disposed on the flat layer 50 having the patterned pixel electrode 200. The pixel definition layer 300 is used to define a light emitting area of an adjacent sub-pixel unit, and a thickness range thereof may be selected from 800 nm to 1500 nm. In one embodiment, the surface of the pixel definition layer 300 is lyophobic, so as to prevent color mixing caused by ink overflow during the printing process.

In the above top emission type display panel 2000, the circuit layer 60 is buried in the insulating layer 70, and the upper surface of the circuit layer 60 is substantially flush with the upper surface of the insulating layer 70, and the flat layer 50 can be evenly disposed on the insulating layer 70 and the insulating layer 70. On the circuit layer 60, the flat layer 50 can better perform the flattening effect, thereby effectively improving the flatness of the surface of the pixel electrode 200, and further improving the uniformity of light emission in the 2000 sub-pixels of the top emission display panel.

Please refer to FIG. 14 to FIG. 20. A method for manufacturing a top emission display panel according to another embodiment includes the following steps:

Providing a substrate 10 having a TFT driving array;

Making an insulating layer 70 on the substrate 10;

Patterning the insulating layer 70 to form an insulating layer opening 73 (ie, a groove) on the insulating layer 70;

Fill the insulating layer opening 73 with a metal material 49 so that the upper surface of the metal material 49 is substantially flush with the upper surface of the insulating layer 70 to form a circuit layer 60 in the insulating layer 70;

Making a flat layer 50 on the insulating layer 70 and the circuit layer 60;

A pixel electrode 200 is fabricated on the flat layer 50.

A method for manufacturing a top-emission display panel 2000 in one embodiment includes the following steps:

S210: Provide a substrate 10 having a TFT driving array.

S212: Referring to FIG. 14, an insulating layer 70 is formed on the substrate 10.

In this embodiment, an insulating layer 70 is obtained by depositing a material such as SiOx or SiNx on the substrate 10 having a TFT driving array.

S213: Please further combine FIG. 15 to form a mask layer 71 on the insulating layer 70.

In this embodiment, the mask layer 71 is a photoresist layer.

S214: Referring to FIG. 15, patterning the mask layer.

In this embodiment, a design pattern including source and drain electrode wiring is provided, the mask layer is developed according to the design pattern, and a part of the mask layer 71 is removed to form a mask opening region 72.

For the case where a large-sized display device needs to add auxiliary electrodes, a design pattern including source, drain electrode wiring, and auxiliary electrode wiring is provided. The mask layer 71 is developed according to the design pattern, and a part of the mask layer 71 is removed to form a mask opening area. 72.

S215: Please further combine FIG. 16 with the patterned mask layer 71 as a mask to etch a portion of the insulating layer 70 that is not covered by the mask layer 71 to form an insulating layer opening 73.

In this embodiment, a part of the insulating layer 70 is etched away by laser etching technology to form an insulating layer opening 73 on the insulating layer 70. The depth of the insulating layer opening 73 is determined according to the design of the source and drain electrode wiring (and auxiliary electrode wiring). Height control.

S216: Please further combine FIG. 17 to deposit a metal material 49 on the insulating layer opening 73 and at least a part of the masking layer 71 surrounding the insulating layer opening 73 on the side of the insulating layer 70 covered with the patterned masking layer 71. The upper surface of the metal material 49 deposited in the insulating layer opening 73 is substantially flush with the upper surface of the insulating layer 70 to form a circuit layer 60 in the insulating layer 70.

In this embodiment, a metal material 49 is deposited on the entire surface, that is, a metal material 49 is deposited on the mask layer 71, and a portion of the metal material 49 falls into the mask opening area 72 and then enters the insulation layer opening 73 on the insulation layer 70 until The insulating layer openings 73 on the insulating layer 70 are filled to form a circuit layer 60 in the insulating layer 70 so that the upper surface of the insulating layer 70 and the upper surface of the circuit layer 60 together form a flat surface. Optionally, the conductive metal may be selected from, but not limited to, Al, Cu / Mo alloy, Al / Mo alloy, and the like.

S217: Please further combine FIG. 18 to peel off the mask layer 71 to remove the excess metal material 49 surrounding the insulating layer opening 73, and retain the metal material 49 in the insulating layer opening 73 to form the circuit layer 60.

In this embodiment, the mask layer 71 is peeled by a lift-off process, and the metal material 49 including the upper surface of the mask layer 71 is also peeled along with it, exposing the upper surface of the insulating layer 70 and the circuit layer 60's upper surface.

S218: Please further combine FIG. 19 to form a flat layer 50 on the insulating layer 70 and the circuit layer 60.

In this embodiment, a flat layer 50 is deposited on the insulating layer 70 and the circuit layer 60 to play a flat role.

S219: Please further combine FIG. 20 to fabricate the pixel electrode 200 on the flat layer 50.

Specifically, in this embodiment, a hole is formed in the flat layer 50 to form a connection hole, and a pixel electrode 200 electrically connected to the circuit layer 60 through the connection hole is formed on the flat layer 50.

In this embodiment, the pixel electrode 200 is a flat reflective conductive film, such as a stacked structure of metal Ag, Al, or semiconductor oxide ITO equal to metal.

In one embodiment, the method for manufacturing the top emission display panel 2000 further includes the following steps:

The pixel electrode 200 is subjected to a patterning process, and a pixel definition layer 300 is fabricated on the flat layer 50 having the patterned pixel electrode 200.

The technical features of the embodiments described above can be arbitrarily combined. In order to make the description concise, all possible combinations of the technical features in the above embodiments have not been described. However, as long as the combination of these technical features does not Any contradiction should be considered as the scope recorded in this specification.

The above-mentioned embodiment only expresses several implementation manners of the present invention, and the description thereof is more specific and detailed, but it cannot be understood as a limitation on the scope of the invention patent. It should be noted that, for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made, which all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent shall be subject to the appended claims.

Claims (20)

1. A display panel backplane structure is characterized in that it includes:

   A substrate with a TFT driving array;

   An insulating layer disposed on the substrate;

   A circuit layer buried in the insulating layer, and an upper surface of the circuit layer is substantially flush with an upper surface of the insulating layer;

   A flat layer is disposed on the insulating layer and the circuit layer.
2. The backplane structure of a display panel according to claim 1, wherein the insulating layer comprises:

   A first layer provided on the substrate, a gate embedded in the first layer, a surface of the gate far from the substrate being substantially flush with a surface of the first layer far from the substrate;

   A second layer provided on the first layer, an active layer embedded in the second layer, a surface of the active layer far from the first layer and a distance of the second layer from the first layer The surface of the layer is substantially flush; and

   A third layer provided on the second layer, the third layer is embedded with a circuit layer, the circuit layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are far from the surface of the second layer Are substantially flush with the surface of the third layer away from the second layer, and the source and drain electrodes are at least partially in contact with the active layer,

   The flat layer is provided with a flat layer opening penetrating the flat layer to expose at least part of the drain.
3. The backplane structure of a display panel according to claim 2, wherein the circuit layer is further provided with at least one auxiliary electrode, and a surface of each of the auxiliary electrodes away from the second layer is away from the third layer The surface of the second layer is substantially flush.
4. The display panel backplane structure according to claim 1, wherein the circuit layer includes source and drain electrode wiring.
5. The backplane structure of a display panel according to claim 4, wherein the circuit layer further comprises an auxiliary electrode wiring.
6. The backplane structure of a display panel according to claim 1, wherein the insulating layer is a gate insulating layer or an etching barrier layer.
7. A method for preparing a display panel backplane structure is characterized in that it includes the following steps:

   Providing a substrate with a TFT drive array;

   Forming an insulating layer on the substrate;

   Patterning the insulating layer to form an insulating layer opening on the insulating layer;

   Depositing a metal material in the opening of the insulating layer so that the upper surface of the metal material is substantially flush with the upper surface of the insulating layer to form a circuit layer in the insulating layer;

   A flat layer is made on the insulating layer and the circuit layer.
8. The method of claim 7, wherein forming an insulating layer on the substrate comprises:

   Forming a first layer of the insulating layer on the substrate;

   A first layer opening is formed in the first layer, and a gate material is deposited in the first layer opening to form a gate, so that the surface of the gate away from the substrate and the first layer away from the substrate The surface is substantially flush;

   Forming a second layer of an insulating layer on a surface of the gate and the first layer remote from the substrate;

   A second layer opening is formed on the second layer, and an active material is deposited in the second layer opening to form an active layer, so that the active layer is far from the surface of the first layer and the second layer. The surface of the layer far from the first layer is substantially flush;

   Forming a third layer of an insulating layer on a surface of the active layer and the second layer remote from the first layer;

   A circuit layer opening penetrating the third layer is formed in the third layer, and the circuit layer opening includes a source opening and a drain opening, respectively, and at least a part of the source opening and the drain opening is exposed. In the source layer, a metal material is deposited in the source opening and the drain opening to form a source and a drain, so that the surfaces of the source and drain away from the second layer are separated from the surface of the second layer. A surface of the three layers far from the second layer is substantially flush, and the source and drain electrodes are at least partially in contact with the active layer; and

   Forming the flat layer on a surface of the source, drain, and the third layer remote from the second layer, and forming a flat layer opening penetrating the flat layer in the flat layer, the flat layer opening being at least A portion of the drain is exposed.
9. The method of claim 8, wherein a first layer opening is formed in the first layer, and a gate material is deposited in the first layer opening to form a gate electrode. The method is:

   Forming a patterned first photoresist layer on a surface of the first layer remote from the substrate, and etching the first layer at a position corresponding to the patterned area of the first photoresist layer to form the first A layer of openings

   A gate material is deposited on a surface of the first photoresist layer away from the first layer and in the opening of the first layer to a thickness at which the gate material is deposited to the same depth as the opening of the first layer. The first photoresist layer and the gate material deposited on the surface of the first photoresist layer are peeled off, and the gate material deposited in the opening of the first layer forms a gate.
10. The method of claim 8, wherein the second layer opening is formed in the second layer, and an active material is deposited in the second layer opening to form an active layer. The method is:

    Forming a patterned second photoresist layer on a surface of the second layer remote from the first layer, and etching the position of the second layer corresponding to the patterned area of the second photoresist layer to form the Mentioned second layer opening;

    An active material is deposited on a surface of the second photoresist layer away from the second layer and in the opening of the second layer to a thickness where the thickness of the active material is the same as the depth of the opening of the second layer. The second photoresist layer and the active material deposited on the surface of the second photoresist layer are peeled off, and the active material deposited in the opening of the second layer forms an active layer.
11. The method for preparing a display panel backplane structure according to claim 8, wherein a circuit layer opening penetrating the third layer is formed in each of the third layers, and the circuit layer openings each include a source opening. And drain openings, a method of depositing a metal material in the source openings and the drain openings to form the source and drain is:

    Forming a patterned third photoresist layer on a surface of the third layer remote from the second layer, and etching the positions of the third layer corresponding to the patterned areas of the third photoresist layer to form the respective portions The source opening and the drain opening;

    A metal material is deposited on a surface of the third photoresist layer away from the third layer, in the source opening and the drain opening to a thickness at which the metal material is deposited to be the same as the thickness of the third layer Removing the third photoresist layer and the metal material deposited on the surface of the third photoresist layer, the metal material deposited in the source opening forms a source, and the metal deposited in the drain opening The material forms a drain.
12. The method of claim 11, wherein the method for forming a circuit layer in the third layer further comprises the following steps:

    Forming at least one auxiliary electrode opening through the third layer in the third layer, and depositing a metal material in each of the auxiliary electrode openings to form an auxiliary electrode so that each of the auxiliary electrodes is far from the second layer The surface of is substantially flush with the surface of the third layer away from the second layer.
13. The method for manufacturing a display panel backplane structure according to claim 12, wherein at least one auxiliary electrode opening penetrating the third layer is formed in the third layer, and each of the auxiliary electrode openings is formed in the third layer The method for forming an auxiliary electrode by depositing a metal material is:

    Etching the position of the third layer corresponding to the patterned region of the third photoresist layer, and further forming at least one auxiliary electrode opening;

    A metal material is deposited in each of the auxiliary electrode openings, the metal material is deposited to a thickness equal to the thickness of the third layer, and the metal material deposited in the auxiliary electrode openings forms an auxiliary electrode.
14. The method of claim 7, wherein the method for patterning the insulating layer comprises the following steps:

    Making a mask layer on the insulating layer;

    Patterning the mask layer;

    With the mask layer subjected to the patterning process as a mask, etching is performed on a portion of the insulating layer not covered by the mask layer to form the insulating layer opening.
15. The method for manufacturing a back panel structure of a display panel according to claim 14, wherein the method for depositing a metal material in the opening of the insulating layer comprises the following steps:

    On the side of the insulating layer that is covered with the patterned masking layer, a metal material is deposited on the insulating layer opening and at least a part of the masking layer surrounding the opening of the insulating layer, so that the upper surface of the metal material is The surface is substantially flush with the upper surface of the insulating layer;

    The mask layer is peeled off to remove excess metal material surrounding the opening of the insulating layer, and the metal material in the opening of the insulating layer is retained to form the circuit layer.
16. The method for manufacturing a display panel backplane structure according to claim 14, wherein the step of patterning the mask layer comprises:

    Provide a design pattern including source and drain electrode wiring, develop the mask layer according to the design pattern, and remove a part of the mask layer to form a mask opening area.
17. The method for manufacturing a display panel backplane structure according to claim 14, wherein the step of patterning the mask layer comprises:

    Provide a design pattern including source, drain electrode wiring, and auxiliary electrode wiring, develop the mask layer according to the design pattern, and remove a part of the mask layer to form a mask opening area.
18. A top-emitting display panel, comprising a display panel backplane structure and a pixel electrode and a pixel definition layer provided on the display panel backplane structure. The display panel backplane structure includes:

    A substrate with a TFT driving array;

    An insulating layer disposed on the substrate;

    A circuit layer buried in the insulating layer, and an upper surface of the circuit layer is substantially flush with an upper surface of the insulating layer;

    A flat layer is disposed on the insulating layer and the circuit layer.
19. The top emission display panel according to claim 18, wherein the insulating layer comprises:

    A first layer provided on the substrate, a gate embedded in the first layer, a surface of the gate far from the substrate being substantially flush with a surface of the first layer far from the substrate;

    A second layer provided on the first layer, an active layer embedded in the second layer, a surface of the active layer far from the first layer and a distance of the second layer from the first layer The surface of the layer is substantially flush; and

    A third layer provided on the second layer, the third layer is embedded with a circuit layer, the circuit layer includes a source electrode and a drain electrode, and the source electrode and the drain electrode are far from the surface of the second layer Are substantially flush with the surface of the third layer away from the second layer, and the source and drain electrodes are at least partially in contact with the active layer,

    The flat layer is provided with a flat layer opening penetrating the flat layer to expose at least part of the drain,

    The pixel electrode is disposed in the flat layer opening and on the flat layer, and the pixel electrode is in contact with the drain,

    The pixel definition layer is provided on the flat layer, and the pixel definition layer is provided with a sub-pixel opening to expose at least a part of the pixel electrode.
20. The top emission display panel according to claim 19, wherein the top emission display panel further comprises a sub-pixel, and the sub-pixel is disposed in the sub-pixel opening of the pixel definition layer.

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