CN110416257A - Display panel back board structure, preparation method and top emission type display panel - Google Patents
Display panel back board structure, preparation method and top emission type display panel Download PDFInfo
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- CN110416257A CN110416257A CN201810776556.8A CN201810776556A CN110416257A CN 110416257 A CN110416257 A CN 110416257A CN 201810776556 A CN201810776556 A CN 201810776556A CN 110416257 A CN110416257 A CN 110416257A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
Abstract
This application involves a kind of top emission type display panels, including substrate, buffer layer, grid, insulating layer, active layer, protective layer, source electrode, drain electrode, auxiliary electrode, flatness layer, pixel electrode and pixel defining layer.Above-mentioned top emission type display panel; grid is embedded in buffer layer and constitutes flat surfaces with buffer layer; active layer is embedded in insulating layer and constitutes flat surfaces with insulating layer; source electrode, drain electrode, auxiliary electrode are embedded in protective layer respectively and constitute flat surfaces with protective layer; so that entire substrate surface forms flat surfaces after the completion of TFT driving circuit processing procedure; avoid the problem that top emission type display panel causes the surface irregularity of pixel electrode due to driving circuit; the uniformity of luminance of top emission type display panel is effectively improved, to improve display effect.
Description
Technical field
The present invention relates to organic illuminating electronic device arts, more particularly to a kind of display panel back board structure, its
Preparation method and top emission type display panel.
Background technique
Organic electroluminescent LED (OLED) due to it with self-luminous, reaction is fast, visual angle is wide, brightness is high, frivolous etc.
Advantage becomes one of the Main way of current display research.OLED display mainly uses solution processing and fabricating, have it is low at
Originally, high production capacity, it is easily achieved the advantages that large scale, becomes the important directions of the following display technology development.Wherein, printing technology quilt
It is considered to realize the most effective approach of OLED low cost and the full-color display of large area.
Since OLED display panel needs to compensate using more complicated driving circuit, in TFT backplate very
Most of all driven circuits are covered, and cause to use the display panel aperture opening ratio of bottom emitting type device architecture smaller, to lead
The problems such as cause power consumption increases, and device lifetime shortens.And opening for display panel can be greatly improved using top emitting device structure
Mouth rate avoids the problems such as power consumption increase and device lifetime shorten because caused by aperture opening ratio is too small.
However when using printing technology preparation top emitting device, the flatness of pixel electrode is required to be much higher than vapor deposition type device
Part.The pixel electrode of top emission type display panel is due to covering driving circuit, and driving circuit is during pre-production very
Difficulty is planarized, therefore the flatness of its pixel electrode surface is poor, leads to the non-uniform light of top emitting OLED.
Summary of the invention
Based on this, it is necessary to provide a kind of top emission type display panel that pixel electrode surface is smooth.
In addition, the application also provides a kind of display panel back board structure and preparation method thereof.
A kind of display panel back board structure, comprising: substrate；
Buffer layer on the substrate is embedded with grid in the buffer layer, and the grid is far from the substrate
Surface is substantially flush with the buffer layer far from the surface of the substrate；
Insulating layer on the buffer layer is embedded with active layer in the insulating layer, and the active layer is far from described
The surface of buffer layer is substantially flush with the insulating layer far from the surface of the buffer layer；
Protective layer on the insulating layer is embedded with source electrode and drain electrode, the source electrode and drain electrode in the protective layer
Be substantially flush respectively with the protective layer far from the surface of the insulating layer far from the surface of the insulating layer, and the source electrode and
Drain electrode is at least partly contacted with the active layer；
Flatness layer on the protective layer, the flatness layer are equipped with the flatness layer opening through the flatness layer, with
At least drain described in exposed portion.
At least one auxiliary electrode, each auxiliary are also embedded in the protective layer in one of the embodiments,
Surface of the electrode far from the insulating layer is substantially flush with the protective layer far from the surface of the insulating layer.
A kind of preparation method of display panel back board structure, comprising the following steps:
Substrate is provided；
Buffer layer is formed on the substrate；
Buffer layer opening is formed in the buffer layer, deposition of gate material forms grid in the buffer layer is open, with
It is substantially flush surface of the grid far from the substrate far from the surface of the substrate with the buffer layer；
Insulating layer is formed far from the surface of the substrate in the grid and the buffer layer；
Insulating layer openings are formed in the insulating layer, active material is deposited in the insulating layer openings and is formed with active layer,
So that surface of the active layer far from the buffer layer is substantially flush with the insulating layer far from the surface of the buffer layer；
Protective layer is formed far from the surface of the buffer layer in the active layer and the insulating layer；
It is respectively formed the source electrode protective layer opening and drain protective layer opening through protection village layer in the protective layer,
Source electrode protective layer opening and drain protective layer opening at least active layer described in exposed portion, are protected in the source electrode
With deposited metal material in drain protective layer opening in layer opening, source electrode and drain electrode is formed, so that the source electrode and drain electrode
Surface far from the insulating layer is substantially flush with the protective layer far from the surface of the insulating layer, and the source electrode and drain electrode
At least partly contacted with the active layer；
Flatness layer is formed far from the surface of the insulating layer in the source electrode, drain electrode and the protective layer, described flat
Layer forms the flatness layer opening through the flatness layer, and the flatness layer opening drains described at least exposed portion.
Buffer layer opening is formed in the buffer layer in one of the embodiments, the deposition in the buffer layer is open
The method of grid material formation grid are as follows:
Patterned first photoresist layer is formed far from the surface of the substrate in the buffer layer, the buffer layer is corresponding
The position of the pattered region of first photoresist layer is etched, to form the buffer layer opening；
Deposition of gate material is extremely in surface of first photoresist layer far from the buffer layer and the buffer layer are open
The thickness of the gate material deposition is identical as the depth that the buffer layer is open, and by first photoresist layer and is deposited on described
The grid material of first photoresist layer surface is removed, and the grid material being deposited in the buffer layer opening forms grid.
Insulating layer openings are formed in the insulating layer in one of the embodiments, are deposited in the insulating layer openings
The method of active material formation active layer are as follows:
Patterned second photoresist layer is formed far from the surface of the buffer layer in the insulating layer, by the insulating layer pair
The position of the pattered region of the second light group layer is answered to be etched, to form the insulating layer openings；
Deposition active material is extremely in surface of second photoresist layer far from the insulating layer and the insulating layer openings
The thickness of the active material deposition is identical as the depth of the insulating layer openings, by second photoresist layer and is deposited on described
The active material of second photoresist layer surface is removed, and the active material being deposited in the insulating layer openings forms active layer.
The source electrode protective layer opening through the protective layer is respectively formed in the protective layer in one of the embodiments,
It is open with drain protective layer, deposited metal material, shape in source electrode protective layer opening and in drain protective layer opening
At the method for source electrode and drain electrode are as follows:
Patterned third photoresist layer is formed far from the surface of the insulating layer in the protective layer, by the protective layer pair
The position of the third photoresist layer pattered region is answered to be etched, to be respectively formed the source electrode protective layer opening and the leakage
Pole protective layer opening；
In surface of the third photoresist layer far from the protective layer, source electrode protective layer opening and drain electrode guarantor
Sheath be open in the thickness that deposits of deposited metal material to the metal material it is identical as the thickness of the protective layer, by described the
Three photoresist layers and the metal material removing for being deposited on the third photoresist layer surface, are deposited in the source electrode protective layer opening
Metal material forms source electrode, and the metal material being deposited in the drain protective layer opening forms drain electrode.
The preparation method of above-mentioned display panel back board structure in one of the embodiments, it is described in the active layer and
It is further comprising the steps of after the insulating layer forms protective layer far from the surface of the buffer layer:
At least one auxiliary electrode protective layer opening through the protective layer is formed in the protective layer, each described
Deposited metal material forms auxiliary electrode in auxiliary electrode protective layer opening, so that each auxiliary electrode is far from the insulation
The surface of layer is substantially flush with the protective layer far from the surface of the insulating layer.
At least one auxiliary electrode guarantor through the protective layer is formed in the protective layer in one of the embodiments,
Sheath opening, the method that deposited metal material forms auxiliary electrode in each auxiliary electrode protective layer is open are as follows:
The position that the protective layer corresponds to the pattered region of the third photoresist layer is etched, also forms at least one
A auxiliary electrode protective layer opening；
The deposited metal material in each auxiliary electrode protective layer is open, the thickness of the metal material deposition and institute
The thickness for stating protective layer is identical, and the metal material being deposited in the auxiliary electrode protective layer opening forms auxiliary electrode.
A kind of top emission type display panel, including display panel back board structure and be set to the display panel back board structure on
Pixel electrode and pixel defining layer；The display panel back board structure, including substrate；
Buffer layer on the substrate is embedded with grid in the buffer layer, and the grid is far from the substrate
Surface is substantially flush with the buffer layer far from the surface of the substrate；
Insulating layer on the buffer layer is embedded with active layer in the insulating layer, and the active layer is far from described
The surface of buffer layer is substantially flush with the insulating layer far from the surface of the buffer layer；
Protective layer on the insulating layer is embedded with source electrode and drain electrode, the source electrode and drain electrode in the protective layer
Be substantially flush respectively with the protective layer far from the surface of the insulating layer far from the surface of the insulating layer, and the source electrode and
The drain electrode is at least partly contacted with the active layer；
Flatness layer on the protective layer, the flatness layer are equipped with the flatness layer opening through the flatness layer, with
At least drain described in exposed portion；
The pixel electrode is set to the pixel electrode and the drain electrode in flatness layer opening and on the flatness layer
Contact；
The pixel defining layer is set on the flatness layer, and the pixel defining layer is open equipped with sub-pixel, at least to reveal
The part pixel electrode out.
Above-mentioned top emission type display panel in one of the embodiments, further includes sub-pixel, and the sub-pixel is set to institute
It states in the sub-pixel opening of pixel defining layer.
Above-mentioned top emission type display panel, grid and buffer layer constitute flat surfaces, and active layer constitutes flat with insulating layer
Surface, source-drain electrode and protective layer constitute flat surfaces so that after the completion of TFT driving circuit processing procedure entire substrate surface formed it is flat
Surface avoids the problem that effectively mentioning in top emission type display panel since driving circuit causes the surface irregularity of pixel electrode
The uniformity of luminance of high top emission type display panel, to improve display effect.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the top emission type display panel of an embodiment；
Fig. 2 is the corresponding structural schematic diagram of step S110；
Fig. 3 is the corresponding structural schematic diagram of step S112；
Fig. 4 and Fig. 5 is the corresponding structural schematic diagram of step S113；
Fig. 6 is the corresponding structural schematic diagram of step S115；
Fig. 7 and Fig. 8 is the corresponding structural schematic diagram of step S116；
Fig. 9 is the corresponding structural schematic diagram of step S118；
Figure 10 is the corresponding structural schematic diagram of step S119；
Figure 11 is the corresponding structural schematic diagram of step S120；
Figure 12 is the corresponding structural schematic diagram of step S121.
Specific embodiment
To facilitate the understanding of the present invention, below will to invention is more fully described, and give it is of the invention compared with
Good embodiment.But the invention can be realized in many different forms, however it is not limited to embodiment described herein.Phase
Instead, purpose of providing these embodiments is makes the disclosure of the present invention more thorough and comprehensive.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term as used herein "and/or" includes one or more phases
Any and all resistances of the listed item of pass are closed.
Referring to Fig. 1, the top emission type display panel 1000 of an embodiment, including 100 He of display panel back board structure
100 pixel electrode 200 and pixel defining layer 300 on display panel back board structure.Wherein, display panel back board structure
100 include substrate 10, buffer layer 20, grid 22, insulating layer 30, active layer 32, protective layer 40, source electrode 42, drain electrode 44, auxiliary electricity
Pole 46 and flatness layer 50.
Further, there is TFT drive array on substrate 10, for driving light emitting component, realize that image is shown.
Further, buffer layer 20 is laminated on substrate 10, grid 22 is embedded in buffer layer 20, grid 22 is far from substrate
10 surface is substantially flush with buffer layer 20 far from the surface of substrate 10, constitutes flat surfaces.
It should be noted that surface of the grid 22 far from substrate 10 is substantially flush with buffer layer 20 far from the surface of substrate 10
Refer to: the upper surface of grid 22 and the upper level difference of buffer layer 20 are no more than the 1% of 20 thickness of buffer layer.
Further, the upper surface of grid 22 is flushed with the upper surface of buffer layer 20.
Wherein, the material of buffer layer 20 is selected from Si oxide (SiOx) and nitrogen silicide (SiNxAt least one of).
It is appreciated that in other embodiments, the material of above-mentioned buffer layer 20 can also be existing and arbitrarily can be used as
The material of buffer layer 20.
Further, the material of grid 22 is conductive metal.In the present embodiment, the material of grid 22 is closed selected from copper-molybdenum
At least one of gold, aluminium and aluminium molybdenum alloys.
It is appreciated that the material of above-mentioned grid 22 can also be the existing material that arbitrarily can be used as grid 22.
In the present embodiment, grid 22 is located in buffer layer 20 close to the surface of substrate 10, as shown in Figure 1.
It is appreciated that in other embodiments, grid 22 can also be close with buffer layer 20 close to the surface of substrate 10
The surface of substrate 10 is substantially flush, and constitutes flat surface.
Further, insulating layer 30 is laminated on buffer layer 20.Active layer 32 is embedded in insulating layer 30.Active layer 32 is remote
Surface from buffer layer 20 is substantially flush with insulating layer 30 far from the surface of buffer layer 20, constitutes flat surfaces.
It should be noted that surface of the active layer 32 far from buffer layer 20 and surface base of the insulating layer 30 far from buffer layer 20
Originally flush and refer to: the difference in height of the upper surface of the upper surface and insulating layer 30 of active layer 32 is no more than 30 thickness of insulating layer
1%.
Further, the upper surface of active layer 32 is flushed with the upper surface of insulating layer 30.
In the present embodiment, active layer 32 is located in insulating layer 30 close to the surface of buffer layer 20, as shown in Figure 1.
Wherein, the material of insulating layer 30 is selected from Si oxide (SiOx) and nitrogen silicide (SiNxAt least one of).
It is appreciated that in other embodiments, the material of above-mentioned insulating layer 30 can also be other gate dielectric materials.
Further, the material of active layer 32 is semiconductor material, such as metal-oxide semiconductor (MOS).
Further, protective layer 40 is laminated on insulating layer 30.Source electrode 42, drain electrode 44 and at least are embedded in protective layer 40
One auxiliary electrode 46.
It is appreciated that auxiliary electrode 46 can omit.
Further, the material of protective layer 40 is selected from Si oxide (SiOx) and nitrogen silicide (SiNxAt least one of).
It is appreciated that in other embodiments, the material of above-mentioned protective layer 40 can also be existing and arbitrarily can be used as
The material of protective layer 40.
Further, the material of source electrode 42, drain electrode 44 and auxiliary electrode 46 is conductive metal.In the present embodiment, source
The material of pole 42, drain electrode 44 and auxiliary electrode 46 is selected from least one of copper molybdenum alloy, aluminium and aluminium molybdenum alloys.
Further, source electrode 42, drain electrode 44 and surface of the auxiliary electrode 46 far from insulating layer 30 are separate with protective layer 40
The surface of insulating layer 30 is substantially flush, and constitutes flat surfaces.
It should be understood that source electrode 42, drain electrode 44 and surface of the auxiliary electrode 46 far from insulating layer 30 with protective layer 40
Surface far from insulating layer 30 is substantially flush and refers to: the upper surface of source electrode 42, drain 44 upper surface, auxiliary electrode 46 it is upper
The difference in height of surface and the upper surface of protective layer 40 is no more than the 1% of 40 thickness of protective layer.
Further, the upper surface of source electrode 42, drain 44 upper surface, auxiliary electrode 46 upper surface with protective layer 40
Upper surface flush.
Further, source electrode 42 and drain electrode 44 are at least partly contacted with active layer 32.The then external power supply of auxiliary electrode 46
Circuit.
Further, flatness layer 50 is laminated on protective layer 40.Flatness layer 50 is equipped with the flatness layer through the flatness layer 50
Opening 52, at least exposed portion drain electrode 44, as shown in figure 12.
Further, flatness layer 50 is that organic photoresist layer serves flat with a thickness of 1 μm.
Further, pixel electrode 200 is set in flatness layer opening 52 and on flatness layer 50.Pixel electrode 200 and drain electrode
44 contacts.
Further, pixel electrode 200 is conductive film layer, which is reflective conductive film layer, such as aluminium, silver, aluminium
The high conductive metal film such as silver alloy；Or including ITO, Ag and ITO etc. multilayered structures reflective conductive film.
Further, pixel defining layer 300 is set on flatness layer 50, and pixel defining layer 300 is equipped with sub-pixel opening, and (figure is
Mark), with exposed portion pixel electrode 200.
In the present embodiment, sub-pixel opening exposes whole pixel electrodes 200.
Further, pixel defining layer 300 with a thickness of 800nm~1500nm, for defining the light-emitting area of each pixel
Size, surface are in lyophobicity, prevent ink spilling from causing colour mixture in printing process.
Above-mentioned top emission type display panel, grid 22 and buffer layer 20 constitute flat surfaces, active layer 32 and insulating layer 30
Flat surfaces are constituted, source electrode 42, drain electrode 44, auxiliary electrode 46 and protective layer 40 constitute flat surfaces, so that TFT driving circuit system
Entire substrate surface forms flat surfaces after the completion of journey, avoids top emission type display panel since driving circuit causes pixel electrode
Surface irregularity the problem of, the uniformity of luminance of top emission type display panel is effectively improved, to improve display effect.
Please refer to Fig. 1~12, the preparation method of the top emission type display panel of an embodiment, comprising the following steps:
S110, substrate 10 is provided, forms buffer layer 20 on aforesaid substrate 10, as shown in Figure 2.
Specifically, the materials such as deposited silicon oxide, nitrogen silicide are on the substrate 10 to form buffer layer 20.
S112, buffer layer opening 23 is formed in buffer layer 20.
Specifically, patterned first photoresist layer 21 is formed far from the surface of substrate 10 in buffer layer 20, by buffer layer 20
The pattered region of corresponding first photoresist layer 21 is etched, to form buffer layer opening 23, as shown in Figure 3.
Specifically, being coated with photoresist far from the surface of substrate 10 in buffer layer 20 and to carry out photoetching patterned to be formed
First photoresist layer 21.
S113, deposition of gate material 25 forms grid 22 in buffer layer opening 23, so that grid 22 is far from substrate 10
Surface is substantially flush with buffer layer 20 far from the surface of substrate 10.
Specifically, the deposition of gate material 25 in surface of first photoresist layer 21 far from buffer layer 20 and buffer layer opening 23
Deposition thickness to the grid material 25 is identical as the depth of buffer layer opening 23, as shown in Figure 4.
First photoresist layer 21 and the grid material 25 for being deposited on 21 surface of the first photoresist layer are removed, buffer layer is deposited on and opens
Grid material in mouth 23 forms grid 22, as shown in Figure 5.
It is appreciated that grid 22 is the grid material 25 being deposited in buffer layer opening 23.
S114, insulating layer 30 is formed far from the surface of substrate 10 in grid 22 and buffer layer 20.
Specifically, in the surface deposition gate dielectric materials of grid 22 and buffer layer 20 far from substrate 10 to form insulating layer
30。
S115, insulating layer openings 33 are formed in insulating layer 30.
Specifically, patterned second photoresist layer 31 is formed far from the surface of buffer layer 20 in insulating layer 30, by insulating layer
The position of the pattered region of 30 corresponding second photoresist layers 31 is etched, to form insulating layer openings 33, as shown in Figure 6.
Specifically, be coated with photoresist far from the surface of buffer layer 20 in insulating layer 30 and carry out photoetching, it is patterned to be formed
Second photoresist layer 31.
S116, the formation active layer 32 of active material 35 is deposited in insulating layer openings 33, so that active layer 32 is far from buffering
The surface of layer 20 is substantially flush with insulating layer 30 far from the surface of buffer layer 20.
Specifically, the 33 deposition active materials in surface of second photoresist layer 31 far from insulating layer 30 and insulating layer openings
35, the deposition thickness of the active material 35 is identical as the depth of insulating layer openings 33, as shown in Figure 7.
Second photoresist layer 31 and the active material 35 for being deposited on 31 surface of the second photoresist layer are removed, insulating layer is deposited on and opens
Active material in mouth 33 forms active layer 32, as shown in Figure 8.
It is appreciated that active layer 32 is the active material 33 for being deposited on insulating layer openings 33.
It should be noted that the active material 33 is the material for forming active layer 32, such as metal-oxide semiconductor (MOS) half
Conductor material.
S117, protective layer 40 is formed far from the surface of buffer layer 20 in active layer 32 and insulating layer 30.
S118, the source electrode protective layer opening 43 through protective layer 40, drain protective layer opening are respectively formed in protective layer 40
45 and auxiliary electrode protective layer opening 47, wherein source electrode protective layer opening 43 and at least exposed portion of drain protective layer opening 45
Active layer 32.
Specifically, patterned third photoresist layer 41 is formed far from the surface of insulating layer 30 in protective layer 40, by protective layer
The position of the pattered region of 40 corresponding third photoresist layers 41 is etched, to form source electrode protective layer opening 43, drain electrode protection
Layer opening 45 and auxiliary electrode protective layer opening 47, wherein source electrode protective layer opening 43 and drain protective layer opening 45 are at least revealed
Part active layer 32 out, as shown in Figure 9.
It is appreciated that above-mentioned auxiliary electrode protective layer opening 47 can be without etching if not needing auxiliary electrode.
Specifically, being coated with photoresist far from the surface of insulating layer 30 in protective layer 40 and carrying out photoetching to form patterned the
Three photoresist layers 41.
S119, it is deposited in source electrode protective layer opening 43, drain protective layer opening 45 and auxiliary electrode protective layer opening 47
Metal material 49 forms source electrode 42, drain electrode 44 and auxiliary electrode 46, so that source electrode 42, drain electrode 44 and auxiliary electrode 46 are far from absolutely
The surface of edge layer 30 is substantially flush with protective layer 40 far from the surface of insulating layer 30, and source electrode 42 and drain electrode 44 at least partly with
Active layer 32 contacts.
Specifically, in surface of the third photoresist layer 41 far from protective layer 40, source electrode protective layer opening 43, drain protective layer
Opening 45 in and auxiliary electrode protective layer opening 47 in deposited metal material 49, the deposition thickness and protective layer of the metal material 49
40 thickness is identical, as shown in Figure 10.
It should be noted that the metal material 49 is the conductive metallic materials such as copper molybdenum alloy, aluminium and aluminium molybdenum alloys.
Third photoresist layer 41 and the metal material 49 for being deposited on 41 surface of third photoresist layer are removed, source electrode protection is deposited on
Metal material in layer opening 43 forms source electrode 42, and the metal material being deposited in drain protective layer opening 45 forms drain electrode 44,
The metal material 49 being deposited in auxiliary electrode protective layer opening 47 forms auxiliary electrode 46, as shown in figure 11.
S120, flatness layer is formed far from the surface of insulating layer 30 in source electrode 42, drain electrode 44, auxiliary electrode 46 and protective layer 40
50。
S121, the flatness layer opening 52 through flatness layer 50 is formed in flatness layer 50, flatness layer opening 52 is at least exposed
Part drain electrode 44.
Specifically, carrying out photoetching to flatness layer 50, flatness layer opening 52, at least exposed portion of flatness layer opening 52 are formed
Drain electrode 44, as shown in figure 12.
S122, flatness layer opening 52 in and flatness layer 50 far from protective layer 40 surface formed pixel electrode 200, the picture
Plain electrode 200 is contacted with drain electrode 44, fixed in the pixel that flatness layer 50 covers pixel electrode 200 far from the surface formation of protective layer 40
Adopted layer 300, setting sub-pixel is open (figure is not marked) in pixel defining layer 300, at least exposed portion pixel electrode 200, such as Fig. 1
It is shown.
Specifically, being closed with flatness layer 50 far from the surface deposition such as aluminium of protective layer 40, silver, aluminium silver in flatness layer opening 52
The contour conductive metallic material of gold；Or successively materials such as alternating deposit ITO, Ag, photoetching is carried out, then to form patterned pixel
Electrode 200.
Specifically, in the position of the pattered region of 50 respective pixel electrode 200 of flatness layer and pixel electrode 200 far from flat
The surface pixel deposition of smooth layer 50 defines layer material, then carries out photoetching, to form the pixel defining layer with sub-pixel opening
300。
In the present embodiment, above-mentioned sub-pixel opening exposes whole pixel electrodes 200.
The preparation method simple possible of above-mentioned top emission type display panel can prepare the smooth backboard knot of pixel electrode surface
Structure avoids the problem that top emission type display panel causes the surface irregularity of pixel electrode due to driving circuit, effectively improves top
The uniformity of luminance of emission type display panel, to improve display effect.
Each technical characteristic of embodiment described above can be carried out arbitrarily hindering and be closed, for simplicity of description, not to above-mentioned reality
It applies all possible resistance conjunction of each technical characteristic in example to be all described, as long as however, the resistance conjunction of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of display panel back board structure characterized by comprising substrate；
Buffer layer on the substrate is embedded with grid, surface of the grid far from the substrate in the buffer layer
It is substantially flush with the buffer layer far from the surface of the substrate；
Insulating layer on the buffer layer is embedded with active layer in the insulating layer, and the active layer is far from the buffering
The surface of layer is substantially flush with the insulating layer far from the surface of the buffer layer；
Protective layer on the insulating layer is embedded with source electrode and drain electrode in the protective layer, and the source electrode and drain electrode is separate
The surface of the insulating layer is substantially flush with the protective layer far from the surface of the insulating layer respectively, and the source electrode and described
Drain electrode is at least partly contacted with the active layer；
Flatness layer on the protective layer, the flatness layer is equipped with the flatness layer opening through the flatness layer, at least
It drains described in exposed portion.
2. display panel back board structure according to claim 1, which is characterized in that be also embedded at least in the protective layer
One auxiliary electrode, surface of each auxiliary electrode far from the insulating layer and the protective layer are far from the insulating layer
Surface is substantially flush.
3. a kind of preparation method of display panel back board structure, which comprises the following steps:
Substrate is provided；
Buffer layer is formed on the substrate；
Buffer layer opening is formed in the buffer layer, deposition of gate material forms grid in the buffer layer is open, so that institute
It states surface of the grid far from the substrate and is substantially flush with the buffer layer far from the surface of the substrate；
Insulating layer is formed far from the surface of the substrate in the grid and the buffer layer；
Insulating layer openings are formed in the insulating layer, active material is deposited in the insulating layer openings and is formed with active layer, so that
Surface of the active layer far from the buffer layer is substantially flush with the insulating layer far from the surface of the buffer layer；
Protective layer is formed far from the surface of the buffer layer in the active layer and the insulating layer；
The source electrode protective layer opening and drain protective layer opening through the protective layer, the source are respectively formed in the protective layer
Pole protective layer opening and drain protective layer opening at least active layer described in exposed portion, are open in the source electrode protective layer
Deposited metal material in the interior and described drain protective layer opening, forms source electrode and drain electrode, so that the source electrode and drain electrode is far from institute
The surface for stating insulating layer is substantially flush with the protective layer far from the surface of the insulating layer respectively, and the source electrode and drain electrode is equal
At least partly contacted with the active layer；
Flatness layer is formed far from the surface of the insulating layer in the source electrode, drain electrode and the protective layer, in the flatness layer shape
It is open at the flatness layer through the flatness layer, the flatness layer opening drains described at least exposed portion.
4. the preparation method of display panel back board structure according to claim 3, which is characterized in that in the buffer layer shape
It is open at buffer layer, the method that deposition of gate material forms grid in the buffer layer is open are as follows:
Patterned first photoresist layer is formed far from the surface of the substrate in the buffer layer, it will be described in buffer layer correspondence
The position of the pattered region of first photoresist layer is etched, to form the buffer layer opening；
Deposition of gate material is to described in surface of first photoresist layer far from the buffer layer and the buffer layer are open
The thickness of gate material deposition is identical as the depth that the buffer layer is open, and by first photoresist layer and is deposited on described first
The grid material of photoresist layer surface is removed, and the grid material being deposited in the buffer layer opening forms grid.
5. the preparation method of display panel back board structure according to claim 3, which is characterized in that in the insulating layer shape
At insulating layer openings, the method that active material is formed with active layer is deposited in the insulating layer openings are as follows:
Patterned second photoresist layer is formed far from the surface of the buffer layer in the insulating layer, the insulating layer is corresponded into institute
The position for stating the pattered region of the second photoresist layer is etched, to form the insulating layer openings；
Deposition active material is to described in surface of second photoresist layer far from the insulating layer and the insulating layer openings
The thickness of active material deposition is identical as the depth of the insulating layer openings, by second photoresist layer and is deposited on described second
The active material of photoresist layer surface is removed, and the active material being deposited in the insulating layer openings forms active layer.
6. the preparation method of display panel back board structure according to claim 3, which is characterized in that in the protective layer point
Xing Cheng through the protective layer source electrode protective layer opening and drain protective layer opening, the source electrode protective layer opening in and
Deposited metal material in the drain protective layer opening, the method for forming source electrode and drain electrode are as follows:
Patterned third photoresist layer is formed far from the surface of the insulating layer in the protective layer, the protective layer is corresponded into institute
The position for stating the pattered region of third photoresist layer is etched, to be respectively formed the source electrode protective layer opening and the drain electrode
Protective layer opening；
In surface of the third photoresist layer far from the protective layer, source electrode protective layer opening and the drain protective layer
The thickness that deposited metal material to the metal material deposits in being open is identical as the thickness of the protective layer, by the third light
Resistance layer and the metal material removing for being deposited on the third photoresist layer surface, the metal being deposited in the source electrode protective layer opening
Material forms source electrode, and the metal material being deposited in the drain protective layer opening forms drain electrode.
7. the preparation method of display panel back board structure according to claim 6, which is characterized in that described described active
It is further comprising the steps of after layer and the insulating layer form protective layer far from the surface of the buffer layer:
At least one auxiliary electrode protective layer opening through the protective layer is formed in the protective layer, in each auxiliary
Deposited metal material forms auxiliary electrode in electrode protecting layer opening, so that each auxiliary electrode is far from the insulating layer
Surface is substantially flush with the protective layer far from the surface of the insulating layer.
8. the preparation method of display panel back board structure according to claim 7, which is characterized in that in the protective layer shape
It is open at least one auxiliary electrode protective layer through the protective layer, it is heavy in each auxiliary electrode protective layer opening
The method that product metal material forms auxiliary electrode are as follows:
The position that the protective layer corresponds to the pattered region of the third photoresist layer is etched, it is auxiliary also to form at least one
Electrode protecting layer is helped to be open；
The deposited metal material in each auxiliary electrode protective layer is open, the thickness of the metal material deposition and the guarantor
The thickness of sheath is identical, and the metal material being deposited in the auxiliary electrode protective layer opening forms auxiliary electrode.
9. a kind of top emission type display panel, which is characterized in that including display panel back board structure and be set to the display panel
Pixel electrode and pixel defining layer on back board structure；The display panel back board structure, including substrate；
Buffer layer on the substrate is embedded with grid, surface of the grid far from the substrate in the buffer layer
It is substantially flush with the buffer layer far from the surface of the substrate；
Insulating layer on the buffer layer is embedded with active layer in the insulating layer, and the active layer is far from the buffering
The surface of layer is substantially flush with the insulating layer far from the surface of the buffer layer；
Protective layer on the insulating layer is embedded with source electrode and drain electrode in the protective layer, and the source electrode and drain electrode is separate
The surface of the insulating layer is substantially flush with the protective layer far from the surface of the insulating layer respectively, and the source electrode and described
Drain electrode is at least partly contacted with the active layer；
Flatness layer on the protective layer, the flatness layer is equipped with the flatness layer opening through the flatness layer, at least
It drains described in exposed portion；
The pixel electrode is set in flatness layer opening and on the flatness layer, and the pixel electrode connects with the drain electrode
Touching；
The pixel defining layer is set on the flatness layer, and the pixel defining layer is open equipped with sub-pixel, at least exposed division
Divide the pixel electrode.
10. top emission type display panel according to claim 9, which is characterized in that the top emission type display panel is also
Including sub-pixel, the sub-pixel is set in the sub-pixel opening of the pixel defining layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810776556.8A CN110416257A (en) | 2018-07-13 | 2018-07-13 | Display panel back board structure, preparation method and top emission type display panel |
| PCT/CN2019/082337 WO2019242384A1 (en) | 2018-06-19 | 2019-04-11 | Backplane structure of display panel and preparation method therefor, and top-emitting display panel |
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| CN201810776556.8A CN110416257A (en) | 2018-07-13 | 2018-07-13 | Display panel back board structure, preparation method and top emission type display panel |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111129106A (en) * | 2020-01-20 | 2020-05-08 | 合肥京东方卓印科技有限公司 | OLED substrate, preparation method thereof, display panel and display device |
| CN111129032A (en) * | 2019-12-19 | 2020-05-08 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN111540757A (en) * | 2020-05-07 | 2020-08-14 | 武汉华星光电技术有限公司 | Display panel, preparation method thereof and display device |
| WO2021184305A1 (en) * | 2020-03-19 | 2021-09-23 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN113437127A (en) * | 2021-06-25 | 2021-09-24 | 武汉天马微电子有限公司 | Display panel and display device |
| WO2023004684A1 (en) * | 2021-07-29 | 2023-02-02 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display apparatus |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364572A (en) * | 2007-08-10 | 2009-02-11 | 群康科技(深圳)有限公司 | Thin-film transistor manufacturing method |
| US20150001492A1 (en) * | 2013-06-26 | 2015-01-01 | Samsung Display Co., Ltd. | Thin-film transistor substrate, related light-emitting apparatus, and related manufacturing method |
| CN105448936A (en) * | 2016-01-04 | 2016-03-30 | 京东方科技集团股份有限公司 | Array base plate and preparing method thereof, display device |
| CN105514116A (en) * | 2015-12-03 | 2016-04-20 | 深圳市华星光电技术有限公司 | Tft backboard structure and manufacturing method thereof |
| CN105552082A (en) * | 2014-10-30 | 2016-05-04 | 元太科技工业股份有限公司 | Active element circuit substrate |
| CN106057827A (en) * | 2016-08-12 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method, and display device |
| CN106531746A (en) * | 2016-11-30 | 2017-03-22 | 京东方科技集团股份有限公司 | Array substrate, fabrication method of array substrate, display panel and display device |
-
2018
- 2018-07-13 CN CN201810776556.8A patent/CN110416257A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364572A (en) * | 2007-08-10 | 2009-02-11 | 群康科技(深圳)有限公司 | Thin-film transistor manufacturing method |
| US20150001492A1 (en) * | 2013-06-26 | 2015-01-01 | Samsung Display Co., Ltd. | Thin-film transistor substrate, related light-emitting apparatus, and related manufacturing method |
| CN105552082A (en) * | 2014-10-30 | 2016-05-04 | 元太科技工业股份有限公司 | Active element circuit substrate |
| CN105514116A (en) * | 2015-12-03 | 2016-04-20 | 深圳市华星光电技术有限公司 | Tft backboard structure and manufacturing method thereof |
| CN105448936A (en) * | 2016-01-04 | 2016-03-30 | 京东方科技集团股份有限公司 | Array base plate and preparing method thereof, display device |
| CN106057827A (en) * | 2016-08-12 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method, and display device |
| CN106531746A (en) * | 2016-11-30 | 2017-03-22 | 京东方科技集团股份有限公司 | Array substrate, fabrication method of array substrate, display panel and display device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111129032A (en) * | 2019-12-19 | 2020-05-08 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method thereof |
| CN111129106A (en) * | 2020-01-20 | 2020-05-08 | 合肥京东方卓印科技有限公司 | OLED substrate, preparation method thereof, display panel and display device |
| WO2021184305A1 (en) * | 2020-03-19 | 2021-09-23 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN111540757A (en) * | 2020-05-07 | 2020-08-14 | 武汉华星光电技术有限公司 | Display panel, preparation method thereof and display device |
| CN111540757B (en) * | 2020-05-07 | 2024-03-05 | 武汉华星光电技术有限公司 | Display panel, preparation method thereof and display device |
| CN113437127A (en) * | 2021-06-25 | 2021-09-24 | 武汉天马微电子有限公司 | Display panel and display device |
| WO2023004684A1 (en) * | 2021-07-29 | 2023-02-02 | 京东方科技集团股份有限公司 | Display panel and manufacturing method therefor, and display apparatus |
| CN116210368A (en) * | 2021-07-29 | 2023-06-02 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
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Application publication date: 20191105 |