CN102664162A - Pixel structure manufacturing method - Google Patents
Pixel structure manufacturing method Download PDFInfo
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- CN102664162A CN102664162A CN2012101463020A CN201210146302A CN102664162A CN 102664162 A CN102664162 A CN 102664162A CN 2012101463020 A CN2012101463020 A CN 2012101463020A CN 201210146302 A CN201210146302 A CN 201210146302A CN 102664162 A CN102664162 A CN 102664162A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000003860 storage Methods 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 54
- 238000000059 patterning Methods 0.000 claims description 34
- 239000010408 film Substances 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000001259 photo etching Methods 0.000 claims description 13
- 230000003213 activating effect Effects 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000004062 sedimentation Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 59
- 150000002500 ions Chemical class 0.000 description 9
- 230000000873 masking effect Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 3
- 239000012044 organic layer Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- Thin Film Transistor (AREA)
Abstract
The invention relates to a method for manufacturing a pixel structure, which comprises the steps of firstly providing a substrate, forming a semiconductor layer with an active region and a storage capacitor region on the transparent substrate, forming a source electrode and a drain electrode on the semiconductor layer, then forming an isolating layer on the source electrode, the drain electrode and the semiconductor layer, then forming a grid electrode and a capacitor electrode on the isolating layer, wherein the grid electrode and the capacitor electrode are respectively arranged on the corresponding positions of the active region and the storage capacitor region, and sequentially forming a dielectric layer and a shielding layer on the grid electrode, the capacitor electrode and the isolating layer, thus forming a thin film transistor, then forming an opening pattern on the shielding layer for etching, further forming a contact window, finally forming a conducting layer on the shielding layer, so that the drain electrode is electrically connected with the conducting layer through the contact window, thus forming a pixel structure through the steps, the pixel structure can increase the storage capacitance, the aperture ratio is not reduced and the metal leakage is prevented.
Description
Present patent application is the application number submitted in 27th in 03 month in 2007 the dividing an application for the one Chinese patent application of " thin film transistor and pixel structure and manufacturing approach thereof " that be 200710091534.X, denomination of invention.
Technical field
The invention relates to a kind of thin film transistor and pixel structure, and this one pixel structure process method.
Background technology
Generally for the transistorized making flow process of PMOS; On photoetching process, must utilize mask to define P+ and P-zone; And general P transistor npn npn making comprises formation one polysilicon layer; Define its P+ and P-zone with mask, form an insulating barrier, a grid, a dielectric layer more in regular turn, form contact hole in dielectric layer, one source pole electrode, a drain electrode and an organic layer; And form another contact hole in this organic layer, form a conductive layer and electrically connect in this organic layer and through another contact hole and this drain electrode.So integral body need be carried out photoetching process through six road masks and constituted, and will increase its technology difficulty and complexity and can't reduce production costs and improve output capacity.
For another the Taiwan " grid, thin-film transistor and the production method of pixel structure " of patent announcement I253533 number; This piece patent content is for providing a kind of production method of pixel structure; Be the cover curtain layer prior to formation one patterning in the substrate, wherein this cover curtain layer is to expose a predetermined zone that forms grid; Then in this zone that this cover curtain layer exposed, form a grid; Remove this cover curtain layer; On this substrate, form an insulating barrier, cover this grid; On this insulating barrier of this grid top, form a channel layer again; On this channel layer, form an one source pole and a drain electrode then; On this substrate, form a protective layer, wherein this protective layer has an opening, in order to expose this drain electrode of part; And on this protective layer, form a pixel electrode at last, and this pixel electrode is electrically connected with this drain electrode through this opening.
Though above-mentioned prior art, a dot structure made, but technology is complicated, can't reduce production costs and improve output capacity, so it is required when reality is used that prior art can't meet the user.
Summary of the invention
A purpose of the present invention is to provide a kind of thin film transistor and pixel structure and manufacturing approach thereof, can significantly improve the storage capacitors amount, can't reduce aperture opening ratio.
Another object of the present invention is to provide a kind of thin film transistor and pixel structure and manufacturing approach thereof, and the metal in this dot structure is leaked outside, and causes electrical problem to produce.
A purpose more of the present invention; Be to provide a kind of thin film transistor and pixel structure and manufacturing approach thereof; Use five road masking process, can effectively improve output capacity, reduce production costs; And the screen that the collocation of this dielectric layer is made with the material of high aperture so overcomes the problem of electrical phase mutual interference in masking process.
In order to achieve the above object, the present invention provides a kind of dot structure manufacturing approach, and this dot structure manufacturing approach comprises:
One substrate is provided;
Form semi-conductor layer on this substrate, the step that wherein forms described semiconductor layer comprises:
Deposition semiconductor film is on described substrate;
Forming one first photoresist is shielded from this semiconductive thin film;
Utilize one first mask that a photoetching process is carried out in this first photoresist shielding, form first photoresist shielding of patterning;
Through this first photoresist shielding of patterning described semiconductive thin film carried out one first ion inject to form a storage capacitors district, this storage capacitors district is a heavy ion doped region; And
Remove first photoresist shielding of described patterning, form described semiconductor layer;
Formation one source pole and drains in this semiconductor layer top and is in direct contact with it, and the step that forms described source electrode and described drain electrode comprises:
Deposit a first metal layer in described semiconductor layer top;
Depositing one second photoresist is shielded from this first metal layer;
Utilize one second mask that a photoetching process is carried out in this second photoresist shielding, form second photoresist shielding of patterning;
Remove not by this described the first metal layer of second photoresist shielding of the patterning part of covering; And
Remove second photoresist shielding of described patterning, form described source electrode and described drain electrode;
Form a separator and be covered in this source electrode and drain electrode;
After the step that forms this source electrode and this drain electrode, form a grid and a capacitance electrode simultaneously on this separator;
Forming a dielectric layer is covered on this grid and this capacitance electrode;
Forming a screen is covered on this dielectric layer;
Form a contact hole in described drain electrode top to expose this drain electrode; And
Forming a conductive layer directly electrically connects with described drain electrode on described screen and through described contact hole;
Wherein, the step that forms described dielectric layer, described screen and described contact hole comprises:
Successive sedimentation one dielectric film and a shielded film are on described grid, described capacitance electrode and described separator; And
Utilize one the 4th mask that described dielectric film and described shielded film are carried out a chemical wet etching technology, form described dielectric layer, described screen and described contact hole.
Constitute this dot structure by above-mentioned steps, storage capacitors of the present invention district is made up of this semiconductor layer, this separator and this capacitance electrode, can significantly improve the storage capacitors amount; Can't reduce aperture opening ratio, and the metal in this dot structure is leaked outside, cause electrical problem to produce; And manufacturing approach of the present invention has five road masking process; Reduce the complexity of technology, effectively improve output capacity, reduce production costs; The present invention joins this screen in masking process with this dielectric layer, can overcome the problem of electrical phase mutual interference (Cross-talk).
Description of drawings
Fig. 1: dot structure manufacturing process sketch map of the present invention;
Fig. 2 A: the cross-sectional view of step S10 of the present invention;
Fig. 2 B: the plan structure sketch map of step S10 of the present invention;
Fig. 2 C: the cross-sectional view of step S11 of the present invention;
Fig. 2 D: the plan structure sketch map of step S11 of the present invention;
Fig. 2 E: the cross-sectional view of step S12 of the present invention;
Fig. 2 F: the plan structure sketch map of step S12 of the present invention;
Fig. 2 G: the cross-sectional view of step S13 of the present invention;
Fig. 2 H: the plan structure sketch map of step S13 of the present invention;
Fig. 2 I: the cross-sectional view of step S14 of the present invention;
Fig. 2 J: the plan structure sketch map of step S14 of the present invention;
Fig. 2 K: the cross-sectional view of step S15 of the present invention and S16;
Fig. 2 L: the plan structure sketch map of step S15 of the present invention and S16;
Fig. 2 M: the cross-sectional view of step S17 of the present invention;
Fig. 2 N: the plan structure sketch map of step S17 of the present invention;
Fig. 3: the schematic flow sheet of formation semiconductor layer of the present invention;
Fig. 4: the schematic flow sheet of formation source electrode of the present invention and drain electrode;
Fig. 5: the schematic flow sheet of formation grid of the present invention and capacitance electrode;
Fig. 6: the schematic flow sheet of formation dielectric layer of the present invention and screen; And
Fig. 7: the schematic flow sheet of formation conductive layer of the present invention.
Drawing reference numeral:
10 transparent substrates, 12 semiconductor layers
120 active regions, 122 storage capacitors districts
124 first active regions, 126 second active regions
128 P-light ion doped regions, 14 source electrodes
16 drain electrodes, 18 separators
200 first ones of 20 grids
202 second 22 capacitance electrodes
24 dielectric layers, 26 screens
28 contact holes, 30 patterns of openings
32 conductive layers
Embodiment
For making your juror further understanding and understanding arranged, be equipped with preferred embodiment and cooperate illustration architectural feature of the present invention and the effect reached.
See also Fig. 1, Fig. 2 A and Fig. 2 B, be respectively the cross-sectional view of dot structure manufacturing process sketch map of the present invention, step S10 of the present invention and the plan structure sketch map of step S10 of the present invention.As shown in the figure: the present invention provides a kind of thin film transistor and pixel structure and manufacturing approach thereof; This one pixel structure process method is to carry out step S10 earlier; One transparent substrates 10 is provided; The material of this transparent substrates 10 comprises glass, quartz or plastics, but looks design requirement and decide, and transparent substrates 10 is replaceable to be light tight substrate.
Please consult Fig. 2 C and Fig. 2 D in the lump, be respectively the cross-sectional view of step S11 of the present invention and the plan structure sketch map of step S11 of the present invention.As shown in the figure: as to follow execution in step S11, form semi-conductor layer 12 on this transparent substrates 10, consult Fig. 3 more in the lump; The method that forms this semiconductor layer 12 is first execution in step S20, and deposition semiconductor film is cooked up an active region 120 and a storage capacitors district 122 on this transparent substrates 10; Then execution in step S21 forms one first photoresist and is shielded from this semiconductive thin film, again execution in step S22; Utilize one first mask that a photoetching process is carried out in this first photoresist shielding, this first mask is exemplified as half and transfers a mask or a gray level mask, carries out an etching technics afterwards and forms first photoresist shielding of patterning; This first photoresist shielding of patterning comprise a shading region and half penetrating region; This shading region is corresponding with above-mentioned active region 120, and this half penetrating region is corresponding with above-mentioned storage capacitors district 122, to should shading region this thickness of first photoresist shielding of patterning than the thicker of this half penetrating region; Carry out step S23; Through this first photoresist shielding of patterning this semiconductive thin film carried out the P ion inject, make the active region corresponding 120 formation one P-light ion doped region with this shading region, other makes the storage capacitors district corresponding with this half penetrating region 122 formation one P+ heavy ion doped region; Wherein, this P+ ion implantation concentration is between 1E18 and 1E21 atom/cm
3Between, carry out step S24 again, remove this first photoresist shielding of patterning; Form this semiconductor layer 12; The material of this semiconductor layer 12 comprises polysilicon, after forming this semiconductor layer 12, further carries out an activating process in addition; P ion in this semiconductor layer 12 of activation, the temperature of this activating process is between 550 degree Celsius and 1000 degree Celsius.
Please consult Fig. 2 E and Fig. 2 F in the lump, be respectively the cross-sectional view of step S12 of the present invention and the plan structure sketch map of step S12 of the present invention.As shown in the figure: after forming this semiconductor layer 12, execution in step S12 forms an one source pole 14 and a drain electrode 16 on this semiconductor layer 12; Please consult Fig. 4 in the lump, the method that forms this source electrode 14 and this drain electrode 16 is first execution in step S30, deposits a first metal layer on this semiconductor layer 12; Then execution in step S31 deposits one second photoresist and is shielded from this first metal layer, again execution in step S32; Utilize one second mask that a photoetching process is carried out in this second photoresist shielding; Carry out an etching technics afterwards and form second photoresist shielding of patterning, get into step S33, remove not by this this first metal layer of second photoresist shielding of patterning part of covering; Last execution in step S34; Remove this second photoresist shielding of patterning, form this source electrode 14 and this drain electrode 16, other further can and drain in this source electrode 14 and a passivation layer is set on 16 respectively.
Please consult Fig. 2 G and Fig. 2 H in the lump, be respectively the cross-sectional view of step S13 of the present invention and the plan structure sketch map of step S13 of the present invention.As shown in the figure: after forming this source electrode 14 and being somebody's turn to do drain electrode 16; Execution in step S13; Form a separator 18 on this source electrode 14, this drain electrode 16 and this semiconductor layer 12; The material of this separator 18 comprises silica (SiOx), silicon nitride (SiNx) or combinations thereof, and its thickness is between
and
.
Consult Fig. 2 I and Fig. 2 J more in the lump, be respectively the cross-sectional view of step S14 of the present invention and the plan structure sketch map of step S14 of the present invention.As shown in the figure: after forming this separator 18, execution in step S14 forms a grid 20 and a capacitance electrode 22 on this separator 18; Please consult Fig. 5 in the lump, the method that forms this grid 20 and this capacitance electrode 22 is first execution in step S40, deposits one second metal level on this separator 18; Then execution in step S41 deposits one the 3rd photoresist and is shielded from this second metal level, again execution in step S42; Utilize one the 3rd mask that the 3rd photoresist is shielded and carry out a photoetching process, carry out an etching technics afterwards and form the 3rd a photoresist shielding of patterning, get into step S43; Remove not by this this second metal level of the 3rd photoresist shielding of patterning part of covering, last execution in step S44 removes this 3rd photoresist shielding of patterning; Form this grid 20 and this capacitance electrode 22, the active region 120 of this semiconductor layer 12 comprises one first active region 124 and one second active region 126, and this grid 20 comprises one first one 200 and 1 second one 202; Be located at and these first active region, 124 tops for first one 200 of this grid 20; Be located at and these second active region, 126 tops for second one 202 of this grid 20, and this capacitance electrode 22 is located at and these 122 corresponding positions, storage capacitors district further then execution in step S45; With this grid 20 is shielding; Active region 120 to this semiconductor layer 12 carries out the injection of P-ion, in this active region 120, forms a P-light ion doped region 128, and this P-ion implantation concentration is between 1E16 and 1E18 atom/cm
3Between, execution in step S46 carries out an activating process to this semiconductor layer 12 again, and with this P-light ion doped region 128 of activation, the temperature of this activating process is between 550 degree Celsius and 1000 degree Celsius.
Then consult Fig. 2 K and Fig. 2 L in the lump, be respectively the cross-sectional view of step S15 of the present invention and S16 and the plan structure sketch map of step S15 of the present invention and S16.As shown in the figure: after forming this grid 20 and this capacitance electrode 22; Execution in step S15; Form a dielectric layer 24 and a screen 26 in regular turn on this grid 20, this capacitance electrode 22 and this separator 18; Formed a thin-film transistor through above-mentioned steps, seen also Fig. 6, the method that forms this dielectric layer 24 and this screen 26 is first execution in step S50; Deposit a dielectric film and a shielded film in regular turn on this grid 20, this capacitance electrode 22 and this separator 18; Execution in step S51 utilizes one the 4th mask that this dielectric film and this shielded film are carried out a photoetching and etching technics again, forms this dielectric layer 24 and this screen 26; The material of above-mentioned dielectric layer 24 comprises silica, silicon nitride or combinations thereof; Its thickness is between
and
, through above-mentioned steps S51, execution in step S16; Form a contact hole 28 on this screen 26; And drain 16 correspondingly with this, and this drain electrode 16 is exposed, the method for this contact hole 28 of above-mentioned formation is to utilize the 4th mask that this dielectric film and this shielded film are carried out this chemical wet etching technology earlier; Further in this formation one of shielded film surface and these 16 corresponding opening patterns 30 that drain; Through this this shielded film of patterns of openings 30 dry etchings and this dielectric film, and be an etching stop surface, and then form this contact hole 28 with this drain electrode 16.
Consult Fig. 2 M and Fig. 2 N at last in the lump, be respectively the cross-sectional view of step S17 of the present invention and the plan structure sketch map of step S17 of the present invention.As shown in the figure: after forming this contact hole 28, execution in step S17 forms a conductive layer 32 on this screen 26; And, seeing also Fig. 7 through this contact hole 28 and these drain electrode 16 electric connections, the method that forms this conductive layer 32 is first execution in step S60; Deposit a conductive film on this screen 26, and electrically connect, then execution in step S61 through this contact hole 28 and this drain electrode 16; Deposit one the 4th photoresist and be shielded from this conductive film, execution in step S62 utilizes one the 5th mask that the 4th photoresist is shielded and carries out a photoetching process again; Carry out an etching technics afterwards and form the 4th a photoresist shielding of patterning, get into step S63, remove not by this this conductive film of the 4th photoresist shielding of patterning part of covering; Last execution in step S64 removes the 4th photoresist shielding of patterning, forms this conductive layer 32; Wherein, the material of this conductive layer 32 comprises tin indium oxide (ITO), indium zinc oxide (IZO) or combinations thereof.
Constitute this dot structure by above-mentioned steps, storage capacitors of the present invention district is made up of this semiconductor layer, this separator and this capacitance electrode, can significantly improve the storage capacitors amount; Can't reduce aperture opening ratio, and the metal in this dot structure is leaked outside, cause electrical problem to produce; And manufacturing approach of the present invention has five road masking process; Reduce the complexity of technology, effectively improve output capacity, reduce production costs; The present invention joins this screen in masking process with this dielectric layer, can overcome the problem of electrical phase mutual interference (Cross-talk).
The above person; Be merely a preferred embodiment of the present invention; Be not to be used for limiting the scope that the present invention implements, the equalization of doing according to the described shape of claim of the present invention, structure, characteristic and spirit such as changes and modifies, and all should be included in the claim of the present invention.
Claims (13)
1. a dot structure manufacturing approach is characterized in that, this dot structure manufacturing approach comprises:
One substrate is provided;
Form semi-conductor layer on this substrate, the step that wherein forms described semiconductor layer comprises:
Deposition semiconductor film is on described substrate;
Forming one first photoresist is shielded from this semiconductive thin film;
Utilize one first mask that a photoetching process is carried out in this first photoresist shielding, form first photoresist shielding of patterning;
Through this first photoresist shielding of patterning described semiconductive thin film carried out one first ion inject to form a storage capacitors district, this storage capacitors district is a heavy ion doped region; And
Remove first photoresist shielding of described patterning, form described semiconductor layer;
Formation one source pole and drains in this semiconductor layer top and is in direct contact with it, and the step that forms described source electrode and described drain electrode comprises:
Deposit a first metal layer in described semiconductor layer top;
Depositing one second photoresist is shielded from this first metal layer;
Utilize one second mask that a photoetching process is carried out in this second photoresist shielding, form second photoresist shielding of patterning;
Remove not by this described the first metal layer of second photoresist shielding of the patterning part of covering; And
Remove second photoresist shielding of described patterning, form described source electrode and described drain electrode;
Form a separator and be covered in this source electrode and drain electrode;
After the step that forms this source electrode and this drain electrode, form a grid and a capacitance electrode simultaneously on this separator;
Forming a dielectric layer is covered on this grid and this capacitance electrode;
Forming a screen is covered on this dielectric layer;
Form a contact hole in described drain electrode top to expose this drain electrode; And
Forming a conductive layer directly electrically connects with described drain electrode on described screen and through described contact hole;
Wherein, the step that forms described dielectric layer, described screen and described contact hole comprises:
Successive sedimentation one dielectric film and a shielded film are on described grid, described capacitance electrode and described separator; And
Utilize one the 4th mask that described dielectric film and described shielded film are carried out a chemical wet etching technology, form described dielectric layer, described screen and described contact hole.
2. the method for claim 1 is characterized in that, forms this dielectric layer and is covered in the step on this grid and this capacitance electrode, and this dielectric layer is covered on this grid and this capacitance electrode fully.
3. the method for claim 1 is characterized in that, forms in the step that this separator is covered in this source electrode and drain electrode, and this separator is covered in this source electrode and drain electrode fully.
4. the method for claim 1 is characterized in that, forms this screen and is covered in the step on this dielectric layer, and this screen is covered on this dielectric layer fully.
5. the method for claim 1; It is characterized in that; Described first photoresist shielding is transferred mask for half; Comprise one first thickness and one second thickness of first photoresist shielding of the respectively corresponding described patterning of a shading region and half penetrating region, wherein this first thickness is greater than this second thickness.
6. the method for claim 1 is characterized in that, it is that the corresponding region forms p+ ion zone on described semiconductor layer that described first ion is injected to p+ ion injection, and wherein this p+ ion implantation concentration is between 1E18 and 1E21atom/cm
3Between.
7. method as claimed in claim 6 is characterized in that, this dot structure manufacturing approach further comprises carries out an activating process, the described p+ ion of activation zone.
8. method as claimed in claim 7 is characterized in that, the temperature of described activating process is between 550 degree Celsius and 1000 degree Celsius.
9. the method for claim 1 is characterized in that, the step that forms described grid and described capacitance electrode comprises:
Deposit one second metal level on described separator;
Depositing one the 3rd photoresist is shielded from this second metal level;
Utilize one the 3rd mask that the 3rd photoresist is shielded and carry out a photoetching process, form the 3rd a photoresist shielding of patterning;
Remove not by this described second metal level of the 3rd photoresist shielding of the patterning part of covering; And
Remove the 3rd photoresist shielding of described patterning, form described grid and described capacitance electrode.
10. the method for claim 1; It is characterized in that; Form that further to comprise with this grid after the step of described grid and described capacitance electrode be a shielding; It is that the corresponding region forms p-ion zone on described semiconductor layer that described semiconductor layer is carried out p-ion injection, and wherein this P-ion implantation concentration is between 1E17 and 1E19atom/cm
3Between.
11. method as claimed in claim 10 is characterized in that, this dot structure manufacturing approach further comprises carries out an activating process, the described p-ion of activation zone.
12. dot structure manufacturing approach as claimed in claim 11 is characterized in that, the temperature of described activating process is between 550 degree Celsius and 1000 degree Celsius.
13. method as claimed in claim 10 is characterized in that, the step that forms described conductive layer comprises:
Deposit a conductive film on described screen, and electrically connect through described contact hole and described drain electrode;
Depositing one the 4th photoresist is shielded from this conductive film;
Utilize one the 5th mask that the 4th photoresist is shielded and carry out a photoetching process, form the 4th a photoresist shielding of patterning;
Remove not by this described conductive film of the 4th photoresist shielding of the patterning part of covering; And
Remove described the 4th photoresist shielding of patterning, form described conductive layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210146302.0A CN102664162B (en) | 2007-03-27 | 2007-03-27 | A method for manufacturing a pixel structure |
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| CN201210146302.0A CN102664162B (en) | 2007-03-27 | 2007-03-27 | A method for manufacturing a pixel structure |
| CN 200710091534 CN101060126A (en) | 2007-03-27 | 2007-03-27 | Thin film transistor and pixel structure and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110085625A (en) * | 2018-06-19 | 2019-08-02 | 广东聚华印刷显示技术有限公司 | Top emissive displays part and preparation method thereof |
| WO2019242384A1 (en) * | 2018-06-19 | 2019-12-26 | 广东聚华印刷显示技术有限公司 | Backplane structure of display panel and preparation method therefor, and top-emitting display panel |
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| CN102881571B (en) | 2012-09-28 | 2014-11-26 | 京东方科技集团股份有限公司 | Active layer ion implantation method and active layer ion implantation method for thin-film transistor |
| CN116632001B (en) * | 2023-07-24 | 2023-10-13 | 合肥晶合集成电路股份有限公司 | Semiconductor device and design assisting device for semiconductor device |
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| CN1170196C (en) * | 2001-06-04 | 2004-10-06 | 友达光电股份有限公司 | Method for manufacturing thin film transistor liquid crystal display |
| CN100339964C (en) * | 2005-04-29 | 2007-09-26 | 友达光电股份有限公司 | Fabrication method of metal oxide semiconductor with lightly doped drain |
| CN100483233C (en) * | 2006-07-18 | 2009-04-29 | 友达光电股份有限公司 | Pixel structure of flat panel display and manufacturing method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085625A (en) * | 2018-06-19 | 2019-08-02 | 广东聚华印刷显示技术有限公司 | Top emissive displays part and preparation method thereof |
| WO2019242384A1 (en) * | 2018-06-19 | 2019-12-26 | 广东聚华印刷显示技术有限公司 | Backplane structure of display panel and preparation method therefor, and top-emitting display panel |
| CN110085625B (en) * | 2018-06-19 | 2021-12-21 | 广东聚华印刷显示技术有限公司 | Top-emission type display device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102664162B (en) | 2015-08-12 |
| CN101060126A (en) | 2007-10-24 |
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