CN112259556A - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
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- CN112259556A CN112259556A CN202011096584.9A CN202011096584A CN112259556A CN 112259556 A CN112259556 A CN 112259556A CN 202011096584 A CN202011096584 A CN 202011096584A CN 112259556 A CN112259556 A CN 112259556A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
The invention provides an array substrate and a preparation method thereof, the array substrate comprises a substrate, an active layer, a first grid insulating layer, a grid layer, an interlayer dielectric layer, a photosensitive layer and a shielding layer, wherein the active layer is arranged on the substrate, the active layer comprises a semiconductor part and a first doping part, the first doping part is arranged on two sides of the semiconductor part, the first grid insulating layer covers the substrate and the active layer, the grid layer is arranged on the first grid insulating layer and is positioned on the semiconductor part, the interlayer dielectric layer covers the first grid insulating layer and the grid layer, the interlayer dielectric layer comprises a first through hole, the first through hole penetrates through the first grid insulating layer and the interlayer dielectric layer to expose the first doping part, the photosensitive layer is arranged on the first through hole and the interlayer dielectric layer, and the shielding layer is arranged on the photosensitive layer. By arranging the photosensitive layer on the first doping part of the active layer, the production cost is reduced, and the yield of the array substrate is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
Fingerprint identification technology has been widely applied to small and medium-sized panels, and mainly includes capacitive type, ultrasonic type, and optical type. Compared with the capacitive and ultrasonic fingerprint identification technologies, the optical fingerprint identification technology has the advantages of good stability, strong antistatic capability, good penetrating power and the like. At present, the photosensitive sensor is usually integrated inside the screen to realize full-screen fingerprint identification, which can greatly improve the user experience, but the integrated array substrate process will become complicated, so that the preparation cost is increased and the product yield is reduced.
Disclosure of Invention
The invention provides an array substrate and a preparation method thereof, which are used for reducing the preparation cost of the array substrate and improving the yield of the array substrate.
The invention provides an array substrate, comprising:
a substrate;
an active layer disposed on the substrate, the active layer including a semiconductor portion and a first doping portion disposed at both sides of the semiconductor portion;
a first gate insulating layer covering the substrate and the active layer;
a gate layer disposed on the first gate insulating layer, the gate layer being over the semiconductor portion;
an interlayer dielectric layer covering the first gate insulating layer and the gate layer, the interlayer dielectric layer including a first via hole penetrating the first gate insulating layer and the interlayer dielectric layer to expose the first doped portion;
the photosensitive layer is arranged on the first through hole and the interlayer dielectric layer; and
and the shielding layer is arranged on the photosensitive layer.
In the array substrate provided by the invention, the array substrate further comprises a doping layer, the doping layer is arranged on the photosensitive layer, and the shielding layer is arranged on the doping layer.
In the array substrate provided by the invention, the shielding layer is a second gate insulating layer, the shielding layer includes a second through hole, and the second through hole penetrates through the shielding layer to expose the photosensitive layer.
In the array substrate provided by the invention, the shielding layer is an indium tin oxide layer.
In the array substrate provided by the invention, the array substrate further comprises a flat layer, the flat layer covers the interlayer dielectric layer, the photosensitive layer and the shielding layer, the flat layer comprises a third through hole, and the third through hole penetrates through the flat layer to expose the shielding layer.
In the array substrate provided by the present invention, the array substrate further includes a first passivation layer covering the shielding layer and the planarization layer, the first passivation layer includes a fourth through hole, and the fourth through hole penetrates through the first passivation layer and the shielding layer to expose the photosensitive layer.
In the array substrate provided by the invention, the array substrate further comprises a common electrode layer, and the common electrode layer is arranged on the first passivation layer and is electrically connected with the photosensitive layer through the fourth through hole.
The invention also provides a preparation method of the array substrate, which comprises the following steps:
providing a substrate;
an active layer is arranged on the substrate and comprises a semiconductor part and first doping parts, and the first doping parts are arranged on two sides of the semiconductor part;
disposing a first gate insulating layer on the substrate and the active layer;
a gate layer disposed on the first gate insulating layer, the gate layer being over the semiconductor portion;
disposing an interlayer dielectric layer on the first gate insulating layer and the gate layer, the interlayer dielectric layer including a first via hole penetrating the first gate insulating layer and the interlayer dielectric layer to expose the first doped portion;
a photosensitive layer is arranged on the first through hole and the interlayer dielectric layer; and
and arranging a shielding layer on the photosensitive layer.
In the method for manufacturing an array substrate provided by the present invention, after the step of disposing a shielding layer on the photosensitive layer, the method further includes:
and forming a doping layer on the photosensitive layer, wherein the shielding layer covers the doping layer and is a second grid insulation layer.
In the preparation method of the array substrate provided by the present invention, after the step of disposing the photosensitive layer on the first through hole and the interlayer dielectric layer, and before the step of disposing the shielding layer on the photosensitive layer, the method further includes:
and arranging a doping layer on the photosensitive layer, wherein the shielding layer covers the doping layer and is an indium tin oxide layer.
The invention provides an array substrate and a preparation method thereof, the array substrate comprises a substrate, an active layer, a first grid insulating layer, a grid layer, an interlayer dielectric layer, a photosensitive layer and a shielding layer, wherein the active layer is arranged on the substrate, the active layer comprises a semiconductor part and a first doping part, the first doping part is arranged on two sides of the semiconductor part, the first grid insulating layer covers the substrate and the active layer, the grid layer is arranged on the first grid insulating layer and is positioned on the semiconductor part, the interlayer dielectric layer covers the first grid insulating layer and the grid layer, the interlayer dielectric layer comprises a first through hole, the first through hole penetrates through the first grid insulating layer and the interlayer dielectric layer to expose the first doping part, the photosensitive layer is arranged on the first through hole and the interlayer dielectric layer, and the shielding layer is arranged on the photosensitive layer. By arranging the photosensitive layer on the first doping part of the active layer, the production cost is reduced, and the yield of the array substrate is improved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
Fig. 1 is a cross-sectional view of a first structure of an array substrate according to the present invention.
Fig. 2 is a cross-sectional view of a second structure of the array substrate provided by the present invention.
FIG. 3 is a flow chart of a method for manufacturing an array substrate according to the present invention
Fig. 4-20 are cross-sectional views of flow structures of a method for manufacturing an array substrate according to the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a cross-sectional view of a first structure of an array substrate according to the present invention. The present invention provides an array substrate 10. The array substrate 10 includes a substrate 100, an active layer 200, a first gate insulating layer 300, a gate layer 400, an interlayer dielectric layer 500, a photosensitive layer 600, and a blocking layer 700.
In one embodiment, the array substrate 10 further includes a light-shielding layer 800. The light-shielding layer 800 is disposed on the substrate 100. The light-shielding layer 800 is used to prevent external light from being incident into the array substrate, so as to prevent threshold voltage drift.
In an embodiment, the array substrate 10 further includes a buffer layer 900. The buffer layer 900 is disposed on the substrate 100 and the light-shielding layer 800.
The active layer 200 is disposed on the substrate 100. The active layer 200 includes a semiconductor portion 210 and a first doping portion 220. The first doping part 220 is disposed at two sides of the semiconductor part 210.
Specifically, the active layer 200 is disposed on the buffer layer 900 and on the light-shielding layer 800. The material of the active layer 200 is polysilicon. The active layer 200 includes a semiconductor portion 210, a first doping portion 220, and a second doping portion 230. The second doping part 230 is disposed at both sides of the semiconductor part 210. The first doping part 220 is located at both sides of the second doping part 230 away from the semiconductor part 210. The first doping portion 220 and the second doping portion 230 are both doped N-type. The doping concentration of the first doping portion 220 is greater than that of the second doping portion 230. The second doping part 230 is doped with N-type with high concentration, so that the thin film transistor can be easily in ohmic contact.
The first gate insulating layer 300 covers the substrate 100 and the active layer 200. Specifically, the first gate insulating layer 300 covers the buffer layer 900 and the active layer 200.
The gate layer 400 is disposed on the first gate insulating layer 300. The gate layer 400 is located above the semiconductor portion 210.
The interlayer dielectric layer 500 covers the first gate insulating layer 300 and the gate layer 400. The material of the interlayer dielectric layer 500 includes one or a combination of SiNx and SiOx. The interlayer dielectric layer 500 may be formed by stacking a plurality of layers. The interlayer dielectric layer 500 includes a first via 501, a first via 502, and a second via 503. The first via 501 penetrates the first gate insulating layer 300 and the interlayer dielectric layer 500 to expose one side of the first doping part 220. The first via hole 502 penetrates the first gate insulating layer 300 and the interlayer dielectric layer 500 to expose the first doping part 220 on the same side as the first via hole 501. The second via 503 penetrates the first gate insulating layer 300 and the interlayer dielectric layer 500 to expose the other side of the first doping part 220.
In an embodiment, the array substrate 10 further includes a first metal layer 1000. The first metal layer 1000 includes a source 1010, a drain 1020, and a routing portion 1030. The source 1010 is disposed in the first via hole 502 and on the interlayer dielectric layer 500, and is electrically connected to one side of the first doping part 220. The drain 1020 is disposed in the second via 503 and on the interlayer dielectric layer 500, and is electrically connected to the other side of the first doped portion 220. The active layer 200, the first gate insulating layer 300, the gate layer 400, the interlayer dielectric layer 500, the source electrode 1010, and the drain electrode 1020 form a thin film transistor 1099.
The photosensitive layer 600 is disposed on the first via 501 and the interlayer dielectric layer 500, and is electrically connected to the first doping part 220. The photosensitive layer 600 is made of amorphous silicon.
The array substrate 10 further includes a doping layer 1100. The doped layer 1100 is disposed on the photosensitive layer 600. The doped layer 1100 is doped P-type. The first doping part 220, the photosensitive layer 600 and the doping layer 1100 form a photosensitive sensor 1199.
The shielding layer 700 is disposed on the photosensitive layer 600 and the doped layer 1100. The blocking layer 700 is a second gate insulating layer 700. The material of the shielding layer 700 is SixOyAnd SixNyOne or a combination of several of them. The shielding layer 700 includes a second through hole 701. The second through hole 701 penetrates through the shielding layer 700 to expose the photosensitive layer 600. Specifically, the second via hole 701 penetrates through the shielding layer 700 to expose the doped layer 1100. And when the shielding layer is the second grid insulation layer, the second grid insulation layer is used as a photomask to prepare the doping layer.
In one embodiment, the array substrate 10 further includes a planarization layer 1200. The planarization layer 1200 covers the interlayer dielectric layer 500, the photosensitive layer 600, the doping layer 1100, and the blocking layer 700. The planarization layer 1200 includes a third via 1201, a third via 1202, and a fourth via 1203. The third via 1201 penetrates the planarization layer 1200 and the blocking layer 700, and penetrates the second via 701 to expose the doped layer 1100. The third via 1202 extends through the planarization layer 1200 to expose the source 1010. The fourth via 1203 penetrates through the planarization layer 1200 to expose the trace portion 1030.
In an embodiment, the array substrate 10 further includes a second metal layer 1300. The second metal layer 1300 is disposed on the planarization layer 1400 and located between the third via 1202 and the fourth via 1203.
In one embodiment, the array substrate 10 further includes a second passivation layer 1400. The second passivation layer 1400 covers the shielding layer 700, the planarization layer 1200, and the second metal layer 1300. The second passivation layer 1400 includes a fifth via 1401. The fifth via 1401 penetrates the second passivation layer 1400 and penetrates the third via 1202 to expose the source 1010. The second through hole 701 further penetrates the second passivation layer 1400.
In an embodiment, the array substrate 10 further includes a third metal layer 1500. The third metal layer 1500 is disposed in the fifth via 1401 and the third via 1202, and is electrically connected to the source 1010.
In an embodiment, the array substrate 10 further includes a third passivation layer 1600. The third passivation layer 1600 covers the second passivation layer 1400. The third passivation layer 1600 includes a sixth via 1601. The sixth via 1601 penetrates through the third passivation layer 1600 to expose the second passivation layer 1400. The second via 701 also penetrates the third passivation layer 1600.
In one embodiment, the array substrate 10 further includes a metal oxide layer 1700. The metal oxide layer 1700 is disposed in the sixth via 1601 and on the third passivation layer 1600.
In an embodiment, the array substrate 10 further includes a first passivation layer 1800. The first passivation layer 1800 is disposed on the planarization layer 1200 and the second metal layer 1300. Specifically, the first passivation layer 1800 covers the third passivation layer 1600 and the metal oxide layer 1700. The first passivation layer 1800 includes a pre-fabricated hole 1801, a fourth through hole 1802, and a seventh through hole 1803. The pre-hole 1801 penetrates the first passivation layer 1800 and the third passivation layer 1600 to expose the second metal layer 1300. The fourth through hole 1802 penetrates the first passivation layer 1800, the third passivation layer 1600, and the second passivation layer 1400, and penetrates the second through hole 701 and the third through hole 1201 to expose the doped layer 1100. The seventh via hole 1803 penetrates through the planarization layer 1200, the second passivation layer 1400, the third passivation layer 1600, and the first passivation layer 1800, and penetrates through the fourth via hole 1203 to expose the trace portion 1030.
In one embodiment, the array substrate 10 further includes a common electrode layer 1900. The common electrode layer 1900 is disposed on the first passivation layer 1800 and electrically connected to the photosensitive layer 600 through the fourth through hole 1802. Specifically, the common electrode layer 1900 is disposed on the first passivation layer 1800. The common electrode layer 1900 is electrically connected to the doped layer 100 through the fourth through hole 1802, the second through hole 701, and the third through hole 1201. The common electrode layer 1900 is electrically connected to the second metal layer 1300 through the pre-fabricated hole 1801. The common electrode layer 1900 is electrically connected to the trace portion 1030 through the seventh via 1803 and the fourth via 1203. The common electrode layer 1900 is made of indium tin oxide.
Referring to fig. 2, fig. 2 is a cross-sectional view of a second structure of an array substrate according to the present invention. Fig. 2 is different from fig. 1 in that: the shielding layer 700 is an ito layer. The material of the shielding layer 700 is indium tin oxide. The shielding layer 700 has no through-hole. The shielding layer 700 is used to prevent the doped layer 1100 from being damaged when the array substrate 10 is opened subsequently, and to increase the contact area with the subsequent pixel electrode layer. Other structures are shown in fig. 1, and are not described herein.
The invention provides an array substrate, wherein an active layer of a thin film transistor 1099 and a doped layer of a photosensitive sensor 1199 are prepared by the same layer of polycrystalline silicon, so that the thin film transistor and the photosensitive sensor are arranged in a horizontal mode, and the preparation cost is reduced when the fingerprint identification function of the thin film transistor and the photosensitive sensor is integrated in the array substrate; a photosensitive layer is arranged on the active layer, the active layer is prepared from polycrystalline silicon, and the photosensitive layer is prepared from amorphous silicon, so that the photoproduction current of the photosensitive sensor is improved; after the doping layer is completed, the shielding layer is arranged on the doping layer, the second grid insulation layer is used as a photomask, the doping layer is prepared, or the doping layer is prevented from being damaged in subsequent opening, meanwhile, the overlapping contact area of the doping layer and the pixel electrode layer is increased, the risk of overlapping fracture of the doping layer is further reduced, and the yield of the array substrate is improved.
Referring to fig. 3 and fig. 4 to 20, fig. 3 is a flowchart illustrating a method for manufacturing an array substrate according to the present invention, and fig. 4 to 20 are cross-sectional views illustrating a flow structure of the method for manufacturing an array substrate according to the present invention. The invention also provides a preparation method of the array substrate. The method comprises the following steps:
21. a substrate 100 is provided.
Please refer to fig. 4 and 5. After the step of providing a substrate 100, the method further includes:
a light-shielding layer 800 material is provided on the substrate 100, and the light-shielding layer 800 is formed by etching and exposure. The material of the light-shielding layer 800 includes Mo, Cu, Al, Fe, and the like. The shading layer is used for preventing external light from being emitted into the array substrate, so that threshold voltage drift is avoided.
After the step of disposing the light-shielding layer 800 on the substrate 100, the method further includes:
a buffer layer 900 is formed on the substrate 100 and the light-shielding layer 800.
22. An active layer 200 is disposed on the substrate 100, the active layer 200 includes a semiconductor portion 210 and a first doping portion 220, and the first doping portion 220 is disposed on both sides of the semiconductor portion 210.
Please refer to fig. 5 and 6. Specifically, the active layer 200 material is deposited on the buffer layer 900, and the active layer 220 is formed by exposure etching. The active layer 200 is positioned on the light-shielding layer 800. The active layer 200 is doped with phosphorus ions, arsenic ions, antimony ions, or the like to form a semiconductor portion 210 and a first doped portion 220. The first doping part 220 is disposed at two sides of the semiconductor part 210.
23. A first gate insulating layer 300 is disposed on the substrate 100 and the active layer 200.
Please refer to fig. 7. Specifically, a first gate insulating layer 300 material is disposed on the buffer layer 900 and the active layer 200 to form the first gate insulating layer 300.
24. A gate layer 400 is disposed on the first gate insulating layer 300, and the gate layer 400 is located above the semiconductor portion 210.
Please refer to fig. 7. Specifically, a gate layer 400 material is provided on the first gate insulating layer 300, and the gate layer 400 is formed by exposure etching.
After the step of forming the gate electrode layer 400 on the first gate insulating layer 300, the method further includes:
the semiconductor portion 210 of the active layer 200 is doped using the gate layer 400 as a mask, thereby forming a second doped portion 230. The second doping part 230 is disposed at both sides of the semiconductor part 210. The first doping part 220 is located at both sides of the second doping part 230 away from the semiconductor part 210. The first doping portion 220 and the second doping portion 230 are both doped N-type. The doping concentration of the first doping portion 220 is greater than that of the second doping portion 230. The second doping part 230 is doped with N-type with high concentration, so that the thin film transistor can be easily in ohmic contact.
25. An interlayer dielectric layer 500 is disposed on the first gate insulating layer 300 and the gate layer 400, the interlayer dielectric layer 500 includes a first via 501, and the first via 501 penetrates through the first gate insulating layer 300 and the interlayer dielectric layer 500 to expose the first doping part 220.
Please refer to fig. 8 and 9. Specifically, an interlayer dielectric layer 500 material is disposed on the first gate insulating layer 300 and the gate layer 400, and the interlayer dielectric layer 500 is formed by exposure and etching. The interlevel dielectric layer 500 includes a first via 502 and a second via 503. The first via 502 penetrates the first gate insulating layer 300 and the interlayer dielectric layer 500 to expose one side of the first doping part 220. The second via 503 penetrates the first gate insulating layer 300 and the interlayer dielectric layer 500 to expose the other side of the first doping part 220. The material of the interlayer dielectric layer 500 includes one or a combination of SiNx and SiOx. The interlayer dielectric layer 500 may be formed by stacking a plurality of layers.
After the step of disposing the interlayer dielectric layer 500 on the first gate insulating layer 300 and the gate layer 400, the method further includes:
depositing a first metal layer 1000 material on the interlayer dielectric layer 500, the first via hole 502 and the second via hole 503, and forming a source 1010, a drain 1020 and a trace 1030 by an exposure etching method. The source 1010 is disposed in the first via hole 502 and on the interlayer dielectric layer 500, and is electrically connected to one side of the first doping part 220. The drain 1020 is disposed in the second via 503 and on the interlayer dielectric layer 500, and is electrically connected to the other side of the first doped portion 220. The active layer 200, the first gate insulating layer 300, the gate layer 400, the interlayer dielectric layer 500, the source electrode 1010, and the drain electrode 1020 form a thin film transistor 1099.
After the step of forming the source 1010, the drain 1020 and the routing portion 1030 on the interlayer dielectric layer 500, the first via 502 and the second via 503, the method further includes:
a first via 501 is etched in the first gate layer 300 and the planarization layer 500, and the first via 501 exposes the first doping part 220 on the same side as the first via 502.
26. A photosensitive layer 600 is disposed on the first through hole 501 and the interlayer dielectric layer 500.
Please refer to fig. 10. Specifically, a photosensitive layer 600 material is disposed in the interlayer dielectric layer 500 and the first through hole 501, and the photosensitive layer 600 is formed by an exposure etching method. The photosensitive layer 600 is made of amorphous silicon.
27. A shielding layer 700 is disposed on the photosensitive layer 600.
Please refer to fig. 11-13. A material for the mask layer 700 is provided on the photosensitive layer 600, and the mask layer 700 is formed by an exposure etching method. The shielding layer 700 includes a second through hole 701. The second through hole 701 penetrates through the shielding layer 700 to expose the photosensitive layer 600. The material of the shielding layer 700 is SixOyAnd SixNyOne or a combination of several of them. And when the shielding layer is the second grid insulation layer, the second grid insulation layer is used as a photomask to prepare the doping layer.
After the step of disposing the shielding layer 700 on the photosensitive layer 600, the method further includes:
the doped layer 1100 is prepared using the second gate insulating layer 700 as a mask. The doped layer 1100 is disposed on the photosensitive layer 600. The second gate insulating layer 700 covers the doped layer 1100. The second via 701 penetrates the blocking layer 700 to expose the doping layer 1100.
In another embodiment, after the step of disposing the photosensitive layer 600 on the first through hole 501 and the interlayer dielectric layer 500, and before the step of disposing the shielding layer 700 on the photosensitive layer 600, the method further includes:
a doped layer 1100 is disposed on the photosensitive layer 600. The blocking layer 700 covers the doped layer 1100. The shielding layer 700 is an ito layer. The material of the shielding layer 700 is indium tin oxide. The shielding layer 700 is used to prevent the doped layer 1100 from being damaged when the array substrate 10 is opened subsequently, and to increase the contact area with the subsequent pixel electrode layer.
A doped layer 1100 is prepared using the second gate insulating layer 700 as a mask. After the step of disposing the doping layer 1100 on the photosensitive layer 600, the method further includes:
please continue to refer to fig. 13. A planarization layer 1200 material is disposed on the interlayer dielectric layer 500, the first metal layer 1000, the photosensitive layer 600, and the doping layer 600, and the planarization layer 1200 is formed by an exposure etching method. The planarization layer 1200 includes a third via 1201, a third via 1202, and a fourth via 1203. The third through hole 1201 penetrates the planarization layer 1200 to expose the shielding layer 700. The third via 1202 extends through the planarization layer 1200 to expose the source 1010. The fourth via 1203 penetrates through the planarization layer 1200 to expose the trace portion 1030.
After the step of forming the planarization layer 1200 on the interlayer dielectric layer 500, the second metal layer 1300, the photosensitive layer 600, and the doped layer 600, the method further includes:
please refer to fig. 14. And (3) arranging a second metal layer 1300 material on the flat layer 1200, and forming the second metal layer 1300 by an exposure etching method. And the second metal layer 1300 is located between the third via 1202 and the fourth via 1203.
After the step of forming the second metal layer 1300 on the planarization layer 1200, the method further includes:
please refer to fig. 15. And arranging a second passivation layer 1400 material on the shielding layer 700, the planarization layer 1200, the third via hole 1202, the fourth via hole 1203 and the second metal layer 1300, and forming a second passivation layer 1400 by an exposure etching method. The second passivation layer 1400 includes a fifth via 1401. The fifth via 1401 penetrates the second passivation layer 1400 and penetrates the third via 1202 to expose the source 1010.
After the step of forming the second passivation layer 1400 on the shielding layer 700, in the planarization layer 1200, the third via 1202, and the fourth via 1203, the method further includes:
please refer to fig. 16. A third metal layer 1500 material is disposed in the fifth via 1401, the third via 1202 and the second passivation layer 1400, and the third metal layer 1500 is formed by an exposure etching method.
After the step of forming the third metal layer 1500 in the fifth via 1401 and on the second passivation layer 1400, the method further includes:
please refer to fig. 17. A third passivation layer 1600 material is disposed on the second passivation layer 1400 and the third metal layer 1500, and the third passivation layer 1600 is formed by an exposure etching method. The third passivation layer 1600 includes a sixth via 1601. The sixth via 1601 penetrates through the third passivation layer 1600 to expose the second passivation layer 1400.
After the step of forming the third passivation layer 1600 on the second passivation layer 1400 and the third metal layer 1500, the method further includes:
please refer to fig. 18. And arranging a metal oxide layer 1700 material on the third passivation layer 1600 and the sixth via 1601, and forming the metal oxide layer 1700 by an exposure etching method.
After the step of forming the metal oxide layer 1700 on the third passivation layer 1600 and the sixth via 1601, the method further includes:
please refer to fig. 19. A first passivation layer 1800 material is disposed on the planarization layer 1200 and the second metal layer 1300, and the first passivation layer 1800 is formed by an exposure etching method. The first passivation layer 1800 includes a pre-fabricated hole 1801, a fourth through hole 1802, and a seventh through hole 1803. The pre-hole 1801 penetrates the first passivation layer 1800 and the third passivation layer 1600 to expose the second metal layer 1300. The fourth through hole 1802 penetrates the first passivation layer 1800, the third passivation layer 1600, and the second passivation layer 1400, and penetrates the second through hole 701 and the third through hole 1201 to expose the doped layer 1100. The seventh via hole 1803 penetrates through the second passivation layer 1400, the third passivation layer 1600, and the first passivation layer 1800, and penetrates through the fourth via hole 1203 to expose the routing portion 1030.
After the step of forming the first passivation layer 1800 on the planarization layer 1200 and the second metal layer 1300, the method further includes:
please refer to fig. 20. A common electrode layer 1900 is formed by providing a common electrode layer 1900 material on the second via 1202 and the planarization layer 1200 and exposing and etching the common electrode layer 1900. The common electrode layer 1900 is electrically connected to the doped layer 100 through the fourth through hole 1802 and the third through hole 1201. The common electrode layer 1900 is electrically connected to the second metal layer 1300 through the pre-fabricated hole 1801. The common electrode layer 1900 is electrically connected to the trace portion 1030 through the seventh via 1803 and the fourth via 1203. The common electrode layer 1900 is made of indium tin oxide.
In the invention, the active layer of the thin film transistor and the doping part of the photosensitive sensor are prepared by the same layer of polycrystalline silicon, namely, the thin film transistor and the photosensitive sensor with the fingerprint identification function can be integrated into the array substrate only by adding two mask processes without additionally introducing phosphine and borane gas, thereby reducing the production cost.
The invention provides an array substrate and a preparation method thereof, the array substrate comprises a substrate, an active layer, a first grid insulating layer, a grid layer, an interlayer dielectric layer, a photosensitive layer and a shielding layer, wherein the active layer is arranged on the substrate, the active layer comprises a semiconductor part and a first doping part, the first doping part is arranged on two sides of the semiconductor part, the first grid insulating layer covers the substrate and the active layer, the grid layer is arranged on the first grid insulating layer and is positioned on the semiconductor part, the interlayer dielectric layer covers the first grid insulating layer and the grid layer, the interlayer dielectric layer comprises a first through hole, the first through hole penetrates through the first grid insulating layer and the interlayer dielectric layer to expose the first doping part, the photosensitive layer is arranged on the first through hole and the interlayer dielectric layer, and the shielding layer is arranged on the photosensitive layer. By arranging the photosensitive layer on the first doping part of the active layer, the production cost is reduced, and the yield of the array substrate is improved.
The embodiments of the present invention are described in detail, and the principle and the embodiments of the present invention are explained by applying specific examples, and the descriptions of the above embodiments are only used to help understanding the technical solutions and the core ideas of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. An array substrate, comprising:
a substrate;
an active layer disposed on the substrate, the active layer including a semiconductor portion and a first doping portion disposed at both sides of the semiconductor portion;
a first gate insulating layer covering the substrate and the active layer;
a gate layer disposed on the first gate insulating layer, the gate layer being over the semiconductor portion;
an interlayer dielectric layer covering the first gate insulating layer and the gate layer, the interlayer dielectric layer including a first via hole penetrating the first gate insulating layer and the interlayer dielectric layer to expose the first doped portion;
the photosensitive layer is arranged on the first through hole and the interlayer dielectric layer; and
and the shielding layer is arranged on the photosensitive layer.
2. The array substrate of claim 1, further comprising a doped layer disposed on the photosensitive layer, wherein the shielding layer is disposed on the doped layer.
3. The array substrate of claim 1, wherein the shielding layer is a second gate insulating layer, the shielding layer comprises a second via hole, and the second via hole penetrates through the shielding layer to expose the photosensitive layer.
4. The array substrate of claim 1, wherein the shielding layer is an indium tin oxide layer.
5. The array substrate of claim 1, further comprising a planarization layer covering the interlayer dielectric layer, the photosensitive layer, and the shielding layer, the planarization layer comprising a third via hole penetrating the planarization layer to expose the shielding layer.
6. The array substrate of claim 5, further comprising a first passivation layer covering the blocking layer and the planarization layer, the first passivation layer comprising a fourth via that penetrates the first passivation layer and the blocking layer to expose the photosensitive layer.
7. The array substrate of claim 6, further comprising a common electrode layer disposed on the first passivation layer and electrically connected to the photosensitive layer through the fourth via hole.
8. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate;
an active layer is arranged on the substrate and comprises a semiconductor part and first doping parts, and the first doping parts are arranged on two sides of the semiconductor part;
disposing a first gate insulating layer on the substrate and the active layer;
a gate layer disposed on the first gate insulating layer, the gate layer being over the semiconductor portion;
disposing an interlayer dielectric layer on the first gate insulating layer and the gate layer, the interlayer dielectric layer including a first via hole penetrating the first gate insulating layer and the interlayer dielectric layer to expose the first doped portion;
a photosensitive layer is arranged on the first through hole and the interlayer dielectric layer; and
and arranging a shielding layer on the photosensitive layer.
9. The method for preparing an array substrate according to claim 8, wherein the step of disposing a shielding layer on the photosensitive layer further comprises:
and forming a doping layer on the photosensitive layer, wherein the shielding layer covers the doping layer and is a second grid insulation layer.
10. The method for manufacturing an array substrate according to claim 8, wherein after the step of disposing the photosensitive layer on the first via hole and the interlayer dielectric layer and before the step of disposing the shielding layer on the photosensitive layer, the method further comprises:
and arranging a doping layer on the photosensitive layer, wherein the shielding layer covers the doping layer and is an indium tin oxide layer.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078171A (en) * | 2021-03-26 | 2021-07-06 | 武汉华星光电技术有限公司 | Array substrate, array substrate manufacturing method and display panel |
| CN113327953A (en) * | 2021-05-11 | 2021-08-31 | 武汉华星光电技术有限公司 | Display panel |
| CN115016173A (en) * | 2022-06-07 | 2022-09-06 | 武汉华星光电技术有限公司 | Backlight module and display device |
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2020
- 2020-10-14 CN CN202011096584.9A patent/CN112259556A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078171A (en) * | 2021-03-26 | 2021-07-06 | 武汉华星光电技术有限公司 | Array substrate, array substrate manufacturing method and display panel |
| CN113327953A (en) * | 2021-05-11 | 2021-08-31 | 武汉华星光电技术有限公司 | Display panel |
| CN113327953B (en) * | 2021-05-11 | 2022-09-27 | 武汉华星光电技术有限公司 | Display panel |
| CN115016173A (en) * | 2022-06-07 | 2022-09-06 | 武汉华星光电技术有限公司 | Backlight module and display device |
| CN115016173B (en) * | 2022-06-07 | 2023-12-15 | 武汉华星光电技术有限公司 | Backlight module and display device |
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