CN1151405C - Thin-film transistor LCD and its manufacture - Google Patents
Thin-film transistor LCD and its manufacture Download PDFInfo
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- CN1151405C CN1151405C CNB001219251A CN00121925A CN1151405C CN 1151405 C CN1151405 C CN 1151405C CN B001219251 A CNB001219251 A CN B001219251A CN 00121925 A CN00121925 A CN 00121925A CN 1151405 C CN1151405 C CN 1151405C
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Abstract
The present invention relates to a film transistor liquid crystal display. The fabrication of a film transistor uses a metal electrode layer as a mask, and when a silicon doping layer is etched to form a source/drain electrode, semiconductor layers in areas beyond the film transistor can be cleanly removed. Thus, the fabrication technology defect that the semiconductor layers are probably residual can be reduced, and the fabrication rate of finished products of the film transistor can be enhanced.
Description
The present invention relates to a kind of Thin Film Transistor-LCD and manufacture method thereof, particularly relate to and utilize metal electrode layer as mask, when the etching doped silicon layer forms source/drain electrode, remove the Thin Film Transistor-LCD and the manufacture method thereof of the semiconductor layer of electrode both sides in the lump.
In the application of active array-type LCD (Active Matrix Liquid Crystal Display), thin film transistor (TFT) (thin-film transistor; Hereinafter referred is TFT) be considered to have the element of good driving and switching capability.One of basic framework of TFT element, as shown in Figure 1.Among the figure, label 1 is a substrate, for example is glass or quartz; Label 2a is a conductive layer, as the grid of TFT; Label 2b is the electrode of reservior capacitor; Label 3 is a gate insulator; 4 is the semiconductor layer of TFT, and (amorphous silicon layer) constituted by amorphous silicon; Label 5 is a doped silicon layer, for being mixed with the polysilicon of n+ type impurity, can be used as source/drain region of TFT; Label 6 is an electrode layer, is generally metal; Label 7 is protective seam (passivation layer); And label 8 is transparency conducting layer, is generally indium tin oxide layer (ITO layer), can be used as the bottom electrode that drives liquid crystal, and label 9 is a channel region.
TFT shown in Figure 1 generally is to limit earlier to form amorphous silicon layer 4 on above-mentioned gate insulator 3, carries out etching more afterwards and forms above-mentioned channel region 9.When etching method for amorphous silicon layer 4,, then can destroy the characteristic of TFT, and reduce its rate that manufactures a finished product if there is amorphous silicon layer 4 to residue on the outer gate insulator 3 of TFT element region.In addition, on electrode 2b, be formed with double-deck dielectric layer (that is gate insulator 3 and protective seam 7), will cause the capacitance Cs of reservior capacitor to reduce.
In view of this, a purpose of the present invention, for proposing novel method of manufacturing thin film transistor, utilize metal electrode layer as mask, when the etching doped silicon layer forms source/drain region, can in the lump thin film transistor (TFT) be removed totally fully with the semiconductor layer of exterior domain, avoid the residual manufacture craft defective that causes of semiconductor layer by this, improve the fabrication yield of thin film transistor (TFT).
Another object of the present invention is for proposing the manufacture method of novel Thin Film Transistor-LCD, the time of mat control etching source/drain region, and under the situation that does not influence the channel region characteristic, can be according to the needs of using, the thickness of gate insulator is suitably reduced, to increase the capacitance Cs of reservior capacitor.
Another purpose of the present invention is for proposing the manufacture method of novel Thin Film Transistor-LCD, when limiting electrode layer, also limit a metal shielding layer in the top of reservior capacitor electrode, afterwards after the etching of the source of finishing/drain region, promptly above above-mentioned reservior capacitor electrode, form a stack layer, to increase the unit area of reservior capacitor.
For achieving the above object, first kind of manufacture method of the thin film transistor (TFT) that the present invention proposes comprises the steps:
One substrate is provided;
Be shaped as a conductive layer in the aforesaid substrate upper limit, as the grid of above-mentioned thin film transistor (TFT);
Forming a gate insulator is covered on above-mentioned conductive layer and the aforesaid substrate;
On above-mentioned gate insulator, form a semi-conductor layer and a doped silicon layer successively;
On above-mentioned doped silicon layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned conductive layer directly over;
Form a metal level, be covered on above-mentioned island sacrifice layer and the above-mentioned doped silicon layer;
Limit the above-mentioned metal level of etching, form an one source pole electrode layer and a drain electrode layer, wherein, area limiting at above-mentioned source electrode layer and this drain electrode interlayer is a passage area, and the aforesaid substrate zone that is covered by above-mentioned source electrode layer, above-mentioned drain electrode layer and above-mentioned passage area is not restricted to a non-TFT regions, so be etched away this source plate electrode layer and this drain electrode layer above-mentioned metal level in addition, above-mentioned island sacrifice layer is exposed in the above-mentioned passage area, and above-mentioned doped silicon layer is exposed in this non-TFT regions;
With above-mentioned source electrode layer and drain electrode layer is mask, carry out the etching program of a scheduled time slot, in this scheduled time slot, finish following two etching process simultaneously: (a) in above-mentioned passage area, remove above-mentioned island sacrifice layer and doped silicon layer, to reveal above-mentioned semiconductor layer, (b) in above-mentioned non-TFT regions, remove above-mentioned doped silicon layer and semiconductor layer, to expose above-mentioned gate insulator; And form a protective seam and cover above-mentioned source electrode layer, drain electrode layer, passage area and non-TFT regions.
For reaching above-mentioned purpose, second kind of manufacture method of the thin film transistor (TFT) that the present invention proposes on the other hand comprises the steps:
One substrate is provided;
Limit and form a conductive layer on aforesaid substrate, as the grid of above-mentioned thin film transistor (TFT);
Forming a gate insulator on above-mentioned conductive layer and aforesaid substrate covers;
On above-mentioned gate insulator, form semi-conductor layer;
On above-mentioned semiconductor layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned conductive layer directly over;
Form a doped silicon layer, be covered on above-mentioned island sacrifice layer and the above-mentioned semiconductor layer;
On above-mentioned doped silicon layer, form a metal level;
Limit the above-mentioned metal level of etching, form an one source pole electrode layer and a drain electrode layer, wherein, area limiting at above-mentioned source electrode layer and this drain electrode interlayer is a passage area, and the aforesaid substrate zone that is covered by above-mentioned source electrode layer, above-mentioned drain electrode layer and above-mentioned passage area is not restricted to a non-TFT regions, so be etched away the metal level beyond this source electrode layer and this drain electrode layer, make above-mentioned doped silicon layer be exposed in the passage area with non-TFT regions in;
With above-mentioned source electrode layer and drain electrode layer is the etching program that mask carries out a scheduled time slot, in this scheduled time slot, finish following two etching process simultaneously: (a) in above-mentioned passage area, remove above-mentioned doped silicon layer and island sacrifice layer, to expose above-mentioned semiconductor layer, (b) in above-mentioned non-TFT regions, remove above-mentioned doped silicon layer and semiconductor layer, to expose above-mentioned gate insulator; And form a protective seam, cover above-mentioned source electrode layer, drain electrode layer, passage area and non-TFT regions.
In above-mentioned etching program, the rate of etch of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively R
IS, R
n, and R
aThe thickness of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively T
IS, T
n, and T
aRemove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) be not less than the above-mentioned doped silicon layer removed in the above-mentioned non-TFT regions and the time (T of semiconductor layer
n/ R
n+ T
a/ R
a).In addition, by controlling the mode of above-mentioned island sacrificial layer thickness, make above-mentioned doped silicon layer and the island sacrifice layer and when exposing above-mentioned semiconductor layer of above-mentioned etching program in removing above-mentioned passage area, except the above-mentioned doped silicon layer in the above-mentioned non-TFT regions and semiconductor layer are removed, also the above-mentioned gate insulator that is exposed in the above-mentioned non-TFT regions is carried out etching, remove a part of above-mentioned gate insulator, and reduce the thickness of above-mentioned gate insulator.
For achieving the above object, first kind of manufacture method of the Thin Film Transistor-LCD (TFT-LCD) that another aspect of the present invention proposes may further comprise the steps;
One substrate is provided;
Be shaped as first and second conductive layers in the aforesaid substrate upper limit, respectively as a grid of above-mentioned thin film transistor (TFT) and a bottom electrode of above-mentioned holding capacitor;
Form an insulation course, cover above-mentioned first, second conductive layer and aforesaid substrate;
On above-mentioned insulation course, form a semi-conductor layer and a doped silicon layer successively;
On above-mentioned doped silicon layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned first conductive layer directly over;
Form a metal level, cover the above-mentioned island sacrifice layer and the above-mentioned doped silicon layer of first conductive layer top;
Limit the above-mentioned metal level of etching, above above-mentioned first conductive layer, form an one source pole electrode layer and a drain electrode layer, wherein, between above-mentioned source electrode layer and this drain electrode layer, limit a passage area, above-mentioned island sacrifice layer is exposed in the above-mentioned passage area, and the part that is not covered by source electrode, drain electrode layer and passage area on the substrate is defined as a non-TFT regions, and above-mentioned doped silicon layer is exposed in this non-TFT regions;
With above-mentioned source electrode, drain electrode layer and shielding electrode layer is mask, carry out an etching program, above-mentioned island sacrifice layer in the above-mentioned passage area and doped silicon layer are removed, to expose the above-mentioned semiconductor layer in the above-mentioned passage area, also remove simultaneously above-mentioned doped silicon layer and semiconductor layer in the above-mentioned non-TFT regions, to expose above-mentioned insulation course;
Form a protective seam, cover on above-mentioned drain electrode, source electrode, passage area and the above-mentioned second electricity layer;
The above-mentioned protective seam of etching forms a perforation, exposing one of above-mentioned source electrode and drain electrode layer, and
Be shaped as a transparency conducting layer in the above-mentioned protective seam upper limit; and extend one of above-mentioned source electrode and drain electrode layer and this second conductive layer top; this transparency conducting layer forms by this perforation and one of above-mentioned source electrode and drain electrode layer and electrically contacts, and makes above-mentioned transparency conducting layer constitute a top electrode of above-mentioned holding capacitor.
For achieving the above object, second kind of manufacture method of the Thin Film Transistor-LCD (TFT-LCD) that further aspect of the present invention proposes, this LCD comprises a thin film transistor (TFT) and a holding capacitor at least, its method for making may further comprise the steps:
One substrate is provided;
Be shaped as first and second conductive layers in the aforesaid substrate upper limit, respectively as a grid of an above-mentioned thin film transistor (TFT) and a bottom electrode of a holding capacitor;
Form an insulation course, cover above-mentioned first, second conductive layer and aforesaid substrate;
On above-mentioned insulation course, form a semi-conductor layer and a doped silicon layer successively;
On above-mentioned doped silicon layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned first conductive layer directly over;
Form a metal level, cover above-mentioned island sacrifice layer and above-mentioned doped silicon layer;
Limit the above-mentioned metal level of etching, above above-mentioned first conductive layer, form an one source pole electrode layer and a drain electrode layer, and form a shielding electrode layer in the top of above-mentioned second conductive layer; Wherein, between above-mentioned source electrode layer and this drain electrode layer, limit a passage area, above-mentioned island sacrifice layer is exposed in the above-mentioned passage area, the area limiting that is covered by above-mentioned shielding electrode layer on the aforesaid substrate is a capacitor regions, the area limiting that is not covered by above-mentioned source electrode, drain electrode layer, above-mentioned capacitor regions and above-mentioned passage area on the aforesaid substrate is a non-TFT regions, and above-mentioned doped silicon layer is exposed in this non-TFT regions;
With above-mentioned source electrode, drain electrode layer and shielding electrode layer is mask, carry out an etching program, above-mentioned island sacrifice layer in the above-mentioned passage area and doped silicon layer are removed, to expose the above-mentioned semiconductor layer in the above-mentioned passage area, also remove simultaneously above-mentioned doped silicon layer and semiconductor layer in the above-mentioned non-TFT regions, to expose above-mentioned gate insulator;
Form a protective seam, cover on above-mentioned drain electrode, source electrode, passage area and the above-mentioned capacitor regions;
The above-mentioned protective seam of etching forms one first perforation to expose one of above-mentioned source electrode and drain electrode layer, reaches and forms one second perforation to expose the above-mentioned shielding electrode layer of above-mentioned capacitor regions; And
Be shaped as a transparency conducting layer in the above-mentioned protective seam upper limit; and extend one of above-mentioned source electrode and drain electrode layer and this shielding electrode layer top; this transparency conducting layer forms with one of above-mentioned source electrode and drain electrode layer by this first perforation and electrically contacts; this transparency conducting layer forms with above-mentioned shielding electrode layer by this second perforation and electrically contacts, and makes above-mentioned transparency conducting layer constitute a top electrode of above-mentioned holding capacitor.
In the manufacture method of above Thin Film Transistor-LCD (TFT-LCD), above-mentioned etching program is respectively R to the rate of etch of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer
IS, R
n, and R
aThe thickness of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively T
IS, T
n, and T
aRemove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) be not less than the above-mentioned doped silicon layer removed in the above-mentioned non-TFT regions and the time (T of semiconductor layer
n/ R
n+ T
a/ R
a).In addition, by controlling the mode of above-mentioned island sacrificial layer thickness, make above-mentioned etching program above-mentioned island sacrifice layer and doped silicon layer and when exposing above-mentioned semiconductor layer in removing above-mentioned passage area, except the above-mentioned doped silicon layer in the above-mentioned non-TFT regions and semiconductor layer are removed, also the above-mentioned insulation course that is exposed in the above-mentioned non-TFT regions is carried out etching, remove a part of above-mentioned insulation course, and reduce the thickness of above-mentioned insulation course.
The first kind of thin film transistor (TFT) that gets according to the said method making, comprising: an island grid layer is arranged on the substrate; One gate insulator covers above-mentioned island grid layer; One island semiconductor layer is arranged on the above-mentioned gate insulator, and is positioned at the top of above-mentioned island grid layer; An one source pole doped silicon layer and a drain electrode doped silicon layer are arranged at one of above-mentioned island semiconductor layer, and above-mentioned source dopant silicon layer and drain electrode doped silicon layer area limiting separately are a passage area, expose above-mentioned island semiconductor layer in above-mentioned passage area; The one first island sacrifice layer and the second island sacrifice layer, be arranged at respectively on above-mentioned source dopant silicon layer and the drain electrode doped silicon layer, and be close to the above-mentioned island semiconductor layer that is exposed between above-mentioned source layer and drain electrode layer, and with this passage area above-mentioned first island sacrifice layer in interval and the second island sacrifice layer; The one source pole electrode is arranged on above-mentioned source dopant silicon layer and the above-mentioned first island sacrifice layer; And a drain electrode is arranged on above-mentioned drain electrode doped silicon layer and the above-mentioned second island sacrifice layer.Wherein, the thickness of above-mentioned first, second island sacrifice layer depends on the thickness of above-mentioned island semiconductor layer, makes this first island sacrifice layer of etching, this second island sacrifice layer, during with this island semiconductor layer, needs roughly the same etching period.
The second kind of thin film transistor (TFT) that gets according to the said method making, comprising: an island grid layer is arranged on the substrate; One gate insulator covers above-mentioned island grid layer; One island semiconductor layer is arranged on the above-mentioned gate insulator, and is positioned at the top of above-mentioned island grid layer; One first island sacrifice layer and one second island sacrifice layer are arranged on the above-mentioned island semiconductor layer, and above-mentioned first island sacrifice layer and second island sacrifice layer area limiting separately are a passage area, expose above-mentioned island semiconductor layer with above-mentioned passage area; An one source pole doped silicon layer and a drain electrode doped silicon layer are arranged on above-mentioned island semiconductor layer, the above-mentioned first and second island sacrifice layers, and with this passage area above-mentioned source dopant silicon layer in interval and drain electrode doped silicon layer; And, an one source pole conductive layer and a drain electrode conductive layer, be arranged at respectively on above-mentioned source layer and the drain electrode layer, wherein, the thickness of above-mentioned first and second island sacrifice layer, the thickness that depends on above-mentioned island semiconductor layer makes this first island sacrifice layer of etching, this second island sacrifice layer, during with this island semiconductor layer, needs roughly the same etching period.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described below in detail; Wherein, the material of identical or similar aspect is all with identical numeral or symbolic representation.In the accompanying drawing:
Fig. 1 shows the basic boom of TFT element;
Fig. 2 A to Fig. 2 F shows the flow process sectional view of first embodiment of the invention;
Fig. 3 A to Fig. 3 F shows the flow process sectional view of second embodiment of the invention;
Fig. 4 A to Fig. 4 F shows the flow process sectional view of third embodiment of the invention;
Fig. 5 A to Fig. 5 F shows the flow process sectional view of fourth embodiment of the invention.
Symbol description:
1,21,41～substrate; 2a～gate metal layer; The electrode of 2b～holding capacitor; 3,23,43～gate insulator; 4,24,44～semiconductor layer; 5,25,45～doped silicon layer; 6,26,46～electrode layer; 7,27,47～protective seam; 8,28,48～transparency conducting layer; 9,30,32,52,53～channel region; 22a, 42a～first conductive layer; 22b, 42b～second conductive layer; 26a, 46a～source electrode; 26b, 46b～drain electrode; 29,49～island sacrifice layer; R
IS, R
n, R
a, R
INS～rate of etch; T
IS, T
n, T
a, T
INS～thickness; SL～stack layer; 1,51～metal shielding layer.
Embodiment one
Fig. 2 A to Fig. 2 F shows that the present invention makes the flow process sectional view of first embodiment of a Thin Film Transistor-LCD.
At first, qualification forms the first conductive layer 22a, reaches the second conductive layer 22b on a substrate 21; Wherein, the first conductive layer 22a is as the grid of thin film transistor (TFT) (TFT); The second conductive layer 22b is as the bottom electrode of reservior capacitor; In this embodiment, first and second conductive layer (22a, 22b) is metal level; The material of substrate is glass or quartz.
Then, on doped silicon layer 25, limit to form island sacrifice layer 29, and island sacrifice layer 29 be positioned at the first conductive layer 22a directly over; Shown in Fig. 2 B.
Next, form a metal level, be covered on island sacrifice layer 29 and the doped silicon layer 25, limit etch metal layers again, comprise in order to formation and the electrode layer 26 of source electrode, drain electrode 26a, 26b wherein, between source electrode, drain electrode 26a, 26b, to expose island sacrifice layer 29.Between source electrode, drain electrode 26a, 26b, limit a passage area 30, and be not a non-TFT regions with the area limiting that above-mentioned passage area covers on the substrate 21 by above-mentioned electrode layer 26, exposing in non-TFT regions has doped silicon layer 25, shown in Fig. 2 C.
With electrode layer 26 is mask, carries out the etching program of a scheduled time slot, in this scheduled time slot, carries out two-part etch process simultaneously.That is to say, in this etching program, not only island sacrifice layer 29 between source electrode, drain electrode 26a, 26b and doped silicon layer 25 are removed, to expose the semiconductor layer 24 between source electrode, drain electrode 26a, 26b, simultaneously, also doped silicon layer on the non-TFT regions 25 and semiconductor layer 24 are removed, to expose gate insulator 23, the result is shown in Fig. 2 D.
In the above-mentioned etching program, the rate of etch of island sacrifice layer 29, doped silicon layer 25 and semiconductor layer 24 is respectively R
IS, R
n, and R
aAnd the thickness of island sacrifice layer 29, doped silicon layer 25 and semiconductor layer 24 is respectively T
IS, T
nAnd T
a
According to the needs of using, can adjust, set the thickness T of island sacrifice layer 29, doped silicon layer 25 and semiconductor layer 24 in advance
IS, T
n, and T
a, cooperate suitable etching mode, and make the sacrifice layer 29 removed between source electrode, drain electrode 26a, 26b and the time T 1 (T1=(T of doped silicon layer 25
IS/ R
IS+ T
n/ R
n)) be not less than the doped silicon layer 25 of removing above-mentioned electrode layer 26 both sides and the time T 2 (T2=(T of semiconductor layer 24
n/ R
n+ T
a/ R
a)).When etch-stop, semiconductor layer 24 is exposed in the passage area between source electrode, drain electrode 26a, 26b, and gate insulator 23 also is exposed to the both sides of electrode layer 26.
In addition, mode by control island sacrifice layer 29 thickness, make above-mentioned etching program in removing passage area in island sacrifice layer 29 and the doped silicon layer 25, except the doped silicon layer in the non-TFT regions 25 and semiconductor layer 24 are removed, also the gate insulator 23 that is exposed to non-TFT regions is carried out etching, reduce the thickness of gate insulator 23 in order to the gate insulator 23 of removing a part.That is to say, when the rate of etch of gate insulator is R
INS, and the thickness of removed part of grid pole insulation course is T
INS, then remove the island sacrifice layer of source electrode, drain electrode interlayer and the time T of doped silicon layer
I(T
I=(T
IS/ R
IS+ T
n/ R
n)) will equal to remove the time T of doped silicon layer, semiconductor layer and part of grid pole insulation course in the non-TFT regions
3(T
3=(T
n/ R
n+ T
a/ R
a+ T
INS/ R
INS).
Then, form a protective seam (passivation layer) 27, cover above-mentioned source electrode 26a, drain electrode 26b, with passage area 30, can finish a kind of thin film transistor (TFT) that is used for a plane rotation (In plane switch) LCD.
Afterwards, etch protection layer 27 is to expose electrode 26b, shown in Fig. 2 F.At last, limit and form a transparency conducting layer 28 on above-mentioned protective seam 27, and electrically contact with electrode 26b formation.This transparency conducting layer can be one deck indium tin oxide layer (ITO layer) 28.
Embodiment two
Fig. 3 A to Fig. 3 F shows the flow process sectional view of second embodiment of the invention; Wherein, identical with Fig. 2 A to Fig. 2 F unit will be represented with same-sign.
Key step, the condition of second embodiment and first embodiment are all identical, main difference is, when limiting the above-mentioned metal level of etching, except that formation comprises the above-mentioned electrode layer 26 of electrode 26a, 26b, also directly over above-mentioned reservior capacitor electrode 22b, metal shielding layer 31 is arranged; Shown in Fig. 3 C.By this, after finishing above-mentioned etching program, above-mentioned metal shielding layer 31 constitutes a stack layer SL on above-mentioned gate insulator 23 and electrode 22b with above-mentioned doped silicon layer 25, channel layer 24; Shown in Fig. 3 D.
Form protective seam 27, above-mentioned TFT is covered, the above-mentioned protective seam 27 of etching exposes electrode 26b and stack layer SL again; Shown in Fig. 3 E.
At last; be shaped as indium tin oxide layer (ITO layer) 28 in above-mentioned protective seam 27 upper limits; and form and electrically contact with metal shielding layer 31 among above-mentioned electrode 26b and the above-mentioned stack layer SL; and during jointly as the top electrode metal level of holding capacitor; except that formation comprises the electrode layer 26 of source electrode, drain electrode 26a, 26b; also directly over storage capacitor electrode 22b, form a metal shielding layer 31, shown in Fig. 3 C.By this, after finishing above-mentioned etching program, metal shielding layer 31, doped silicon layer 25, on gate insulator 23 and electrode 22b, constitute a stack layer SL with semiconductor layer 24, shown in Fig. 3 D.
In this embodiment, be defined as a channel region 32 between source electrode, drain electrode 26a, the 26b, the substrate portion that covers by source electrode, drain electrode 26a, 26b, passage area 32, with holding capacitor is not defined as a non-thin film transistor region.At this moment, the island sacrifice layer 29 between removal source electrode, drain electrode 26a, 26b and the time T of doped silicon layer 25
I(T
I=(T
IS/ R
IS+ T
n/ R
n)) equal to remove the time T of the doped silicon layer 25 and the semiconductor layer 24 of non-thin film transistor region
2(T
2=(T
n/ R
n+ T
a/ R
a)).When etch-stop, semiconductor layer 24 is exposed in the channel region 32 between source electrode, drain electrode (26a, 26b), and gate insulator 23 also is exposed on the non-thin film transistor region, shown in Fig. 3 D.
Then form protective seam (passivation layer) 27; cover source electrode 26a, drain electrode 26b, channel region 30; on stack layer SL, so can finish a kind of thin film transistor (TFT) that is used for a plane rotation (Inplane switch) LCD.Etch protection layer 27 again, expose drain electrode 26b and stack layer SL; Shown in Fig. 3 F.At last, be shaped as a transparency conducting layer,, and form with the metal shielding layer 31 of electric capacity and to electrically contact as indium tin oxide layer (ITO layer) 28 in protective seam 27 upper limits, and jointly as the top electrode of reservior capacitor, shown in Fig. 3 F.
Because the formation of stack layer SL makes the per surface area of reservior capacitor increase, so can increase its capacitance Cs.
Embodiment three
Fig. 4 A to Fig. 4 F shows the flow process sectional view of third embodiment of the invention.Among first embodiment, the island sacrifice layer is formed on semiconductor layer and the doped silicon layer.Step, the condition of the 3rd embodiment and first embodiment are roughly the same, main difference be the island sacrifice layer be formed on the semiconductor layer, under the doped silicon layer.
At first, limit the formation first conductive layer 42a and the second conductive layer 42b on a substrate 41, wherein, the first conductive layer 42a is as the grid of thin film transistor (TFT) (TFT), and the second conductive layer 42b is as the electrode of holding capacitor.In this embodiment, first and second conductive layer (42a, 42b) is metal level, and the material of substrate 14 is glass or quartz.
Then, on semiconductor layer 44, limit to form island sacrifice layer 49, and island sacrifice layer 49 be positioned at the first conductive layer 22a directly over, shown in Fig. 4 B.Form doped silicon layer 45, be covered on above-mentioned island sacrifice layer 49 and the above-mentioned semiconductor layer 44.
Form metal level, be covered on the above-mentioned doped silicon layer 45, limit etch metal layers again, form the electrode layer 46 that comprises source electrode, drain electrode 46a, 46b.Between source electrode, drain electrode 46a, 46b, limit a passage area 52, and doped silicon layer 45 is exposed in the channel region 52.Be not defined as a non-TFT regions by electrode layer 46 and the part that channel region 52 covers on the substrate 41, doped silicon layer 45 also is exposed in the non-TFT regions, shown in Fig. 4 C.
With electrode layer 46 is mask, carry out the etching program of a scheduled time slot, with the doped silicon layer 45 between source electrode, drain electrode 46a, 46b and sacrifice layer 49 and removal, to expose the semiconductor layer 44 between source electrode, drain electrode 46a, 46b, also the doped silicon layer 45 and the semiconductor layer 44 of non-TFT regions are removed simultaneously, to expose gate insulator 43, the result is shown in Fig. 4 D.Certainly, also can be by the thickness of control island sacrifice layer 49, make and also the gate insulator 43 that is exposed in the non-TFT regions is carried out etching in the above-mentioned etching program, remove the gate insulator 43 of a part, and reduce the thickness of gate insulator 43.
The rate of etch of island sacrifice layer 49, doped silicon layer 45, semiconductor layer 44 is respectively R in the above-mentioned etching program
IS, R
n, R
a, and the thickness of island sacrifice layer 49, doped silicon layer 45 and semiconductor layer 44 is respectively T
IS, T
n, and T
a
In the above-mentioned etching program,, can adjust in advance, set the thickness T of above-mentioned island sacrifice layer 49, doped silicon layer 45 and semiconductor layer 44 according to the needs of using
IS, T
n, and T
a, and remove the time T of doped silicon layer 45 and island sacrifice layer 49 in the channel region 52
I(T
I=(T
IS/ R
IS+ T
n/ R
n)) be not less than the doped silicon layer 45 of removing non-thin film transistor region and the time T of semiconductor layer 44
2(T
2=(T
n/ R
n+ T
a/ R
a)), use allowing the reaction end of etching program be the semiconductor layer 44 of channel region and the gate insulator 43 of non-thin film transistor region.
Further say, when the rate of etch of gate insulator is R
INS, and the thickness of removed part of grid pole insulation course is T
INS, then remove the island sacrifice layer of source electrode, drain electrode interlayer and the time T of doped silicon layer
I(T
I=(T
IS/ R
IS+ T
n/ R
n)) will equal to remove the time T of doped silicon layer, semiconductor layer and part of grid pole insulation course in the non-TFT regions
3(T
3=(T
n/ R
n+ T
a/ R
a+ T
INS/ R
INS).
Then, form protective seam (passivation layer) 47, etch protection layer 47 again, to expose drain electrode 46b, shown in Fig. 4 E.At last, be shaped as indium tin oxide layer (ITOlayer) 48, and electrically contact with drain electrode 46b formation in protective seam 47 upper limits.
Embodiment four
Fig. 5 A to Fig. 5 F shows the flow process sectional view of fourth embodiment of the invention; Wherein, the unit that Fig. 4 A to Fig. 4 F is identical will be represented with same-sign.
Key step, the condition of the 4th embodiment and the 3rd embodiment are all identical, main difference is, when limiting the above-mentioned metal level of etching, except that formation comprises the above-mentioned electrode layer 46 of source electrode, drain electrode 46a, 46b, also directly over above-mentioned reservior capacitor electrode 42b, be formed with metal shielding layer 51; Shown in Fig. 5 C.By this, after finishing above-mentioned etching program, above-mentioned metal shielding layer 51 and above-mentioned doped silicon layer 45, the semiconductor layer 44 stack layer SLs of formation one on above-mentioned gate insulator 43 and electrode 42b; Shown in Fig. 5 D.
In this embodiment, be defined as a channel region 53 between source electrode, drain electrode 46a, the 46b, the substrate portion that covers by source electrode, drain electrode (46a, 46b), passage area 53, with reservior capacitor is not defined as a non-thin film transistor region.At this moment, the sacrifice layer 49 between removal source electrode, drain electrode (46a, 46b) and the time T of doped silicon layer 45
I(T
I=(T
IS/ R
IS+ T
n/ R
n)) equal to remove the time T of the doped silicon layer 45 and the semiconductor layer 44 of non-thin film transistor region
2(T
2=(T
n/ R
n+ T
a/ R
a)).When etch-stop, semiconductor layer 44 is exposed in the channel region 53 between source electrode, drain electrode (46a, 46b), and gate insulator 43 also is exposed on the non-thin film transistor region, shown in Fig. 5 D.
Then, form protective seam 47 cover source electrode 26a, drain electrode 26b, channel region 30, with stack layer SL on, so can finish a kind of thin film transistor (TFT) that is used for a plane rotation (In plane switch) LCD.The above-mentioned protective seam 47 of etching exposes electrode 46b and stack layer SL again; Shown in Fig. 5 E.
At last, be shaped as a transparency conducting layer,, and form and electrically contact with metal shielding layer 51 among drain electrode 46b and the stack layer SL as indium tin oxide layer (ITOlayer) 48 in protective seam 47 upper limits, and jointly as the top electrode of reservior capacitor, shown in Fig. 5 F.
Because the formation of stack layer SL makes the per surface area of holding capacitor increase, so can increase its capacitance Cs.
By the foregoing description as can be known, the present invention utilizes metal electrode layer as mask, when the etching doped silicon layer forms source/drain region, can in the lump thin film transistor (TFT) be removed totally fully with the semiconductor layer of exterior domain, reduce the manufacture craft defective that semiconductor layer may be residual by this, improve the fabrication yield of thin film transistor (TFT).In addition, can be by gate insulator being carried out etching or forming stack layer, to increase the capacitance of reservior capacitor.
In addition, with reference to Fig. 2 F, Fig. 3 F, the first kind of thin film transistor (TFT) that gets according to the said method making, its structure comprises: an island grid layer 22a is arranged on the substrate 21; One gate insulator 23 covers island grid layer 22a; One island semiconductor layer 24 is arranged on the gate insulator 23, and is positioned at the top of island grid layer 22a; An one source pole doped silicon layer 25 and a drain electrode doped silicon layer 25 are arranged on the island semiconductor layer 24, and above-mentioned source dopant silicon layer and drain electrode doped silicon layer area limiting separately are a passage area, expose the island semiconductor layer in passage area; The one first island sacrifice layer 29 and the second island sacrifice layer 29 are arranged at respectively on above-mentioned source dopant silicon layer 25 and the drain electrode doped silicon layer 25, and with this passage area above-mentioned first island sacrifice layer in interval and the second island sacrifice layer; One source pole electrode 26a is arranged on above-mentioned source dopant silicon layer 25 and the above-mentioned first island sacrifice layer 29; And a drain electrode 26b is arranged on the drain electrode doped silicon layer 25 and the second island sacrifice layer 29.
Wherein, the thickness of first and second island sacrifice layer 29 depends on the thickness of island semiconductor layer 25, makes this first island sacrifice layer of etching, this second island sacrifice layer, during with this island semiconductor layer, needs identical etching period.
On the other hand, please refer to Fig. 4 F, Fig. 5 F, the second kind of thin film transistor (TFT) that gets according to the said method making, comprising: an island grid layer 42a is arranged on the substrate 41; One gate insulator 43 covers island grid 42a layer; One island semiconductor layer 44 is arranged on the gate insulator 43, and is positioned on the above-mentioned island grid layer 42a; One first island sacrifice layer and one second island sacrifice layer 49 are arranged on the above-mentioned island semiconductor layer 44, and the first island sacrifice layer and second island sacrifice layer area limiting separately are a passage area, expose the island semiconductor layer in passage area; An one source pole doped silicon layer and a drain electrode doped silicon layer 45 are arranged on island semiconductor layer 44, the first and second island sacrifice layers 49, and with this passage area above-mentioned source dopant silicon layer in interval and drain electrode doped silicon layer; And an one source pole electrode 46a and a drain electrode 46b, be arranged at respectively on above-mentioned source dopant silicon layer 45 and the drain electrode doped silicon layer 45.
Wherein, the thickness of first and second island sacrifice layer 49 depends on the thickness of island semiconductor layer 44, makes the etching first island sacrifice layer, the second island sacrifice layer, during with the island semiconductor layer, needs the roughly the same etching period.
Though the present invention discloses as above with four preferred embodiments; but it is not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; can make some changes and retouching, so protection scope of the present invention should be defined by accompanying Claim.
Claims (32)
1. method of manufacturing thin film transistor comprises:
One substrate is provided;
Be shaped as a conductive layer in the aforesaid substrate upper limit, as the grid of above-mentioned thin film transistor (TFT);
Form a gate insulator, be covered on above-mentioned conductive layer and the aforesaid substrate;
On above-mentioned gate insulator, form a semi-conductor layer and a doped silicon layer successively;
On above-mentioned doped silicon layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned conductive layer directly over;
Form a metal level, be covered on above-mentioned island sacrifice layer and the above-mentioned doped silicon layer;
Limit the above-mentioned metal level of etching, form an one source pole electrode layer and a drain electrode layer; Wherein, be a passage area at the area limiting of above-mentioned source electrode layer and this drain electrode interlayer, and the aforesaid substrate zone that is not covered by above-mentioned source electrode layer, above-mentioned drain electrode layer and above-mentioned passage area is restricted to a non-TFT regions; So be etched away this source electrode layer and this drain electrode layer above-mentioned metal level in addition, above-mentioned island sacrifice layer is exposed in the above-mentioned passage area, above-mentioned doped silicon layer is exposed in this non-TFT regions;
With above-mentioned source electrode layer and drain electrode layer is mask, carry out the etching program of a scheduled time slot, in this scheduled time slot, finish following two etching process simultaneously: (a) in above-mentioned passage area, remove above-mentioned island sacrifice layer and doped silicon layer, to expose above-mentioned semiconductor layer, (b) in above-mentioned non-TFT regions, remove above-mentioned doped silicon layer and semiconductor layer, to expose above-mentioned gate insulator; And
Form a protective seam, cover above-mentioned source electrode layer, drain electrode layer, passage area and non-TFT regions.
2. the method for claim 1, wherein above-mentioned etching program is respectively R to the rate of etch of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer
IS, R
n, and R
aThe thickness of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively T
IS, T
n, and T
aRemove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) be not less than the above-mentioned doped silicon layer removed in the above-mentioned non-TFT regions and the time (T of semiconductor layer
n/ R
n+ T
a/ R
a).
3. method as claimed in claim 2, wherein, by controlling the mode of above-mentioned island sacrificial layer thickness, make above-mentioned etching program above-mentioned island sacrifice layer and doped silicon layer and when exposing above-mentioned semiconductor layer in removing above-mentioned passage area, except the above-mentioned doped silicon layer in the above-mentioned non-TFT regions and semiconductor layer are removed, also the above-mentioned gate insulator that is exposed in the above-mentioned non-TFT regions is carried out etching, remove a part of above-mentioned gate insulator, and reduce the thickness of above-mentioned gate insulator.
4. method as claimed in claim 3 wherein, is R to the rate of etch of above-mentioned part of grid pole insulation course
INS, and the thickness of above-mentioned part of grid pole insulation course is T
INS, wherein, remove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) will equal to remove the time (T of above-mentioned doped silicon layer, semiconductor layer and part of grid pole insulation course in the above-mentioned non-TFT regions
n/ R
n+ T
a/ R
a+ T
INS/ T
INS).
5. the method for claim 1, finish above-mentioned etching program after, also comprise the steps:
The above-mentioned protective seam of etching exposes one of above-mentioned source electrode and drain electrode layer; And
Limit and form a transparency conducting layer on above-mentioned protective seam, and electrically contact with the formation of one of above-mentioned source electrode and drain electrode layer.
6. method as claimed in claim 5, wherein, above-mentioned semiconductor layer is an amorphous silicon layer; Above-mentioned doped silicon layer is the polysilicon layer that is mixed with n type impurity; Above-mentioned conductive layer is a metal level; The material of aforesaid substrate is glass or quartz; This transparency conducting layer is an indium tin oxide layer.
7. method of manufacturing thin film transistor comprises:
One substrate is provided;
Be shaped as a conductive layer in the aforesaid substrate upper limit, as the grid of above-mentioned thin film transistor (TFT);
Form a gate insulator, be covered on above-mentioned conductive layer and the aforesaid substrate;
On above-mentioned gate insulator, form semi-conductor layer;
On above-mentioned semiconductor layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned conductive layer directly over;
Form a doped silicon layer, be covered on above-mentioned island sacrifice layer and the above-mentioned semiconductor layer;
On above-mentioned doped silicon layer, form a metal level;
Limit the above-mentioned metal level of etching, form an one source pole electrode layer and a drain electrode layer; Wherein, be a passage area at the area limiting of above-mentioned source electrode layer and this drain electrode interlayer, and the aforesaid substrate zone that is not covered by above-mentioned source electrode layer, above-mentioned drain electrode layer and above-mentioned passage area is restricted to a non-TFT regions; So be etched away this source electrode layer and this drain electrode layer above-mentioned metal level in addition, above-mentioned doped silicon layer is exposed in the above-mentioned passage area, above-mentioned doped silicon layer is exposed in the above-mentioned and non-TFT regions;
With above-mentioned source electrode layer and drain electrode layer is the etching program that mask carries out a scheduled time slot, in this scheduled time slot, finish following two etch process simultaneously: (a) in above-mentioned passage area, remove above-mentioned doped silicon layer and island sacrifice layer, to expose above-mentioned semiconductor layer, (b) in above-mentioned non-TFT regions, remove above-mentioned doped silicon layer and semiconductor layer, to expose above-mentioned gate insulator; And
Form a protective seam, cover above-mentioned source electrode layer, drain electrode layer, passage area and non-TFT regions.
8. method as claimed in claim 7, wherein, above-mentioned etching program is respectively R to the rate of etch of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer
IS, R
n, and R
aThe thickness of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively T
IS, T
n, and T
aRemove the time (T of above-mentioned two interelectrode above-mentioned sacrifice layers and doped silicon layer
IS/ R
IS+ T
n/ R
n) be not less than the above-mentioned doped silicon layer of removing above-mentioned electrode layer both sides and the time (T of semiconductor layer
n/ R
n+ T
a/ R
a).
9. method as claimed in claim 8, wherein, by controlling the mode of above-mentioned island sacrificial layer thickness, make above-mentioned etching program above-mentioned doped silicon layer and island sacrifice layer and when exposing above-mentioned semiconductor layer in removing above-mentioned passage area, except the above-mentioned doped silicon layer in the above-mentioned non-TFT regions and semiconductor layer are removed, also the above-mentioned gate insulator that is exposed in the above-mentioned non-TFT regions is carried out etching, remove a part of above-mentioned gate insulator, and reduce the thickness of above-mentioned gate insulator.
10. method as claimed in claim 9 wherein, is R to the rate of etch of above-mentioned part of grid pole insulation course
INS, and the thickness of above-mentioned part of grid pole insulation course is T
INS, wherein, remove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) will equal to remove the time (T of above-mentioned doped silicon layer, semiconductor layer and part of grid pole insulation course in the above-mentioned non-TFT regions
n/ R
n+ T
a/ R
a+ T
INS/ R
INS).
11. method as claimed in claim 7, finish above-mentioned etching program after, also comprise the steps:
The above-mentioned protective seam of etching exposes one of above-mentioned two electrodes; And
Be shaped as a transparency conducting layer in the above-mentioned protective seam upper limit, and electrically contact with the formation of one of above-mentioned electrode.
12. method as claimed in claim 11, wherein, above-mentioned semiconductor layer is an amorphous silicon layer; Above-mentioned doped silicon layer is the polysilicon layer that is mixed with n type impurity; Above-mentioned conductive layer is a metal level; The material of aforesaid substrate is glass or quartz; Above-mentioned transparency conducting layer is an indium tin oxide layer.
13. the manufacture method of a Thin Film Transistor-LCD, this LCD comprise a thin film transistor (TFT) and a holding capacitor at least, its method for making may further comprise the steps at least;
One substrate is provided;
Be shaped as first and second conductive layers in the aforesaid substrate upper limit, respectively as a grid of above-mentioned thin film transistor (TFT) and a bottom electrode of above-mentioned holding capacitor;
Form an insulation course, cover above-mentioned first, second conductive layer and aforesaid substrate;
On above-mentioned insulation course, form a semi-conductor layer and a doped silicon layer successively;
On above-mentioned doped silicon layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned first conductive layer directly over;
Form a metal level, cover the above-mentioned island sacrifice layer and the above-mentioned doped silicon layer of first conductive layer top;
Above above-mentioned first conductive layer, limit the above-mentioned metal level of etching, form an one source pole electrode layer and a drain electrode layer, wherein, between above-mentioned source electrode layer and this drain electrode layer, limit a passage area, above-mentioned island sacrifice layer is exposed in the above-mentioned passage area, the part that is not covered by above-mentioned source electrode, drain electrode layer and above-mentioned passage area on the aforesaid substrate is defined as a non-TFT regions, and above-mentioned doped silicon layer is exposed in this non-TFT regions;
With above-mentioned source electrode, drain electrode layer and shielding electrode layer is mask, carry out an etching program, above-mentioned island sacrifice layer in the above-mentioned passage area and doped silicon layer are removed, to expose the above-mentioned semiconductor layer in the above-mentioned passage area, also remove simultaneously above-mentioned doped silicon layer and semiconductor layer in the above-mentioned non-TFT regions, to expose above-mentioned insulation course;
Form a protective seam, cover on above-mentioned drain electrode, source electrode, passage area and above-mentioned second conductive layer;
The above-mentioned protective seam of etching forms a perforation to expose one of above-mentioned source electrode and drain electrode layer; And
Be shaped as a transparency conducting layer in the above-mentioned protective seam upper limit; and extend one of above-mentioned source electrode and drain electrode layer and this second conductive layer top; this transparency conducting layer forms by this perforation and one of above-mentioned source electrode and drain electrode layer and electrically contacts, and makes above-mentioned transparency conducting layer constitute a top electrode of above-mentioned holding capacitor.
14. method as claimed in claim 13, wherein, above-mentioned etching program is respectively R to the rate of etch of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer
IS, R
n, and R
aThe thickness of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively T
IS, T
n, and T
aRemove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) be not less than the above-mentioned doped silicon layer removed in the above-mentioned non-TFT regions and the time (T of semiconductor layer
n/ R
n+ T
a/ R
a).
15. method as claimed in claim 14, wherein, by controlling the mode of above-mentioned island sacrificial layer thickness, make above-mentioned etching program above-mentioned island sacrifice layer and doped silicon layer and when exposing above-mentioned semiconductor layer in removing above-mentioned passage area, except the above-mentioned doped silicon layer in the above-mentioned non-TFT regions and semiconductor layer are removed, also the above-mentioned insulation course that is exposed in the above-mentioned non-TFT regions is carried out etching, remove a part of above-mentioned insulation course, and reduce the thickness of above-mentioned insulation course.
16. method as claimed in claim 15 wherein, is R to the rate of etch of above-mentioned part of grid pole insulation course
INS, and the thickness of above-mentioned partial insulative layer is T
INS, wherein, remove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) will equal to remove the time (T of above-mentioned doped silicon layer, semiconductor layer and partial insulative layer in the above-mentioned non-TFT regions
n/ R
n+ T
a/ R
a+ T
INS/ R
INS).
17. the manufacture method of a Thin Film Transistor-LCD, this LCD comprise a thin film transistor (TFT) and a holding capacitor at least, its method for making may further comprise the steps at least:
One substrate is provided;
Be shaped as first and second conductive layers in the aforesaid substrate upper limit, respectively as a grid of a thin film transistor (TFT) and a bottom electrode of a holding capacitor;
Form an insulation course, cover above-mentioned first, second conductive layer and aforesaid substrate;
On above-mentioned insulation course, form a semi-conductor layer and a doped silicon layer successively;
On above-mentioned doped silicon layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned first conductive layer directly over;
Form a metal level, be covered in above-mentioned island sacrifice layer and above-mentioned doped silicon layer;
Limit the above-mentioned metal level of etching, form an one source pole electrode layer and a drain electrode layer in the top of above-mentioned first conductive layer, and form a shielding electrode layer in the top of above-mentioned second conductive layer; Wherein, between above-mentioned source electrode layer and this drain electrode layer, limit a passage area, above-mentioned island sacrifice layer is exposed in the above-mentioned passage area, the area limiting that is covered by above-mentioned shielding electrode layer on the aforesaid substrate is a capacitor regions, the area limiting that is not covered by above-mentioned source electrode, drain electrode layer, above-mentioned capacitor regions and above-mentioned passage area on the aforesaid substrate is a non-TFT regions, and above-mentioned doped silicon layer is exposed in this non-membrane transistor zone;
With above-mentioned source electrode, drain electrode layer and shielding electrode layer is mask, carry out an etching program, above-mentioned island sacrifice layer in the above-mentioned passage area and doped layer are removed, to expose the above-mentioned semiconductor layer in the above-mentioned passage area, also remove simultaneously above-mentioned doped silicon layer and semiconductor layer in the above-mentioned non-TFT regions, to expose above-mentioned gate insulator;
Form a protective seam, cover on above-mentioned drain electrode, source electrode, passage area and the above-mentioned capacitor regions;
The above-mentioned protective seam of etching forms one first perforation, to expose one of above-mentioned source electrode and drain electrode layer, reaches and forms one second perforation, to expose the above-mentioned shielding electrode layer of above-mentioned capacitor regions; And
Be shaped as a transparency conducting layer in the above-mentioned protective seam upper limit; and extend one of above-mentioned source electrode and drain electrode layer and this shielding electrode layer top; this transparency conducting layer forms with one of above-mentioned source electrode and drain electrode layer by this first perforation and electrically contacts; this transparency conducting layer forms with above-mentioned shielding electrode layer by this second perforation and electrically contacts, and makes above-mentioned transparency conducting layer constitute a top electrode of above-mentioned holding capacitor.
18. method as claimed in claim 17, wherein, above-mentioned etching program is respectively R to the rate of etch of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer
IS, R
n, and R
aThe thickness of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively T
IS, T
n, and T
aRemove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) be not less than the above-mentioned doped silicon layer removed in the above-mentioned non-TFT regions and the time (T of semiconductor layer
n/ R
n+ T
a/ R
a).
19. the manufacture method of a Thin Film Transistor-LCD, this LCD comprise a thin film transistor (TFT) and a holding capacitor at least, its method for making may further comprise the steps:
One substrate is provided;
Be shaped as first and second conductive layers in the aforesaid substrate upper limit, respectively as a grid of a thin film transistor (TFT), an and bottom electrode of above-mentioned holding capacitor;
Form an insulation course, be covered on above-mentioned first, second conductive layer and the aforesaid substrate;
On above-mentioned insulation course, form semi-conductor layer;
On above-mentioned semiconductor layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned first conductive layer directly over;
Form a doped silicon layer, be covered on above-mentioned island sacrifice layer and the above-mentioned semiconductor layer;
Form a metal level, be covered on above-mentioned doped silicon layer and the above-mentioned island sacrifice layer;
Limit the above-mentioned metal level of etching, form an one source pole electrode layer and a drain electrode layer in the top of above-mentioned first conductive layer; Wherein, between above-mentioned source electrode layer and this drain electrode layer, be defined as a passage area, above-mentioned doped silicon layer is exposed in the above-mentioned passage area; On the aforesaid substrate not by above-mentioned source electrode, drain electrode layer, and the area limiting that covers of above-mentioned passage area be a non-TFT regions, in above-mentioned non-TFT regions, also expose above-mentioned doped silicon layer;
With above-mentioned source electrode, drain electrode layer is mask, carry out an etching program, above-mentioned doped silicon layer in the above-mentioned passage area and island sacrifice layer are removed, to expose the above-mentioned semiconductor layer in the above-mentioned passage area, also remove simultaneously above-mentioned doped silicon layer and semiconductor layer in the above-mentioned non-TFT regions, to expose above-mentioned insulation course;
Form a protective seam, cover on above-mentioned drain electrode, source electrode, passage area and above-mentioned second conductive layer;
The above-mentioned protective seam of etching forms a perforation, exposing one of above-mentioned source electrode and drain electrode layer, and
Be shaped as a transparency conducting layer in the above-mentioned protective seam upper limit; and extend one of above-mentioned source electrode and drain electrode layer and this second conductive layer top; this transparency conducting layer forms by this perforation and one of above-mentioned source electrode and drain electrode layer and electrically contacts, and makes above-mentioned transparency conducting layer constitute a top electrode of above-mentioned holding capacitor.
20. method as claimed in claim 19, wherein, above-mentioned etching program is respectively R to the rate of etch of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer
IS, R
n, and R
aThe thickness of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively T
IS, T
n, and T
aRemove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) be not less than the above-mentioned doped silicon layer removed in the above-mentioned non-TFT regions and the time (T of semiconductor layer
n/ R
n+ T
a/ R
a).
21. method as claimed in claim 20, wherein, by controlling the mode of above-mentioned island sacrificial layer thickness, make above-mentioned etching program and when exposing above-mentioned semiconductor layer at the above-mentioned doped silicon layer of removing above-mentioned passage area and island sacrifice layer, except the above-mentioned doped silicon layer in the above-mentioned non-TFT regions and semiconductor layer are removed, also the above-mentioned insulation course that is exposed in the above-mentioned non-TFT regions is carried out etching, remove a part of above-mentioned insulation course, and reduce the thickness of above-mentioned insulation course.
22. method as claimed in claim 21 wherein, is R to the rate of etch of above-mentioned part of grid pole insulation course
INS, and the thickness of above-mentioned partial insulative layer is T
INS, wherein, remove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) will equal to remove the time (T of above-mentioned doped silicon layer, semiconductor layer and partial insulative layer in the above-mentioned non-TFT regions
n/ R
n+ T
a/ R
a+ T
INS/ R
INS).
23. the manufacture method of a Thin Film Transistor-LCD, this LCD comprise a thin film transistor (TFT) and a holding capacitor at least, its method for making may further comprise the steps:
One substrate is provided;
Limit to form first and second conductive layers on aforesaid substrate, respectively as a grid of a thin film transistor (TFT), an and bottom electrode of above-mentioned holding capacitor;
Form an insulation course, cover on above-mentioned first, second conductive layer and the aforesaid substrate;
On above-mentioned insulation course, form semi-conductor layer;
On above-mentioned semiconductor layer, limit to form an island sacrifice layer, and above-mentioned island sacrifice layer be positioned at above-mentioned first conductive layer directly over;
Forming a doped silicon layer on above-mentioned island sacrifice layer and above-mentioned semiconductor layer covers;
Form a metal level, be covered on above-mentioned doped silicon layer and the above-mentioned island sacrifice layer;
Limit the above-mentioned metal level of etching, form an one source pole electrode layer and a drain electrode layer in the top of above-mentioned first conductive layer, and directly over above-mentioned the second electrode lay, form a shielding electrode layer; Wherein, between above-mentioned source electrode layer and this drain electrode layer, limit a passage area, above-mentioned doped silicon layer is exposed in the above-mentioned passage area, above above-mentioned second conductive layer, be defined as a capacitor regions, the area limiting that is not covered by above-mentioned source electrode, drain electrode layer, above-mentioned capacitor regions and above-mentioned passage area on aforesaid substrate is a non-TFT regions, also exposes above-mentioned doped silicon layer in above-mentioned non-TFT regions;
With above-mentioned source electrode, drain electrode layer and capacitor regions is mask, carry out an etching program, above-mentioned doped silicon layer in the above-mentioned passage area and island sacrifice layer are removed, to expose the above-mentioned semiconductor layer in the above-mentioned passage area, also remove simultaneously above-mentioned doped silicon layer and semiconductor layer in the above-mentioned non-TFT regions, to expose above-mentioned insulation course;
Form a protective seam, cover on above-mentioned drain electrode, source electrode, passage area and the above-mentioned capacitor regions;
The above-mentioned protective seam of etching forms one first perforation to expose one of above-mentioned source electrode and drain electrode layer, reaches and forms one second perforation to expose the above-mentioned shielding electrode layer of above-mentioned capacitor regions; And
Be shaped as a transparency conducting layer in the above-mentioned protective seam upper limit; and extend one of above-mentioned source electrode and drain electrode layer and this shielding electrode layer top; this transparency conducting layer forms with one of above-mentioned source electrode and drain electrode layer by this first perforation and electrically contacts; this transparency conducting layer forms with above-mentioned shielding electrode layer by this second perforation and electrically contacts, and makes above-mentioned transparency conducting layer constitute a top electrode of above-mentioned holding capacitor.
24. method as claimed in claim 23, wherein, above-mentioned etching program is respectively R to the rate of etch of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer
IS, R
n, and R
aThe thickness of above-mentioned island sacrifice layer, doped silicon layer and semiconductor layer is respectively T
IS, T
n, and T
aRemove the above-mentioned island sacrifice layer of above-mentioned source electrode layer, drain electrode interlayer and the time (T of doped silicon layer
IS/ R
IS+ T
n/ R
n) equal to remove the above-mentioned doped silicon layer in the above-mentioned non-TFT regions and the time (T of semiconductor layer
n/ R
n+ T
a/ R
a).
25. a thin film transistor (TFT) comprises:
One island grid layer is arranged on the substrate;
One gate insulator covers above-mentioned island grid layer;
One island semiconductor layer is arranged on the above-mentioned gate insulator, and is positioned at the top of above-mentioned island grid layer;
An one source pole doped silicon layer and a drain electrode doped silicon layer are arranged on the above-mentioned island semiconductor layer, and above-mentioned source dopant silicon layer and drain electrode doped silicon layer area limiting separately are a passage area, expose above-mentioned island semiconductor layer in above-mentioned passage area;
The one first island sacrifice layer and the second island sacrifice layer are arranged at respectively on above-mentioned source dopant silicon layer and the drain electrode doped silicon layer, and with this passage area above-mentioned first island sacrifice layer in interval and the second island sacrifice layer;
The one source pole electrode is arranged on above-mentioned source dopant silicon layer and the above-mentioned first island sacrifice layer; And
One drain electrode is arranged on above-mentioned drain electrode doped silicon layer and the above-mentioned second island sacrifice layer;
Wherein, the thickness of above-mentioned first and second island sacrifice layer depends on the thickness of above-mentioned island semiconductor layer, makes this first island sacrifice layer of etching, this second island sacrifice layer, during with this island semiconductor layer, needs roughly the same etching period.
26. thin film transistor (TFT) as claimed in claim 25, wherein, the rate of etch of above-mentioned first and second island sacrifice layer is R
IS, above-mentioned source dopant silicon layer is R with the rate of etch of drain electrode doped silicon layer
n, the rate of etch of above-mentioned island semiconductor layer is R
a, when above-mentioned source electrode is T with drain electrode doped silicon layer thickness
nAnd the thickness of above-mentioned island semiconductor layer is T
aThe time, the thickness T of above-mentioned first and second island sacrifice layer
ISMust meet (T
IS/ R
IS+ T
n/ R
n) 〉=(T
n/ R
n+ T
a/ R
a) condition.
27. thin film transistor (TFT) as claimed in claim 25 also comprises a protective seam, covers above-mentioned source electrode, drain electrode and passage area, and above-mentioned thin film transistor (TFT) is used for a plane rotation LCD.
28. thin film transistor (TFT) as claimed in claim 25 also comprises:
One protective seam, in order to cover this thin film transistor (TFT), above-mentioned protective seam has an opening in above-mentioned drain electrode top; And
One transparency conducting layer is positioned on the above-mentioned drain electrode, and is electrically connected with above-mentioned drain electrode formation.
29. a thin film transistor (TFT) comprises:
One island grid layer is arranged on the substrate;
One gate insulator covers above-mentioned island grid layer;
One island semiconductor layer is arranged on the above-mentioned gate insulator, and is positioned at the top of above-mentioned island grid layer;
One first island sacrifice layer and one second island sacrifice layer, be arranged on the above-mentioned island semiconductor layer, above-mentioned first island sacrifice layer and second island sacrifice layer area limiting separately are a passage area, expose above-mentioned island semiconductor layer in above-mentioned passage area;
An one source pole doped silicon layer and a drain electrode doped silicon layer are arranged at above-mentioned island semiconductor layer, on the above-mentioned first and second island sacrifice layers, and with this passage area above-mentioned source dopant silicon layer in interval and drain electrode doped silicon layer; And
An one source pole electrode and a drain electrode are arranged at respectively on above-mentioned source dopant silicon layer and the drain electrode doped silicon layer;
Wherein, the thickness of above-mentioned first and second island sacrifice layer depends on the thickness of above-mentioned island semiconductor layer, when making this first island sacrifice layer of etching, this second island sacrifice layer and this island semiconductor layer, needs roughly the same etching period.
30. thin film transistor (TFT) as claimed in claim 29, wherein, the rate of etch of above-mentioned first and second island sacrifice layer is R
IS, above-mentioned source dopant silicon layer is R with the rate of etch of drain electrode doped silicon layer
n, the rate of etch of above-mentioned island semiconductor layer is R
a, when above-mentioned source electrode is T with drain electrode doped silicon layer thickness
nAnd the thickness of above-mentioned island semiconductor layer is T
aThe time, the thickness T of above-mentioned first and second island sacrifice layer
ISMust meet (T
IS/ R
IS+ T
n/ R
n) 〉=(T
n/ R
n+ T
a/ R
a) condition.
31. thin film transistor (TFT) as claimed in claim 29 also comprises a protective seam, covers above-mentioned source electrode, drain electrode and passage area, and above-mentioned thin film transistor (TFT) is used for a plane rotation LCD.
32. thin film transistor (TFT) as claimed in claim 29 also comprises:
One protective seam, in order to cover this thin film transistor (TFT), above-mentioned protective seam has an opening in above-mentioned drain electrode top; And
One transparency conducting layer is positioned on the above-mentioned drain electrode, and is electrically connected with above-mentioned drain electrode formation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001219251A CN1151405C (en) | 2000-07-25 | 2000-07-25 | Thin-film transistor LCD and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001219251A CN1151405C (en) | 2000-07-25 | 2000-07-25 | Thin-film transistor LCD and its manufacture |
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| Publication Number | Publication Date |
|---|---|
| CN1335533A CN1335533A (en) | 2002-02-13 |
| CN1151405C true CN1151405C (en) | 2004-05-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB001219251A Expired - Lifetime CN1151405C (en) | 2000-07-25 | 2000-07-25 | Thin-film transistor LCD and its manufacture |
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| CN (1) | CN1151405C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100368917C (en) * | 2005-09-27 | 2008-02-13 | 广辉电子股份有限公司 | Array base plate for liquid crystal display and producing method thereof |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3970813B2 (en) * | 2002-09-05 | 2007-09-05 | 三星コーニング精密琉璃株式会社 | Film removing apparatus and film removing method |
| KR100539833B1 (en) * | 2002-10-21 | 2005-12-28 | 엘지.필립스 엘시디 주식회사 | array circuit board of LCD and fabrication method of thereof |
| WO2004090623A1 (en) * | 2003-04-11 | 2004-10-21 | Quanta Display Inc. | Method for fabrcating a thin film transistor liquid crystal display |
| CN1331202C (en) * | 2004-03-19 | 2007-08-08 | 友达光电股份有限公司 | Thin film transistor and its mfg. method |
| CN100368911C (en) * | 2005-02-03 | 2008-02-13 | 广辉电子股份有限公司 | Liquid crystal display device |
| CN100368912C (en) * | 2005-02-03 | 2008-02-13 | 广辉电子股份有限公司 | Manufacturing method of liquid crystal display device |
| WO2012002974A1 (en) * | 2010-07-02 | 2012-01-05 | Hewlett-Packard Development Company, L.P. | Thin film transistors |
| CN102420183B (en) * | 2011-12-07 | 2014-02-05 | 深圳市华星光电技术有限公司 | Manufacturing method of TFT (Thin Film Transistor) array substrate and TFT array substrate |
| TWI613488B (en) * | 2017-06-19 | 2018-02-01 | 友達光電股份有限公司 | Display panel and method for forming tether |
| CN107564966B (en) * | 2017-08-07 | 2020-05-05 | 武汉华星光电半导体显示技术有限公司 | Thin film transistor, method for manufacturing thin film transistor, and liquid crystal display panel |
-
2000
- 2000-07-25 CN CNB001219251A patent/CN1151405C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100368917C (en) * | 2005-09-27 | 2008-02-13 | 广辉电子股份有限公司 | Array base plate for liquid crystal display and producing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1335533A (en) | 2002-02-13 |
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