CN110071107A - A kind of dual-die device of terminal trenches structure and preparation method thereof - Google Patents
A kind of dual-die device of terminal trenches structure and preparation method thereof Download PDFInfo
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- CN110071107A CN110071107A CN201910550117.XA CN201910550117A CN110071107A CN 110071107 A CN110071107 A CN 110071107A CN 201910550117 A CN201910550117 A CN 201910550117A CN 110071107 A CN110071107 A CN 110071107A
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- 238000002360 preparation method Methods 0.000 title abstract description 4
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- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
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- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 18
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 230000001376 precipitating effect Effects 0.000 claims description 3
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 claims 1
- 230000003628 erosive effect Effects 0.000 claims 1
- 239000007789 gas Substances 0.000 abstract description 22
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000001681 protective effect Effects 0.000 abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000009826 distribution Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- 239000000203 mixture Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
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- 238000002513 implantation Methods 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
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- 238000000926 separation method Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention discloses dual-die devices of a kind of terminal trenches structure and preparation method thereof.For the present invention when drain electrode pressurization, P- body area and N- epitaxial layer form depletion layer, and by terminal, the breakdown voltage of entire terminal structure are promoted by the pressure resistance of terminal trenches grid oxygen, reduces the purpose of device reverse leakage current.P- body area is an overall structure, is not necessarily to the gluing photoetching on the upside of gate oxide before making P- body area.Connecting hole is divided into two step production; when being etched under the second mixed gas; the protective film that second mixed gas is formed is relatively thin, and then the second connecting hole is arranged to round or ellipse shape, after carrying out hole injection and diffusion; the contact zone of formation is in crescent shape; the area of contact zone distribution is wider, is conducive to base resistor reduction, to prevent the conducting of parasitic triode; and then improve UIS ability, significant effect.Breakdown voltage by improving device of the invention above about can be improved 8%, and conducting resistance can reduce by 0.6%.
Description
Technical field
The present invention relates to semiconductor fields, and in particular to a kind of dual-die device of terminal trenches structure and its production side
Method.
Background technique
NMOS as two would generally be used in some lithium battery charge and discharge protective circuits is used together, and is realized
Overcharge, over-discharge, overcurrent, short circuit when battery protection function.
Normal practice is that two NMOS carry terminal structure, is then encapsulated in together, disadvantage of this is that after encapsulation
The area of chip is larger.
Then there are some dual-die devices, such as application No. is 201510683826.7 and 201510683582.2 disclosures
Dual-die device, be only by two tube cores use a terminal, reduce the area of chip, application No. is
Metal layer also is arranged by side at the terminal, to stop outer signals to be interfered in dual-die device disclosed in 201510683582.2
Chip operation.In chip manufacturing proces and the chip package in later period, the oxide of chip surface is easy to produce or introduces
Surface charge (including fixed charge and movable charge), when its quantity reaches a certain level, it is possible to incude in silicon face
Carrier out, silicon face can accumulate, exhaust, one of three kinds of situations of transoid.It i.e. can be in active area and scribe line for transoid
Between form surface conduction channel, seriously affect the performance of device or even cause chip failure.And it is passed through from actual chip manufacturing
It examines, the phenomenon that transoid of silicon face results in surface conduction channel is very universal, common, and the presence of surface conduction channel is not
It can ignore, therefore, it is necessary to be further improved.
Summary of the invention
The purpose of the present invention is in view of the deficienciess of the prior art, providing a kind of dual-die device of terminal trenches structure
And preparation method thereof.
To achieve the above object, in a first aspect, the present invention provides a kind of dual-die devices of terminal trenches structure
Production method, comprising the following steps:
Step 1: providing the substrate of the first conduction type, and side makes epitaxial layer over the substrate；
Step 2: etching forms several first grooves, second groove and setting in first groove and the second ditch on said epitaxial layer there
Third groove between slot；
Step 3: side and first groove, the long gate oxide of second groove and third groove inside on said epitaxial layer there；
Step 4: the deposit polycrystalline silicon on the outside of the gate oxide, and return and carve on first groove, second groove and third groove
It holds and with the polysilicon of exterior domain；
Step 5: impurity injection being executed to epitaxial layer and pushes away trap operation, to form the body area that the second conduction type is lightly doped；
Step 6: injection and the annealing operation of impurity are executed to the body area of first groove, second groove and third trench region, with
It is respectively formed the first source region, the second source region and termination environment of the first conduction type heavy doping；
Step 7: in the long dielectric layer in the upside of gate oxide and polysilicon；
Step 8: etching forms connecting hole, to hole injection and annealing operation is carried out on the downside of the connecting hole being located on the upside of body area, with shape
At the contact zone of the second conduction type heavy doping；
Step 9: precipitating metal and partial etching, to be respectively formed the first source metal and the second source metal that connect with body area
And the terminal metal being separately connected with the polysilicon in body area and third groove.
Further, the contact zone is in crescent shape.
Further, the etching forms connecting hole and includes:
Hole gluing and exposure-processed are carried out on the upside of dielectric layer, under the first mixed gas, by Jie on the upside of source region and termination environment
Matter layer and gate oxide etch the first connecting hole；
Under the second mixed gas, the second connecting hole is etched on the downside of the first connecting hole.
Further, the second connecting hole vertical section elliptical shape.
Further, second mixed gas is Cl2, HBr, He, O2, SF6, CHF3 and CF4 mixed gas.
Further, the mixed proportion of Cl2, HBr, He, O2, SF6, CHF3 and CF4 are as follows: 4/6/14/35/3/32/40.
Further, in step 3, it first long sacrificial oxide layer and is removed on the inside of side and groove on said epitaxial layer there,
Long gate oxide again.
In second aspect, the present invention also provides a kind of dual-die devices of terminal trenches structure, including the first conductive-type
The substrate and epitaxial layer of type, on the epitaxial layer etching formed several first grooves, second groove and setting first groove with
Third groove between second groove, the epitaxial layer upside, first groove, second groove and third groove inside with grid
Oxide layer is deposited with polysilicon, the epitaxial layer on the outside of the gate oxide in the first groove, second groove and third groove
On be formed with the body area that the second conduction type is lightly doped, the lower end surface setting in the body area is in first groove, second groove and the
The upside of the lower end surface of three grooves forms the first source region, the second source region and the end of the first conduction type heavy doping in the body area
Petiolarea, the long dielectric layer in the upside of the gate oxide and polysilicon, etch away sections body area and polysilicon in third groove and
Gate oxide and dielectric layer on the upside of it deeply have second to lead to form connecting hole to the formation on the downside of the connecting hole in body area
The contact zone of electric type heavy doping, be formed on the upside of the dielectric layer the first source metal, the second source metal and with terminal gold
Belong to, first source metal and the second source metal are connect by connecting hole with body area, and the terminal metal passes through connecting hole
It is separately connected with the polysilicon in body area and third groove.
Further, the contact zone is in crescent shape.
Further, the connecting hole on the upside of body area includes the first connecting hole etched in dielectric layer and gate oxide
With the second connecting hole etched on the downside of the first connecting hole, the vertical section elliptical shape of second connecting hole.
The utility model has the advantages that the present invention when drain pressurization when, P- body area and N- epitaxial layer form depletion layer, and by terminal,
The breakdown voltage of entire terminal structure is promoted by the pressure resistance of terminal trenches grid oxygen, reduces the purpose of device reverse leakage current.P-
Body area is an overall structure, is not necessarily to the gluing photoetching on the upside of gate oxide before making P- body area.Connecting hole is divided into two
Step production, when etching under the second mixed gas, the protective film that the second mixed gas is formed is relatively thin, and then by the second connecting hole
It is arranged to round or ellipse shape, after carrying out hole injection and diffusion, the contact zone of formation is in crescent shape, the face of contact zone distribution
Product is wider, is conducive to base resistor reduction, to prevent the conducting of parasitic triode, and then improves UIS ability, and effect is aobvious
It writes.Breakdown voltage by improving device of the invention above about can be improved 8%, and conducting resistance can reduce by 0.6%.
Detailed description of the invention
Fig. 1 is the schematic diagram after etching groove；
Fig. 2 is the schematic diagram after long gate oxide；
Fig. 3 is the schematic diagram after deposit polycrystalline silicon；
Fig. 4 is the schematic diagram for carrying out polysilicon Hui Kehou；
Fig. 5 is the schematic diagram to be formed behind the first body area, the second body area and third body area；
Fig. 6 is the schematic diagram to be formed behind the first source region, the second source region and termination environment；
Fig. 7 is the schematic diagram after long dielectric layer；
Fig. 8 is the schematic diagram to be formed behind connecting hole and contact zone；
Fig. 9 is the structural schematic diagram of the dual-die device of terminal trenches structure.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the present invention is furture elucidated, and the present embodiment is with technical solution of the present invention
Premised under implemented, it should be understood that these examples are only for illustrating the present invention and are not intended to limit the scope of the present invention.
In conjunction with Fig. 1 to 9, the embodiment of the invention provides a kind of production method of the dual-die device of terminal trenches structure,
The following steps are included:
Step 1: as shown in Figure 1, providing the substrate 1 of the first conduction type, and epitaxial layer 2 is made on the upside of substrate 1.Wherein, it serves as a contrast
Bottom 1 is heavy doping, and epitaxial layer 2 is that the first conduction type is lightly doped.
Step 2: etching forms several first grooves 6, second groove 7 and setting in first groove 6 and the on epitaxial layer 2
Third groove 8 between two grooves 7.Specifically, being first used as masking layer, the thickness of oxide layer 3 in the 2 long oxide layer 3 in upside of epitaxial layer
Degree is preferably 3000-5000, then in 3 upside gluing 4 of masking layer, and makes several groove opening areas 5, groove opening area 5 by lithography
Width preferably at 0.2 to 0.8 μm, successively the masking layer 3 and epitaxial layer 2 of the downside of groove opening area 5 are performed etching, just outside
The two sides for prolonging layer 2 etch to form several spaced first grooves 6, second groove 7 and third groove 8.First groove 6,
The depth of two grooves 7 and third groove is preferably at 0.5 to 2 μm.First groove 6 and second groove 7 can be respectively multiple, third
Groove 8 is preferably 1.
Step 3: as shown in Fig. 2, long on the inside of 2 upside of epitaxial layer and first groove 6, second groove 7 and third groove 8
Gate oxide 9.Before long gate oxide 9, glue 4 also first should also should be first removed, is then etched away again in first groove 6, the second ditch
The 2 remaining oxide layer 3 in upside of epitaxial layer other than slot 7 and third groove 8.It is further preferred that before long gate oxide 9, it can
First long sacrificial oxide layer and to be removed in the upside of epitaxial layer 2 and first groove 6, second groove 7 and 8 inside of third groove,
Impurity is precipitated.
Step 4: as shown in Figures 3 and 4, in 9 outside deposit polycrystalline silicon 10 of gate oxide, and returning and carve first groove 6, second
Groove 7 and 8 upper end of third groove and the polysilicon 10 with exterior domain.So that polysilicon 10 is only filled in first groove 6, the second ditch
In slot 7 and third groove 8, and the upper surface of polysilicon 10 is preferably shorter than the upper surface of epitaxial layer 2.
Step 5: as shown in figure 5, impurity injection is executed to epitaxial layer 2 and pushes away trap operation, it is light to form the second conduction type
The body area 11 of doping.Body area 11 is preferably injected boron element, Implantation Energy are as follows: 30-90Kev, injection metering: 5E12-3E13.Body area
11 bottom surface is on the bottom surface of ditch first groove 6, second groove 7 and third groove 8, i.e. first groove 6,7 and of second groove
Third groove 8 extends through body area 11, and the bottom of first groove 6, second groove 7 and third groove 8 is connect with epitaxial layer 2.
Step 6: as shown in fig. 6, the body area 11 to 8 region of first groove 6, second groove 7 and third groove executes impurity
Injection and annealing operation, to be respectively formed the first source region 12, the second source region 13 and termination environment of the first conduction type heavy doping
14。
Step 7: as shown in fig. 7, in the long dielectric layer 15 in the upside of gate oxide 9 and polysilicon 10.The thickness of dielectric layer 15
It is 8000 or so.Dielectric layer 15 is used as grid and source electrode separation layer.
Step 8: as shown in figure 8, etching forms connecting hole, to progress hole injection on the downside of the connecting hole for being located at 11 upside of body area
And annealing operation, to form the contact zone 16 of the second conduction type heavy doping.The contact zone 16 of the embodiment of the present invention is preferably provided with
At crescent shape, can be realized by changing the shape of the connecting hole of 11 upside of body area.Specifically, etching forms the company of 11 upside of body area
Connecing hole includes: that hole gluing and exposure-processed are carried out on the upside of dielectric layer 15, under the first mixed gas, by the first source region 12, the
The dielectric layer 15 and gate oxide 9 of 14 upside of two source regions 13 and termination environment etch the first connecting hole 17.First connecting hole 17 with
Connecting hole in the prior art is identical, and cross section is rectangular, and the composition and ratio of the first mixed gas can also be used existing
Have a technology, the preferred composition of the first mixed gas is Cl2, HBr, He, SF6 and CHF3 mixed gas, wherein Cl2, HBr, He,
The preferred mixed proportion of SF6 and CHF3 are as follows: 3/10/24/4/20.Then, under the second mixed gas, under the first connecting hole 17
The second connecting hole 18 is etched in the area Ce Ti 11.Due to being also provided with connecting hole on the upside of third groove 8, connecting hole herein and
The connecting hole of area of grid not shown in the figure can make together formation with the first connecting hole 17 and the second connecting hole 18.Second
The vertical section of connecting hole 18 is preferably provided with rounded or elliptical shape, as long as guaranteeing that the bottom of the second connecting hole 18 is for arc shape
It can.The preferred composition of second mixed gas is Cl2, HBr, He, O2, SF6, CHF3 and CF4 mixed gas.Wherein, Cl2, HBr, He,
The mixed proportion of O2, SF6, CHF3 and CF4 are as follows: 4/6/14/35/3/32/40.
Step 9: as shown in figure 9, precipitating metal and partial etching, to be respectively formed the first source electrode connecting with body area 11 gold
Belong to 19 and second source metal 20 and the terminal metal 21 that is separately connected of polysilicon 10 in body area 11 and third groove 8.
As shown in Figure 8-9, it will be understood by those skilled in the art that the embodiment of the invention also provides a kind of terminal trenches
The dual-die device of structure, the device include the substrate 1 and epitaxial layer 2 of the first conduction type, wherein substrate 1 is heavy doping, outside
Prolonging layer 2 is that the first conduction type is lightly doped.Etching forms several first grooves 6, second groove 7 and setting the on epitaxial layer 2
Third groove 8 between one groove 6 and second groove 7, the width of first groove 6, second groove 7 and third groove 8 are preferably
0.2 to 0.8 μm, depth is preferably 0.5 to 2 μm.In 2 upside of epitaxial layer, first groove 6, second groove 7 and third groove 8
Inside with gate oxide 9, be deposited on the outside of the gate oxide 9 in first groove 6, second groove 7 and third groove 8 more
Crystal silicon 10 is formed with the body area 11 that the second conduction type is lightly doped on epitaxial layer 2, and body area 11 is preferably injected boron element, injection
Energy are as follows: 30-90Kev, injection metering: 5E12-3E13.The lower end surface in body area 11 is arranged in first groove 6,7 and of second groove
The upside of the lower end surface of third groove 8 forms in the body area 11 in 8 region of first groove 6, second groove 7 and third groove
The first source region 12, the second source region 13 and the termination environment 14 of one conduction type heavy doping, in the upside of gate oxide 9 and polysilicon 10
Long dielectric layer 15, the gate oxide 9 and dielectric layer of polysilicon 10 and its upside in etch away sections body area 11 and third groove 8
15, to form connecting hole, the contact zone 16 of the second conduction type heavy doping is deeply formed with to the connecting hole downside in body area 11,
The first source metal 19, the second source metal 20 and terminal metal 21 are formed on the upside of dielectric layer 15, in the first source metal
19 and second source metal 20 connect with body area 11 by connecting hole, terminal metal 21 passes through connecting hole and body area 11 and third ditch
Polysilicon 10 in slot 8 is separately connected.
Contact zone 16 is preferably provided to crescent shape.In order to produce the contact zone 16 of crescent shape, the position of the embodiment of the present invention
The connecting hole of 11 upside Yu Tiqu includes carving on the first connecting hole 17 and body area 11 that dielectric layer 15 and gate oxide 9 etch
The second connecting hole 18 out is lost, the downside of the first connecting hole 17 is arranged in the second connecting hole 18.First connecting hole 17 and existing skill
Connecting hole in art is identical, and cross section is rectangular, and the prior art can also be used in the composition and ratio of the first mixed gas,
The preferred composition of first mixed gas be Cl2, HBr, He, SF6 and CHF3 mixed gas, wherein Cl2, HBr, He, SF6 and
The preferred mixed proportion of CHF3 are as follows: 3/10/24/4/20.The vertical section of second connecting hole 18 is preferably provided with rounded or oval
Shape, as long as guaranteeing that the bottom of the second connecting hole 18 is arc shape.The preferred composition of second mixed gas be Cl2, HBr, He,
O2, SF6, CHF3 and CF4 mixed gas.Wherein, the mixed proportion of Cl2, HBr, He, O2, SF6, CHF3 and CF4 are as follows: 4/6/14/
35/3/32/40。
For the present invention when drain electrode pressurization, P- body area and N- epitaxial layer form depletion layer, and by terminal, pass through terminal ditch
The pressure resistance of slot grid oxygen promotes the breakdown voltage of entire terminal structure, reduces the purpose of device reverse leakage current.P- body area is one
Overall structure is not necessarily to the gluing photoetching on the upside of gate oxide before making P- body area.Connecting hole is divided into two step production,
When etching under the second mixed gas, the protective film that the second mixed gas is formed is relatively thin, and then the second connecting hole is arranged to circle
Or elliptical shape, after carrying out hole injection and diffusion, the contact zone of formation is in crescent shape, and the area of contact zone distribution is wider, is had
Conducive to base resistor reduction, to prevent the conducting of parasitic triode, and then UIS ability, significant effect are improved.By with
The upper breakdown voltage for improving device of the invention about can be improved 8%, and conducting resistance can reduce by 0.6%.
It should be noted that illustrating by taking NMOS as an example, above-mentioned first conduction type is N-type, and the second conduction type is p-type.
Illustrate by taking PMOS as an example, above-mentioned first conduction type is p-type, and the second conduction type is N-type.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, other parts not specifically described belong to the prior art or common knowledge.In the premise for not departing from the principle of the invention
Under, several improvements and modifications can also be made, these modifications and embellishments should also be considered as the scope of protection of the present invention.
Claims (10)
1. a kind of production method of the dual-die device of terminal trenches structure, which comprises the following steps:
Step 1: providing the substrate of the first conduction type, and side makes epitaxial layer over the substrate；
Step 2: etching forms several first grooves, second groove and setting in first groove and the second ditch on said epitaxial layer there
Third groove between slot；
Step 3: side and first groove, the long gate oxide of second groove and third groove inside on said epitaxial layer there；
Step 4: the deposit polycrystalline silicon on the outside of the gate oxide, and return and carve on first groove, second groove and third groove
It holds and with the polysilicon of exterior domain；
Step 5: impurity injection being executed to epitaxial layer and pushes away trap operation, to form the body area that the second conduction type is lightly doped；
Step 6: injection and the annealing operation of impurity are executed to the body area of first groove, second groove and third trench region, with
It is respectively formed the first source region, the second source region and termination environment of the first conduction type heavy doping；
Step 7: in the long dielectric layer in the upside of gate oxide and polysilicon；
Step 8: etching forms connecting hole, to hole injection and annealing operation is carried out on the downside of the connecting hole being located on the upside of body area, with shape
At the contact zone of the second conduction type heavy doping；
Step 9: precipitating metal and partial etching, to be respectively formed the first source metal and the second source metal that connect with body area
And the terminal metal being separately connected with the polysilicon in body area and third groove.
2. the production method of the dual-die device of terminal trenches structure according to claim 1, which is characterized in that described to connect
Touching area is in crescent shape.
3. the production method of the dual-die device of terminal trenches structure according to claim 2, which is characterized in that the quarter
Erosion forms connecting hole and includes:
Hole gluing and exposure-processed are carried out on the upside of dielectric layer, under the first mixed gas, by Jie on the upside of source region and termination environment
Matter layer and gate oxide etch the first connecting hole；
Under the second mixed gas, the second connecting hole is etched on the downside of the first connecting hole.
4. the production method of the dual-die device of terminal trenches structure according to claim 3, which is characterized in that described
Two connecting hole vertical section elliptical shapes.
5. the production method of the dual-die device of terminal trenches structure according to claim 3, which is characterized in that described
Two mixed gas are Cl2, HBr, He, O2, SF6, CHF3 and CF4 mixed gas.
6. the production method of the dual-die device of terminal trenches structure according to claim 5, which is characterized in that Cl2,
The mixed proportion of HBr, He, O2, SF6, CHF3 and CF4 are as follows: 4/6/14/35/3/32/40.
7. the production method of the dual-die device of terminal trenches structure according to claim 1, which is characterized in that in step
In 3, first long sacrificial oxide layer and removed on the inside of side and groove on said epitaxial layer there, then long gate oxide.
8. a kind of dual-die device of terminal trenches structure, which is characterized in that substrate and epitaxial layer including the first conduction type,
Etching forms several first grooves, second groove and the third being arranged between first groove and second groove on the epitaxial layer
Groove, the epitaxial layer upside, first groove, second groove and third groove inside with gate oxide, first ditch
It is deposited with polysilicon on the outside of gate oxide in slot, second groove and third groove, the second conduction is formed on the epitaxial layer
The lower end surface of first groove, second groove and third groove is arranged in the body area that type is lightly doped, the lower end surface in the body area
Upside forms the first source region, the second source region and the termination environment of the first conduction type heavy doping, the gate oxide in the body area
With the long dielectric layer in upside of polysilicon, the gate oxide of etch away sections body area and polysilicon and its upside in third groove and
Dielectric layer deeply has the contact of the second conduction type heavy doping to form connecting hole to the formation on the downside of the connecting hole in body area
Area, be formed on the upside of the dielectric layer the first source metal, the second source metal and and terminal metal, first source metal
It is connect by connecting hole with body area with the second source metal, the terminal metal passes through in connecting hole and body area and third groove
Polysilicon is separately connected.
9. the dual-die device of terminal trenches structure according to claim 8, which is characterized in that the contact zone is in crescent moon
Shape.
10. the dual-die device of terminal trenches structure according to claim 9, which is characterized in that on the upside of body area
Connecting hole includes the first connecting hole etched in dielectric layer and gate oxide and etch on the downside of the first connecting hole second
Connecting hole, the vertical section elliptical shape of second connecting hole.
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| US20110254070A1 (en) * | 2009-11-20 | 2011-10-20 | Force Mos Technology Co. Ltd. | Trench mosfet with trenched floating gates in termination |
| CN102544107A (en) * | 2012-03-13 | 2012-07-04 | 无锡新洁能功率半导体有限公司 | Power metal oxide semiconductor (MOS) device with improved terminal structure and manufacturing method for power MOS device |
| CN105206608A (en) * | 2015-10-20 | 2015-12-30 | 福建省福芯电子科技有限公司 | Double-tube-core Trench MOSFET and processing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110254070A1 (en) * | 2009-11-20 | 2011-10-20 | Force Mos Technology Co. Ltd. | Trench mosfet with trenched floating gates in termination |
| CN102544107A (en) * | 2012-03-13 | 2012-07-04 | 无锡新洁能功率半导体有限公司 | Power metal oxide semiconductor (MOS) device with improved terminal structure and manufacturing method for power MOS device |
| CN105206608A (en) * | 2015-10-20 | 2015-12-30 | 福建省福芯电子科技有限公司 | Double-tube-core Trench MOSFET and processing method thereof |
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