CN209843711U - Double-tube-core device - Google Patents
Double-tube-core device Download PDFInfo
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- CN209843711U CN209843711U CN201920954924.3U CN201920954924U CN209843711U CN 209843711 U CN209843711 U CN 209843711U CN 201920954924 U CN201920954924 U CN 201920954924U CN 209843711 U CN209843711 U CN 209843711U
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Abstract
The utility model discloses a double tube core device. The utility model discloses when pressurizing from the drain electrode, P-body region extension and N-epitaxial layer form the layer that exhausts, and the layer that exhausts of source region bottom and terminal region slowly becomes and cuts to in the terminal to weakening chip edge electric field realizes promoting the breakdown voltage of whole terminal structure, reduces the reverse purpose of leaking current of device. The utility model discloses fall into two step preparation with the connecting hole, when the sculpture under the second mist, the protection film that the second mist formed is thinner, and then sets the second connecting hole to circular or oval shape, after carrying out hole injection and diffusion, the contact zone of formation is crescent, and the area that the contact zone distributes is wider, is favorable to reducing of base region resistance to prevent switching on of parasitic triode, and then improved the UIS ability, the effect is showing. Through the improvement, the utility model discloses a breakdown voltage of device can improve 11% approximately, and on-resistance can reduce 3.3% approximately.
Description
Technical Field
The utility model relates to a semiconductor field, concretely relates to double tube core device.
Background
Two same NMOS are commonly used in some lithium battery charging and discharging protection circuits, so that the battery protection function under the conditions of overcharge, overdischarge, overcurrent, short circuit and the like is realized.
The conventional method is that two NMOS self-contained terminal structures are packaged together, and the disadvantage of this is that the area of the packaged chip is large.
Some dual-die devices, such as those disclosed in applications 201510683826.7 and 201510683582.2, have been developed, which simply use two dies with a terminal to reduce the chip area, and the dual-die device disclosed in application 201510683582.2 also has a metal layer disposed on the upper side of the terminal to prevent external signals from interfering with the operation of the chip. In the chip manufacturing process and later chip packaging, the oxide on the chip surface is easy to generate or introduce surface charges (including fixed charges and movable charges), and when the amount of the oxide reaches a certain degree, carriers can be induced on the silicon surface, and one of the three situations of accumulation, depletion and inversion can occur on the silicon surface. For inversion, a surface conduction channel is formed between the active region and the scribing groove, which seriously affects the performance of the device and even causes chip failure. From the experience of actual chip manufacturing, the phenomenon that the inversion of the silicon surface causes the formation of surface conduction channels is very common and common, and the existence of the surface conduction channels is not negligible, so that further improvement is needed.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a double tube core device to the not enough of prior art existence.
In order to achieve the above object, the present invention provides a dual die device, which comprises a substrate of a first conductive type and an epitaxial layer, wherein a plurality of first trenches and second trenches are formed on both sides of the epitaxial layer by etching, a gate oxide layer is grown on the inner sides of the first trenches and the second trenches, polysilicon is deposited on the outer sides of the gate oxide layer in the first trenches and the second trenches, a first body region, a second body region and a third body region of a second conductive type are formed on both sides of the first trenches and the second trenches and in the epitaxial layer between the first trenches and the second trenches, respectively, the lower end surfaces of the first body region and the second body region are disposed on the upper sides of the lower end surfaces of the first trenches and the second trenches, and a first source region, a second source region and a terminal region of the first conductive type are formed in the first body region, the second body region and the third body region, respectively, the gate oxide layer and the upper side of the polycrystalline silicon are long, a part of the first body region, the second body region and the third body region, and the gate oxide layer and the dielectric layer on the upper side of the gate oxide layer and the polycrystalline silicon are etched to form a connecting hole, contact regions with second conductive type heavy doping are formed in the first body region, the second body region and the third body region on the lower side of the connecting hole, first source electrode metal, second source electrode metal and terminal metal are formed on the upper side of the dielectric layer, and the first source electrode metal, the second source electrode metal and the terminal metal are connected with the first body region, the second body region and the third body region through the connecting hole respectively.
Further, the contact area is crescent.
Furthermore, the connecting holes comprise a first connecting hole etched in the dielectric layer and the gate oxide layer and a second connecting hole etched on the lower side of the first connecting hole, and the vertical section of the second connecting hole is oval.
Further, the depth of the first trench and the second trench is 0.5 to 2 μm.
Further, the thickness of the dielectric layer is
Further, the first body region, the second body region and the third body region are formed by boron element implantation, and the implantation energy is as follows: 30-90Kev, injection dosing: 5E12-3E 13.
Has the advantages that: the utility model discloses when pressurizing from the drain electrode, P-body region extension and N-epitaxial layer form the layer that exhausts, and the layer that exhausts of source region bottom and terminal region slowly becomes and cuts to in the terminal to weakening chip edge electric field realizes promoting the breakdown voltage of whole terminal structure, reduces the reverse purpose of leaking current of device. The utility model discloses fall into two step preparation with the connecting hole, when the sculpture under the second mist, the protection film that the second mist formed is thinner, and then sets the second connecting hole to circular or oval shape, after carrying out hole injection and diffusion, the contact zone of formation is crescent, and the area that the contact zone distributes is wider, is favorable to reducing of base region resistance to prevent switching on of parasitic triode, and then improved the UIS ability, the effect is showing. Through the improvement, the utility model discloses a breakdown voltage of device can improve 11% approximately, and on-resistance can reduce 3.3% approximately.
Drawings
FIG. 1 is a schematic illustration after etching a trench;
FIG. 2 is a schematic diagram after a long gate oxide;
FIG. 3 is a schematic illustration after deposition of polysilicon;
FIG. 4 is a schematic diagram after a polysilicon etch back is performed;
fig. 5 is a schematic diagram after forming a first body region, a second body region and a third body region;
fig. 6 is a schematic diagram after forming a first source region, a second source region and a termination region;
FIG. 7 is a schematic illustration after a long dielectric layer;
FIG. 8 is a schematic view after forming a connection hole and a contact region;
fig. 9 is a schematic diagram of a structure of a dual die device.
Detailed Description
The present invention will be further clarified by the following embodiments with reference to the attached drawings, which are implemented on the premise of the technical solution of the present invention, and it should be understood that these embodiments are only used for illustrating the present invention and are not used for limiting the scope of the present invention.
With reference to fig. 1 to 9, an embodiment of the present invention provides a method for manufacturing a dual die device, including the following steps:
step 1: as shown in fig. 1, a substrate 1 of a first conductivity type is provided and an epitaxial layer 2 is formed on the upper side of the substrate 1. The substrate 1 is heavily doped, and the epitaxial layer 2 is lightly doped with the first conductivity type.
Step 2: etching two sides of the epitaxial layer 2 to form a plurality of first trenches 6 and second trenches 7 which are arranged at intervals; specifically, the oxide layer 3 is grown on the epitaxial layer 2 as a mask layer, and the thickness of the oxide layer 3 is preferably set to be thickAnd then coating glue 4 on the upper side of the masking layer 3, photoetching a plurality of groove opening areas 5, wherein the width of each groove opening area 5 is preferably 0.2-0.8 mu m, and etching the masking layer 3 and the epitaxial layer 2 on the lower side of each groove opening area 5 in sequence to form a plurality of first grooves 6 and second grooves 7 which are arranged at intervals on two sides of the epitaxial layer 2 in an etching mode. The depth of the first trenches 6 and the second trenches 7 is preferably 0.5 to 2 μm. The first trench 6 and the second trench 7 may be plural in number, respectively.
And step 3: as shown in fig. 2, a gate oxide layer 8 is grown on the upper side of the epitaxial layer 2 and inside the first trench 6 and the second trench 7. Before the gate oxide layer 8 is grown, the glue 4 should be removed first, and then the oxide layer 3 remaining on the upper side of the epitaxial layer 2 outside the first trench 6 and the second trench 7 should be etched. More preferably, before growing the gate oxide layer 8, a sacrificial oxide layer may be grown and removed on the upper side of the epitaxial layer 2 and inside the first trench 6 and the second trench 7 to precipitate impurities.
And 4, step 4: as shown in fig. 3 to 4, polysilicon 9 is deposited outside the gate oxide layer 8, and the polysilicon 9 is etched back at the upper ends of the first trench 6 and the second trench 7 and in the areas outside. So that the polysilicon 9 is filled only in the first trench 6 and the second trench 7, and the upper end face of the polysilicon 9 is preferably lower than the upper end face of the epitaxial layer 2.
And 5: as shown in fig. 5, the epitaxial layer 2 between the first trench 6 and the second trench 7 and between the first trench 6 and the second trench 7 are patterned by photoresist and photolithography, the upper sides of the first trench 6 and the second trench 7 and a portion of the gate oxide layer 8 between the first trench 6 and the second trench 7 are exposed, and then impurity implantation and drive-in operations are performed to form a first body region 10, a second body region 11 and a third body region 12, which are lightly doped with the second conductivity type and are independent of each other, respectively. The first, second and third body regions 10, 11, 12 are preferably implanted with boron elements at an implant energy of: 30-90Kev, injection dosing: 5E12-3E 13. The bottom surfaces of the first body region 10 and the second body region 11 are above the bottom surfaces of the first trench 6 and the second trench 7, i.e. the first trench 6 and the second trench 7 respectively penetrate the first body region 10 and the second body region 11, and the bottom of the first trench 6 and the second trench 7 are connected with the epitaxial layer 2.
Step 6: as shown in fig. 6, impurity implantation and annealing operations are performed on the first body region 10, the second body region 11 and the third body region 12 to form a first source region 13, a second source region 14 and a termination region 15, respectively, which are heavily doped with the first conductivity type.
And 7: as shown in fig. 7, a dielectric layer 16 is grown on the upper side of the gate oxide layer 8 and the polysilicon 9. The dielectric layer 16 has a thickness ofLeft and right. Dielectric layer 16 serves as a gate and source spacer.
And 8: as shown in fig. 8, a connection hole is formed by etching, and hole implantation and annealing operations are performed in the first body region 10, the second body region 11 and the third body region 12 on the lower side of the connection hole to form heavily doped contact regions 17 of the second conductivity type, respectively. The contact area 17 of the present embodiment is preferably arranged in a crescent shape, which can be achieved by changing the shape of the connection hole. Specifically, the step of forming the connecting hole by etching comprises the following steps: and (3) performing hole gluing and exposure treatment on the upper side of the dielectric layer 16, and etching the dielectric layer 16 and the gate oxide layer 8 on the upper sides of the first source region 13, the second source region 14 and the terminal region 15 to form a first connecting hole 18 under the first mixed gas. The first connection hole 18 has a rectangular cross section, and the composition and ratio of the first mixed gas can be the same as those of the prior art, and the preferred composition of the first mixed gas is Cl2, HBr, He, SF6 and CHF3 mixed gas, wherein the preferred mixing ratio of Cl2, HBr, He, SF6 and CHF3 is: 3/10/24/4/20. Then, under the second mixed gas, the second connection hole 19 is etched on the first body region 10, the second body region 11, and the third body region 12 below the first connection hole 18. The vertical section of the second connection hole 19 is preferably set to be circular or elliptical, as long as the bottom of the second connection hole 19 is ensured to be arc-shaped. The second mixed gas preferably has a composition of Cl2, HBr, He, O2, SF6, CHF3, and CF 4. Wherein the mixing ratio of Cl2, HBr, He, O2, SF6, CHF3 and CF4 is as follows: 4/6/14/35/3/32/40.
And step 9: as shown in fig. 9, metal is deposited and partially etched to form a first source metal 20 connected to the first body region 10, a second source metal 21 connected to the second body region 11 and a terminal metal 22 connected to the third body region 12, respectively.
As shown in fig. 8 to 9, it can be understood by those skilled in the art that the embodiment of the present invention also provides a dual-die device, which includes a substrate 1 of a first conductivity type and an epitaxial layer 2, wherein the substrate 1 is heavily doped and the epitaxial layer 2 is lightly doped. A plurality of first trenches 6 and second trenches 7 arranged at intervals are formed on two sides of the epitaxial layer 2 by etching, the width of the first trenches 6 and the width of the second trenches 7 are preferably 0.2 to 0.8 μm, and the depth of the first trenches 6 and the depth of the second trenches 7 are preferably 0.5 to 2 μm. The epitaxial layer 2 has a gate oxide layer 8 on the upper side, inside the first trench 6 and the second trench 7, the gate oxide layer inside the first trench 6 and the second trench 7 has a polysilicon 9 deposited on the outer side, the epitaxial layer 2 between the first trench 6 and the second trench 7 and the two sides of the first trench 6 and the second trench 7 has a first body region 10, a second body region 11 and a third body region 12 of the second conductive type, the first body region 10, the second body region 11 and the third body region 12 are preferably implanted with boron, and the implantation energy is: 30-90Kev, injection dosing: 5E12-3E 13. The lower end surfaces of the first body region 10 and the second body region 11 are respectively arranged on the upper sides of the lower end surfaces of the first trench 6 and the second trench 7, a first source region 13, a second source region 14 and a terminal region 15 which are heavily doped with the first conductivity type are respectively formed in the first body region 10, the second body region 11 and the third body region 12, a dielectric layer 16 is long on the upper sides of the gate oxide layer 8 and the polysilicon 9, and the thickness of the dielectric layer 16 is preferably the same as that of the dielectric layer 16Left and right. Etching away part of the first body region 10, the second body region 11 and the third bodyA region 12, a gate oxide layer 8 and a dielectric layer 16 on the upper side of the region 12 to form a connection hole, a contact region 17 with a second conductivity type heavy doping is formed in the first body region 10, the second body region 11 and the third body region 12 on the lower side of the connection hole, a first source metal 20, a second source metal 21 and a terminal metal 22 are formed on the upper side of the dielectric layer 16, and the first source metal 20, the second source metal 21 and the terminal metal 22 are respectively connected with the first body region 10, the second body region 11 and the third body region 12 through the connection hole.
The contact zone 17 is preferably arranged in a crescent. In order to make the crescent-shaped contact region 17, the connection holes of the embodiment of the present invention include a first connection hole 18 etched in the dielectric layer 16 and the gate oxide layer 8 and a second connection hole 19 etched in the first body region 10, the second body region 11 and the third body region 12, the second connection hole 19 being disposed at a lower side of the first connection hole 18. The first connection hole 18 has a rectangular cross section, and the composition and ratio of the first mixed gas can be the same as those of the prior art, and the preferred composition of the first mixed gas is Cl2, HBr, He, SF6 and CHF3 mixed gas, wherein the preferred mixing ratio of Cl2, HBr, He, SF6 and CHF3 is: 3/10/24/4/20. The vertical section of the second connection hole 19 is preferably set to be circular or elliptical, as long as the bottom of the second connection hole 19 is ensured to be arc-shaped. The second mixed gas preferably has a composition of Cl2, HBr, He, O2, SF6, CHF3, and CF 4. Wherein the mixing ratio of Cl2, HBr, He, O2, SF6, CHF3 and CF4 is as follows: 4/6/14/35/3/32/40.
When the drain electrode is pressurized, the P-body area expands and the N-epitaxial layer forms a depletion layer, and the depletion layer at the bottom of the source area and the depletion layer of the terminal area are gradually changed and cut to the terminal, so that the edge electric field of the chip is weakened, the breakdown voltage of the whole terminal structure is improved, and the reverse leakage current of the device is reduced. According to the invention, the connecting hole is manufactured in two steps, when the second mixed gas is etched, the protective film formed by the second mixed gas is thinner, the second connecting hole is further set to be circular or elliptical, after hole injection and diffusion are carried out, the formed contact area is crescent, the distribution area of the contact area is wider, the reduction of base region resistance is facilitated, the conduction of a parasitic triode is prevented, the UIS capability is improved, and the effect is obvious. Through the improvement, the breakdown voltage of the device can be improved by about 11%, and the on-resistance can be reduced by about 3.3%.
It should be noted that, taking NMOS as an example, the first conductivity type is N-type, and the second conductivity type is P-type. Taking PMOS as an example, the first conductive type is P-type, and the second conductive type is N-type.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that other parts not specifically described are within the prior art or common general knowledge to those of ordinary skill in the art. Without departing from the principle of the invention, several improvements and modifications can be made, and these improvements and modifications should also be construed as the scope of the invention.
Claims (6)
1. A double-tube core device comprises a substrate and an epitaxial layer of a first conductive type, wherein a plurality of first grooves and second grooves which are arranged at intervals are formed on two sides of the epitaxial layer in an etching mode, gate oxide layers are grown on the upper side of the epitaxial layer and the inner sides of the first grooves and the second grooves, polycrystalline silicon is deposited on the outer sides of the gate oxide layers in the first grooves and the second grooves, a first body area, a second body area and a third body area which are lightly doped with a second conductive type are formed on two sides of the first grooves and on the two sides of the second grooves and in the epitaxial layer between the first grooves and the second grooves respectively, the lower end faces of the first body area and the second body area are arranged on the upper sides of the lower end faces of the first grooves and the second grooves respectively, the double-tube core device is characterized in that a first source area, a second source area and a terminal area which are heavily doped with a first conductive type are formed in the first body area, the second body area and the third body area respectively, etching off parts of the first body region, the second body region, the third body region, the gate oxide layer and the dielectric layer on the upper side of the first body region, the second body region and the third body region to form connecting holes, forming second conductive type heavily doped contact regions in the first body region, the second body region and the third body region on the lower side of the connecting holes, forming first source metal, second source metal and terminal metal on the upper side of the dielectric layer, and respectively connecting the first source metal, the second source metal and the terminal metal with the first body region, the second body region and the third body region through the connecting holes.
2. The dual die device of claim 1, wherein the contact region is crescent shaped.
3. The dual die device of claim 2, wherein the connection holes comprise a first connection hole etched in the dielectric layer and the gate oxide layer and a second connection hole etched in a lower side of the first connection hole, the second connection hole having an elliptical vertical cross-section.
4. The dual die device of claim 1, wherein the first trench and the second trench have a depth of 0.5 to 2 μ ι η.
5. The dual die device of claim 1, wherein the dielectric layer has a thickness of
6. The dual die device of claim 1 wherein the first, second and third body regions are formed by boron implantation at an implant energy of: 30-90Kev, injection dosing: 5E12-3E 13.
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| CN201920954924.3U CN209843711U (en) | 2019-06-24 | 2019-06-24 | Double-tube-core device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211957A (en) * | 2019-06-24 | 2019-09-06 | 南京华瑞微集成电路有限公司 | A kind of dual-die device and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110211957A (en) * | 2019-06-24 | 2019-09-06 | 南京华瑞微集成电路有限公司 | A kind of dual-die device and preparation method thereof |
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