CN110036477B - 用于高性能标准单元的多过孔结构 - Google Patents

用于高性能标准单元的多过孔结构 Download PDF

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CN110036477B
CN110036477B CN201780075100.2A CN201780075100A CN110036477B CN 110036477 B CN110036477 B CN 110036477B CN 201780075100 A CN201780075100 A CN 201780075100A CN 110036477 B CN110036477 B CN 110036477B
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CN110036477A (zh
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S·萨哈
X·陈
V·宝娜帕里
H·利姆
M·马拉布里
M·古普塔
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Qualcomm Inc
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Abstract

一种IC的MOS器件，包括pMOS和nMOS晶体管。MOS器件进一步包括：第一Mx层互连，其沿第一方向延伸并且将pMOS和nMOS晶体管漏极耦合在一起；以及第二Mx层互连，其沿第一方向延伸并且将pMOS和nMOS晶体管漏极耦合在一起。第一和第二Mx层互连是平行的。MOS器件进一步包括沿与第一方向正交的第二方向延伸的第一Mx+1层互连。第一Mx+1层互连被耦合到第一Mx层互连和第二Mx层互连。MOS器件进一步包括沿第二方向延伸的第二Mx+1层互连。第二Mx+1层互连被耦合到第一Mx层互连和第二Mx层互连。第二Mx+1层互连与第一Mx+1层互连平行。

Description

用于高性能标准单元的多过孔结构
相关申请的交叉引用
本申请要求2016年12月28日提交的主题为“MULTIPLE VIA STRUCTURE FOR HIGHPERFORMANCE STANDARD CELLS(用于高性能标准单元的多过孔结构)”的美国专利申请No.15/393,180的权益，该申请通过引用明确地整体并入本文。
技术领域
本公开总体涉及标准单元架构，并且更具体地，涉及用于高性能标准单元的多过孔结构。
背景技术
标准单元器件是实现数字逻辑的集成电路(IC)。专用IC(ASIC)(诸如片上系统(SoC)器件)可以包含数千到数百万的标准单元器件。典型的IC包括顺序形成的层的堆叠。每个层可以被堆叠或覆盖在先前层上并且被图案化以形成定义晶体管(例如，场效应晶体管(FET))和/或鳍式FET(FinFET)的形状，并将晶体管连接到电路中。
在7nm节点和更小的制造工艺中，互连电阻非常高。目前存在对于改进标准单元的设计的需要，以解决较高的互连电阻。
发明内容
在本公开的一个方面，IC的金属氧化物半导体(MOS)器件包括多个p型MOS(pMOS)晶体管，每个p型MOS晶体管具有pMOS晶体管栅极、pMOS晶体管漏极和pMOS晶体管源极。每个pMOS晶体管栅极沿第一方向延伸。MOS器件进一步包括多个n型MOS(nMOS)晶体管，每个n型MOS晶体管具有nMOS晶体管栅极、nMOS晶体管漏极和nMOS晶体管源极。每个nMOS晶体管栅极沿第一方向延伸。每个nMOS晶体管栅极与对应的pMOS晶体管栅极通过沿第一方向延伸的相同的栅极互连形成。MOS器件进一步包括第一金属x(Mx)层互连，其沿第一方向延伸并且将pMOS晶体管漏极耦合到nMOS晶体管漏极。MOS器件进一步包括第二Mx层互连，其沿第一方向延伸并且将pMOS晶体管漏极耦合到nMOS晶体管漏极。第二Mx层互连与第一Mx层互连平行。MOS器件进一步包括沿与第一方向正交的第二方向延伸的第一金属x+1(Mx+1)层互连。第一Mx+1层互连被耦合到第一Mx层互连和第二Mx层互连。MOS器件进一步包括沿第二方向延伸的第二Mx+1层互连。第二Mx+1层互连被耦合到第一Mx层互连和第二Mx层互连。第二Mx+1层互连与第一Mx+1层互连平行。第一Mx+1层互连和第二Mx+1层互连是MOS器件的输出。
附图说明
图1是示出了标准单元和IC内的各种层的侧视图的第一图。
图2是示出了标准单元和IC内的各种层的侧视图的第二图。
图3是概念性地示出MOS器件的布局的平面图的图。
图4是概念性地示出示例性MOS器件的布局的平面图的图。
图5是示出示例性MOS器件的布局的平面图的图。
图6是概念性地示出标准单元中的示例性MOS器件的图。
图7是示出了示例性MOS器件的操作方法的图。
具体实施方式
以下结合附图阐述的详细描述旨在作为各种配置的描述，而不旨在表示可实践本文描述的概念的仅有配置。详细描述包括用于提供对各种概念的透彻理解的目的的具体细节。然而，对于本领域技术人员明显的是，可以在没有这些具体细节的情况下实践这些概念。在一些实例中，众所周知的结构和部件以框图形式示出，以避免模糊这些概念。装置和方法将在以下详细描述中描述，并且可以在附图中通过各种块、模块、部件、电路、步骤、工艺、算法、元件等来说明。
在7nm节点和更小的制造工艺中，互连电阻(尤其对于过孔)非常高。条形过孔(宽度约为两倍)可以降低互连电阻，但是由于预定义的金属1(M1)层、金属2(M2)层和金属3(M3)层宽度和间距，在一些标准单元中可能无法使用条形过孔。即使可以使用条形过孔，条形过孔的使用也可能需要进行其它不期望的设计改变。以下描述了在不必使用条形过孔的情况下降低互连电阻的示例MOS器件(参见图3、4、5)。
图1是示出标准单元和IC内的各种层的侧视图的第一图100。如图1中所示，晶体管具有栅极102、源极104和漏极106。源极104和漏极106可以由鳍形成。接触B(CB)层互连108(也称为金属多晶(MP)层互连)可以接触栅极102。接触A(CA)层互连110(也称为金属扩散(MD)层互连)可以接触源极104或漏极106。过孔112(称为过孔D(VD)或过孔G(VG))可以接触CA层互连110。过孔VD、VG 112在至少双重图案化工艺中由单独的掩模形成。金属0(M0)层互连114接触过孔VD/VG 112。过孔V0 116可以接触M0层互连114。
图2是示出标准单元和IC内的各种层的侧视图的第二图200。如图2中所示，晶体管具有栅极202、源极204和漏极206。源极204和漏极206可以由鳍形成。CB层互连208可以接触栅极202。CA层互连210可以接触源极204或漏极206。过孔212VD/VG可以接触CB层互连208。M0层互连214接触过孔VD/VG 212。过孔V0 216可以接触M0层互连214。
图3是概念性地示出MOS器件的布局的平面图的图300。MOS器件是具有增强的驱动强度的反相器。M0层互连302Vdd提供用于为pMOS晶体管供电的第一电压Vdd。M0层互连302Vss提供用于为nMOS晶体管供电的第二电压Vss。M0层互连302p将pMOS漏极连结在一起(例如，参见图1，利用CA层互连110和VD/VG过孔112)。M0层互连302n将nMOS漏极连结在一起(例如，参见图1，具有CA层互连110和VD/VG过孔112)。M0层互连302g将pMOS和nMOS栅极连结在一起(例如，参见图2，利用CB层互连208和VD/VG过孔212)。M0层互连302x可以与MOS器件不连接/不耦合，并且可以被包括以填充开放空间，其可以在包括MOS器件的IC的制造期间提高产量。M1层互连304是到MOS器件的输入(例如，输入引脚)并且被耦合到M0层互连302g。M1层互连306通过过孔V0耦合到M0层互连302p和M0层互连302n，以将pMOS漏极与nMOS漏极连结在一起。附加的M1层互连308通过过孔V0耦合到M0层互连302p和M0层互连302n，以将pMOS漏极和nMOS漏极连结在一起。M2层互连310通过方形过孔V1 312耦合到M1层互连306、308。通过提供穿过过孔V1 312、M1层互连306、308以及耦合到M0层互连302p、302n的过孔V0的两个并联电流路径，M1层互连306、308、M2层互连310、以及对应的过孔连接减小输出电阻。输出引脚可以是M2层互连310。在全局布线期间，M3层互连316可以通过方形过孔V2 314被耦合到M2层互连310(输出引脚)。M3层互连316可以被耦合到另一标准单元/MOS器件的输入。作为两个并联的输出电流路径的结果，MOS器件具有改善的驱动强度。
图4是概念性地示出示例性MOS器件的布局的平面图的图400。MOS器件是具有增强的驱动强度的反相器。M0层互连402Vdd提供用于为pMOS晶体管供电的第一电压Vdd。M0层互连402Vss提供用于为nMOS晶体管供电的第二电压Vss。M0层互连402p将pMOS漏极连结在一起(例如，参见图1，利用CA层互连110和VD/VG过孔112)。M0层互连402n将nMOS漏极连结在一起(例如，参见图1，利用CA层互连110和VD/VG过孔112)。M0层互连402g将pMOS和nMOS栅极连结在一起(例如，参见图2，利用CB层互连208和VD/VG过孔212)。M0层互连402x可以与MOS器件不连接/不耦合，并且可以被包括以填充开放空间，其可以在包括MOS器件的IC的制造期间提高产量。M1层互连404是到MOS器件的输入(例如，输入引脚)并且被耦合到M0层互连402g。M1层互连406通过过孔V0被耦合到M0层互连402p和M0层互连402n，以将pMOS漏极和nMOS漏极连结在一起。附加的M1层互连408通过过孔V0被耦合到M0层互连402p和M0层互连402n，以将pMOS漏极和nMOS漏极连结在一起。M2层互连410通过方形过孔V1 412被耦合到M1层互连406、408。附加的M2层互连418通过方形过孔V1 420被耦合到M1层互连406、408。通过提供穿过M2层互连410、418、过孔V1 412、420、M1层互连406、408以及耦合到M0层互连402p、402n的过孔V0的四个并联电流路径，M1层互连406、408、M2层互连410、418以及对应的过孔连接减小输出电阻。输出引脚可以是M2层互连410、418。因此，包括图4的MOS器件的标准单元可以具有两个单独的输出引脚。在全局布线期间，M3层互连416可以通过方形过孔V2 414被耦合到M2层互连410(第一输出引脚)并且通过方形过孔V2 422被耦合到M2层互连418(第二输出引脚)。M3层互连416可以被耦合到另一标准单元/MOS器件的输入。作为四个并联输出电流路径的结果，MOS器件具有改善的驱动强度。
图5是示出示例性MOS器件的布局的平面图的图500。MOS器件是具有增强的驱动强度的反相器。M0层互连502Vdd提供用于为pMOS晶体管供电的第一电压Vdd。M0层互连502Vdd通过过孔VG555和CA层互连(参见图1)被耦合到pMOS晶体管的源极。M0层互连502Vss提供用于为nMOS晶体管供电的第二电压Vss。M0层互连502Vss通过过孔VG 557和CA层互连(参见图1)被耦合到nMOS的源极。pMOS晶体管和nMOS晶体管的栅极由栅极互连592形成。虚设栅极互连(可以是浮置的)可以位于标准单元的左侧和右侧上。M0层互连502p通过过孔VD 534将pMOS漏极连结在一起(例如，参见图1，利用CA层互连110和VD/VG过孔112)。M0层互连502n通过过孔VD 538将nMOS漏极连结在一起(例如，参见图1，利用CA层互连110和VD/VG过孔112)。M0层互连502g通过过孔VD552和过孔VG 554将pMOS和nMOS栅极连结在一起(例如，参见图2，利用CB层互连208和VD/VG过孔212)。如上所述，过孔VD 534、538、552和过孔VG 554、555、557在不同的图案化工艺中利用不用的掩模形成。M0层互连502x可以与MOS器件不连接/不耦合，并且可以被包括以填充开放空间，这可以在包括MOS器件的IC的制造期间提高产量。M0切口572、574、576、578切割M0层互连502n、502x，并且M0切口582、584切割M0层互连502p、502g。在制造期间处理M0切口，因此M0层互连502x、502n被分成三个部分，其中两个部分是浮置的(在左侧和右侧上)。M0层互连502p、502g在第一图案化工艺中利用第一掩模集合形成，并且M0层互连502x、502n在第二图案化工艺中利用第二掩模集合形成。M1层互连504是到MOS器件的输入(例如，输入引脚)，并且通过过孔V0 560被耦合到M0层互连502g。M1层互连506通过过孔V0 536’、540’分别耦合到M0层互连502p以及M0层互连502n，以将pMOS漏极和nMOS漏极连结在一起。附加的M1层互连508通过过孔536”、540”分别耦合到M0层互连502p以及M0层互连502n，以将pMOS漏极和nMOS漏极连结在一起。M2层互连510通过方形过孔V1512被耦合到M1层互连506、508。附加的M2层互连518通过方形过孔V1 520被耦合到M1层互连506、508。通过提供穿过M2层互连510、518、过孔V1 512、520、M1层互连506、508以及耦合到M0层互连502p、502n的过孔V0的四个并联电流路径，M1层互连506、508、M2层互连510、518以及对应的过孔连接减小输出电阻。输出引脚可以是M2层互连510、518。因此，包括图5的MOS器件的标准单元可以具有两个单独的输出引脚。在全局布线期间，M3层互连516可以通过方形过孔V2 514被耦合到M2层互连510(第一输出引脚)，并且通过方形过孔V2 522被耦合到M2层互连518(第二输出引脚)。M3层互连516可以被耦合到另一标准单元/MOS器件的输入。作为四个并联输出电流路径的结果，MOS器件具有改善的驱动强度。
图6是概念性地示出标准单元中的示例性MOS器件的图600。如图6所示，标准单元602包括反相器604。反相器604可以是图4中和图5中概念性地示出的反相器。反相器604的输入608对应于输入引脚404、504。反相器604的输出610对应于M3层互连416、516，M3层互连416、516连接在图4和图5中概念性地示出的反相器的两个输出引脚。标准单元602可以包括其它逻辑/功能606。例如，其它逻辑/功能606可以是另一个反相器。因此，标准单元602可以实现缓冲器。由于反相器604需要比反相器606更高的驱动强度，因此图4和图5中概念性地示出的反相器可以被用于反相器604。
再次参考图4、5、6，IC的MOS器件包括多个pMOS晶体管，每个pMOS晶体管具有pMOS晶体管栅极、pMOS晶体管漏极、pMOS晶体管源极。每个pMOS晶体管栅极沿第一方向延伸。MOS器件进一步包括多个nMOS晶体管，每个nMOS晶体管具有nMOS晶体管栅极、nMOS晶体管漏极和nMOS晶体管源极。每个nMOS晶体管栅极沿第一方向延伸。每个nMOS晶体管栅极与对应的pMOS晶体管栅极通过沿第一方向延伸的相同的栅极互连592形成。MOS器件进一步包括第一Mx层互连406、506，第一Mx层互连406、506沿第一方向延伸并且将pMOS晶体管漏极耦合到nMOS晶体管漏极。MOS器件进一步包括第二Mx层互连408、508，第二Mx层互连408、508沿第一方向延伸并且将pMOS晶体管漏极耦合到nMOS晶体管漏极。第二Mx层互连408、508与第一Mx层互连406、506平行。MOS器件进一步包括沿与第一方向正交的第二方向延伸的第一Mx+1层互连410、510。第一Mx+1层互连410、510耦合到第一Mx层互连406、506和第二Mx层互连408、508。MOS器件进一步包括沿第二方向延伸的第二Mx+1层互连418、518。第二Mx+1层互连418、518耦合到第一Mx层互连406、506和第二Mx层互连408、508。第二Mx+1层互连418、518与第一Mx+1层互连410、510平行。第一Mx+1层互连410、510和第二Mx+1层互连418、518是MOS器件的输出。
在一种配置中，金属x+2(Mx+2)层互连416、516沿第一方向延伸。Mx+2层互连416、516耦合到第一Mx+1层互连410、510和第二Mx+1层互连418、518。在一种配置中，MOS器件在标准单元内并且Mx+2层互连416、516延伸到标准单元外部以与另一标准单元的输入耦合。在一种配置中，Mx+2层互连416、516利用过孔x+1层上的第一过孔x+1(Vx+1)过孔414、514耦合到第一Mx+1层互连410、510，并且利用过孔x+1层上的第二Vx+1过孔422、522耦合到第二Mx+1层互连418、518。在一种配置中，MOS器件被配置为使得输出电流通过第一Vx+1过孔414、514和第二Vx+1过孔422、522流动到Mx+2层互连416、516。
在一种配置中，第一Mx+1层互连410、510利用过孔x层上的第一过孔x(Vx)过孔412、512耦合到第一Mx层互连406、506，并且利用过孔x层上的第二Vx过孔412、512耦合到第二Mx层互连408、508。在这种配置中，第二Mx+1层互连418、518利用过孔x层上的第三Vx过孔420、520耦合到第一Mx层互连406、506，并且利用过孔x层上的第四Vx过孔520耦合到第二Mx层互连408、508。在一种配置中，MOS器件被配置为使得输出电流通过第一Vx过孔412、512和第二Vx过孔412、512流到第一Mx+1层互连410、510，并且通过第三Vx过孔420、520和第四Vx过孔420、520流到第二Mx+1层互连418、518。
在一种配置中，x是1。在一种配置中，MOS器件进一步包括第一金属x-1(Mx-1)层互连402p、502p，第一Mx-1层互连402p、502p沿第二方向延伸并将pMOS晶体管漏极耦合在一起。第一Mx层互连406、506和第二Mx层互连408、508被耦合到第一Mx-1层互连402p、502p。在这种配置中，MOS器件进一步包括第二Mx-1层互连402n、502n，第二Mx-1层互连402n、502n沿第二方向延伸并将nMOS晶体管漏极耦合在一起。第一Mx层互连406、506和第二Mx层互连408、508被耦合到第二Mx-1层互连402n、502n。在一种配置中，MOS器件进一步包括第三Mx-1层互连402g、502g，第三Mx-1层互连402g、502g沿第二方向延伸并将pMOS晶体管栅极和nMOS晶体管栅极耦合在一起。
在一种配置中，MOS器件作为反相器操作，在一种配置中，MOS器件在标准单元内，第一Mx+1层互连410、510是标准单元的第一输出引脚，并且第二Mx+1层互连418、518是标准单元的第二输出引脚。
图7是示出了示例性MOS器件的操作方法的图。如图7中所示出的，在702处，操作多个pMOS晶体管。每个pMOS晶体管具有pMOS晶体管栅极、pMOS晶体管漏极和pMOS晶体管源极。每个pMOS晶体管栅极沿第一方向延伸。在704处，操作多个nMOS晶体管。每个nMOS晶体管具有nMOS晶体管栅极、nMOS晶体管漏极和nMOS晶体管源极。每个nMOS晶体管栅极沿第一方向延伸。每个nMOS晶体管栅极与对应的pMOS晶体管栅极通过沿第一方向延伸的相同的栅极互连592形成。在706处，第一信号传播通过第一Mx层互连406、506，第一Mx层互连406、506沿第一方向延伸并且将pMOS晶体管漏极耦合到nMOS晶体管漏极。在708处，第二信号传播通过第二Mx层互连408、508，第二Mx层互连408、508沿第一方向延伸并且将pMOS晶体管漏极耦合到nMOS晶体管漏极。第二Mx层互连408、508与第一Mx层互连406、506平行。在710处，第三信号传播通过沿与第一方向正交的第二方向延伸的第一Mx+1层互连410、510。第一Mx+1层互连410、510被耦合到第一Mx层互连406、506和第二Mx层互连408、508。在712处，第四信号传播通过沿第二方向延伸的第二Mx+1层互连418、518。第二Mx+1层互连418、518被耦合到第一Mx层互连406、506和第二Mx层互连408、508。第二Mx+1层互连418、518与第一Mx+1层互连410、510平行。第一Mx+1层互连410、510和第二Mx+1层互连418、518是MOS器件的输出。
再次参照图4、5、6，IC的MOS器件包括多个pMOS晶体管，每个pMOS晶体管具有pMOS晶体管栅极、pMOS晶体管漏极和pMOS晶体管源极。每个pMOS晶体管栅极沿第一方向延伸。MOS器件进一步包括多个nMOS晶体管，每个nMOS晶体管具有nMOS晶体管栅极、nMOS晶体管漏极和nMOS晶体管源极。每个nMOS晶体管栅极沿第一方向延伸。每个nMOS晶体管栅极与对应的pMOS晶体管栅极通过沿第一方向延伸的相同的栅极互连592形成。MOS器件进一步包括第一Mx层互连406、506，第一Mx层互连406、506沿第一方向延伸并且将pMOS晶体管漏极耦合到nMOS晶体管漏极。MOS器件进一步包括第二Mx层互连408、508，第二Mx层互连408、508沿第一方向延伸并且将pMOS晶体管漏极耦合到nMOS晶体管漏极。第二Mx层互连408、508与第一Mx层互连406、506平行。MOS器件进一步包括沿与第一方向正交的第二方向延伸的第一Mx+1层互连410、510。第一Mx+1层互连410、510被耦合到第一Mx层互连406、506和第二Mx层互连408、508。MOS器件进一步包括用于传播信号的装置418、518。用于传播信号的装置418、518沿第二方向延伸。用于传播信号的装置418、518被耦合到第一Mx层互连406、506和第二Mx层互连408、508。用于传播信号的装置418、518与第一Mx+1层互连410、510平行。第一Mx+1层互连410、510和用于传播信号的装置418、518是MOS器件的输出。用于传播信号的装置418、518可以是第二Mx+1层互连418、518。
如上所述，图4、5中提供了包括反相器的标准单元，其包括来自反相器的pMOS和nMOS漏极的四个并联输出路径。四个并联输出路径降低了输出处的有效过孔互连电阻。由于无论pMOS晶体管还是nMOS晶体管都是同时操作的，因此方形过孔电阻大约减半。假设布局约束将允许使用这种条形过孔，通过使用条形过孔可以进一步减小过孔电阻。
应当理解，所公开的工艺中的步骤的特定顺序或层次是示例性方法的说明。应当理解，基于设计偏好，可以重新排列工艺中的步骤的特定顺序或层次。进一步，可以组合或省略一些步骤。所附方法权利要求以样本顺序呈现各个步骤的元件，并不意味着限于所呈现的特定顺序或层次。
提供先前的描述是为了使所属领域的技术人员能够实践本文中所描述的各种方面。对于本领域技术人员来说，对这些方面的各种修改是明显的，并且本文定义的一般原理可以应用于其他方面。因此，权利要求不旨在限于本文所示的方面，而是与符合语言权利要求的全部范围相一致，除非特别说明，其中对单数元件的引用并非旨在表示“一个且仅一个”，而是“一个或多个”。本文使用的单词“示例性”表示“用作示例、实例或说明”。本文中描述为“示例性”的任何方面不一定被解释为比其它方面优选或有利。除非另外特别说明，否则术语“一些”是指一个或多个。诸如“A、B或C中的至少一个”、“A、B和C中的至少一个”和“A、B、C或其任何组合”的组合包括A、B和/或C的任何组合，并且可以包括A的倍数、B的倍数或C的倍数。具体地，诸如“A、B或C中的至少一个”、“A、B和C中的至少一个”和“A、B、C或其任何组合”可以是仅A、仅B、仅C、A和B、A和C、B和C、或A和B和C，其中任何此类组合可以包含A、B或C中的一个或多个成员或成员。本领域普通技术人员已知或以后将知道的贯穿本公开内容所描述的各个方面的元件的所有结构和功能等同物通过引用明确地并入本文，并且旨在由权利要求书涵盖。此外，无论在权利要求中是否明确地叙述了这样的公开内容，本文所公开的内容都不旨在专用于公众。权利要求的要求元件不应被解释为装置加功能，除非使用短语“用于……的装置”明确地叙述该元件。

Claims (12)

1.一种集成电路的金属氧化物半导体MOS器件，包括：
多个pMOS晶体管，每个pMOS晶体管具有pMOS晶体管栅极、pMOS晶体管漏极和pMOS晶体管源极，每个pMOS晶体管栅极沿第一方向延伸并且由栅极互连形成；
多个nMOS晶体管，每个nMOS晶体管具有nMOS晶体管栅极、nMOS晶体管漏极和nMOS晶体管源极，每个nMOS晶体管栅极沿所述第一方向延伸并且由所述栅极互连形成；
第一金属x层互连，沿所述第一方向延伸，并且将所述pMOS晶体管漏极耦合到所述nMOS晶体管漏极；
第二金属x层互连，沿所述第一方向延伸，并且将所述pMOS晶体管漏极耦合到所述nMOS晶体管漏极，所述第二金属x层互连与所述第一金属x层互连平行；
第一金属x+1层互连，沿与所述第一方向正交的第二方向延伸，所述第一金属x+1层互连被耦合到所述第一金属x层互连和所述第二金属x层互连；以及
第二金属x+1层互连，沿所述第二方向延伸，所述第二金属x+1层互连被耦合到所述第一金属x层互连和所述第二金属x层互连，所述第二金属x+1层互连与所述第一金属x+1层互连平行，所述第一金属x+1层互连和所述第二金属x+1层互连是所述MOS器件的输出。
2.根据权利要求1所述的MOS器件，进一步包括沿所述第一方向延伸的金属x+2层互连，所述金属x+2层互连被耦合到所述第一金属x+1层互连和所述第二金属x+1层互连。
3.根据权利要求2所述的MOS器件，其中所述MOS器件在标准单元内，并且所述金属x+2层互连延伸到所述标准单元外部以与另一标准单元的输入耦合。
4.根据权利要求2所述的器件，其中所述金属x+2层互连通过过孔x+1层上的第一Vx+1过孔被耦合到所述第一金属x+1层互连，并且通过所述过孔x+1层上的第二Vx+1过孔被耦合到所述第二金属x+1层互连。
5.根据权利要求4所述的MOS器件，其中所述MOS器件被配置为使得输出电流通过所述第一Vx+1过孔和所述第二Vx+1过孔流到所述金属x+2层互连。
6.根据权利要求1所述的MOS器件，其中所述第一金属x+1层互连通过过孔x层上的第一Vx过孔被耦合到所述第一金属x层互连，并且通过所述过孔x层上的第二Vx过孔被耦合到所述第二金属x层互连，并且其中所述第二金属x+1层互连通过所述过孔x层上的第三Vx过孔被耦合到所述第一金属x层互连，并且通过所述过孔x层上的第四Vx过孔被耦合到所述第二金属x层互连。
7.根据权利要求6所述的MOS器件，其中所述MOS器件被配置为使得输出电流通过所述第一Vx过孔和所述第二Vx过孔流到所述第一金属x+1层互连，并且通过所述第三Vx过孔和所述第四Vx过孔流到所述第二金属x+1层互连。
8.根据权利要求1所述的MOS器件，其中x为1。
9.根据权利要求1所述的MOS器件，进一步包括：
第一金属x-1层互连，沿所述第二方向延伸并且将所述pMOS晶体管漏极耦合在一起，所述第一金属x层互连和所述第二金属x层互连被耦合到所述第一金属x-1层互连；以及
第二金属x-1层互连，沿所述第二方向延伸并且将所述nMOS晶体管漏极耦合在一起，所述第一金属x层互连和所述第二金属x层互连被耦合到所述第二金属x-1层互连。
10.根据权利要求9所述的MOS器件，进一步包括第三金属x-1层互连，所述第三金属x-1层互连沿所述第二方向延伸并且将所述pMOS晶体管栅极和所述nMOS晶体管栅极耦合在一起。
11.根据权利要求1所述的MOS器件，其中所述MOS器件作为反相器操作。
12.根据权利要求1所述的MOS器件，其中所述MOS器件在标准单元内，所述第一金属x+1层互连是所述标准单元的第一输出引脚，并且所述第二金属x+1层互连是所述标准单元的第二输出引脚。
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