CN110034131A - Array substrate and its manufacturing method, display panel and display device - Google Patents
Array substrate and its manufacturing method, display panel and display device Download PDFInfo
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- CN110034131A CN110034131A CN201910308991.2A CN201910308991A CN110034131A CN 110034131 A CN110034131 A CN 110034131A CN 201910308991 A CN201910308991 A CN 201910308991A CN 110034131 A CN110034131 A CN 110034131A
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- layer
- via hole
- underlay substrate
- active layer
- shielded layer
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- 239000000758 substrate Substances 0.000 title claims abstract description 148
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims description 268
- 238000000034 method Methods 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 239000010936 titanium Substances 0.000 claims description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 239000011733 molybdenum Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000011651 chromium Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- -1 grid Substances 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 14
- 239000010409 thin film Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 238000002161 passivation Methods 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 239000000956 alloy Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the invention provides a kind of array substrates, comprising: underlay substrate and the active layer being successively set on underlay substrate, grid, source electrode and drain electrode, further include shielded layer, between underlay substrate and active layer.The outer profile in orthographic projection region of the shielded layer on underlay substrate is greater than the outer profile in orthographic projection region of the active layer on underlay substrate.And shielded layer is provided with the first via hole, the position that the position of the first via hole is contacted with source electrode with active layer is corresponding；And/or shielded layer is provided with the second via hole, the position that the position of the second via hole is contacted with drain electrode with active layer is corresponding.The embodiment of the invention also discloses the manufacturing methods of a kind of display panel, display device and array substrate.Since the outer profile of the shielded layer of the embodiment of the present invention is greater than the outer profile of active layer, the occlusion effect of shielded layer is enhanced.Meanwhile shielded layer is provided with the first via hole and/or the second via hole, so as to avoid the generation of parasitic capacitance between source, drain electrode and shielded layer.
Description
Technical field
The present invention relates to field of display technology, specially array substrate and its manufacturing method, display panel and display device.
Background technique
Conventional display panels include the array substrate being oppositely arranged and color membrane substrates, and array substrate includes multiple film crystals
Pipe, when the active layer that thin film transistor (TFT) includes is by illumination, characteristic is easy to happen drift, influences the normal of thin film transistor (TFT)
It uses.Environment light is directly or indirectly irradiated to active layer in order to prevent, and a shielded layer usually is arranged in the lower section of active layer, uses
In the irradiation for blocking environment light.
Inventors have found that the position that shielded layer is blocked at present is only corresponding with the position of the channel region of active layer, and not
The region of entire active layer is blocked, so that active layer is easy the irradiation by environment light, to influence thin film transistor (TFT)
Characteristic.
Summary of the invention
In view of this, the present invention provides a kind of array substrate and its manufacturing method, display panel and display device, solve existing
There is active layer existing for technology to be easy the irradiation by environment light, thus the technical issues of influencing the characteristic of thin film transistor (TFT).
To solve the above-mentioned problems, the embodiment of the present invention mainly provides the following technical solutions:
In the first aspect, the embodiment of the invention discloses a kind of array substrates, comprising: underlay substrate and sets gradually
Active layer, grid on the underlay substrate, source electrode and drain electrode further include shielded layer, are located at the underlay substrate and described
Between active layer；
The outer profile in orthographic projection region of the shielded layer on the underlay substrate is greater than the active layer in the lining
The outer profile in the orthographic projection region on substrate；And
The shielded layer is provided with the first via hole, and the position of first via hole is contacted with the source electrode with the active layer
Position it is corresponding；And/or
The shielded layer is provided with the second via hole, and the position of second via hole is contacted with the drain electrode with the active layer
Position it is corresponding.
Optionally, the area in orthographic projection region of the shielded layer on the underlay substrate is greater than the active layer in institute
State the area in the orthographic projection region on underlay substrate.
Optionally, the outer profile in orthographic projection region of first via hole on the underlay substrate is greater than or equal to source electrode
The outer profile in orthographic projection region of the via hole on the underlay substrate；
The outer profile in orthographic projection region of second via hole on the underlay substrate is greater than or equal to drain via and exists
The outer profile in the orthographic projection region on the underlay substrate.
Optionally, frontal projected area of first via hole on the underlay substrate is greater than or equal to the source electrode and institute
State frontal projected area of the region of active layer contact on the underlay substrate.
Optionally, frontal projected area of second via hole on the underlay substrate is greater than or equal to the drain electrode and institute
State frontal projected area of the region of active layer contact on the underlay substrate.
Optionally, frontal projected area of first via hole on the underlay substrate is equal to second via hole described
Frontal projected area on underlay substrate.
Optionally, further include public electrode wire, the public electrode wire is located on the same floor with the shielded layer, and with it is described
Shielded layer electrical connection.
Optionally, the public electrode wire is structure as a whole with the shielded layer.
Optionally, further includes: public electrode wire, and the insulating layer between the active layer and the shielded layer,
Gate insulating layer between the active layer and the grid；
The public electrode wire is located on the same floor with the grid, and by running through the insulating layer and the gate insulator
The third via hole of layer is electrically connected with the shielded layer.
Optionally, the material of the shielded layer is at least one of copper, aluminium, molybdenum, titanium, chromium and tungsten.
In second aspect, the embodiment of the invention discloses a kind of display panels, including array base described in first aspect
Plate.
In a third aspect, the embodiment of the invention discloses a kind of display devices, including display surface described in second aspect
Plate.
In fourth aspect, the embodiment of the invention discloses a kind of manufacturing methods of array substrate, including active layer, grid
The production of pole, source electrode and drain electrode, further includes:
Shielded layer, orthographic projection of the shielded layer on the underlay substrate are made on underlay substrate by patterning processes
The outer profile in region is greater than the outer profile in orthographic projection region of the active layer on the underlay substrate；
The first via hole and/or the second via hole, the position of first via hole and the source electrode are made on the shielded layer
The position contacted with the active layer is corresponding, the position that the position of second via hole is contacted with the drain electrode with the active layer
It is corresponding.
Optionally, after the first via hole and/or the second via hole are made on the shielded layer, this method is specifically included:
Insulating layer is made on the shielded layer；
On the insulating layer by patterning processes successively make active layer, gate insulating layer, grid, interlayer insulating film,
Source electrode and drain electrode.
Optionally, this method further includes the production of public electrode wire, the public electrode wire and the shielded layer using same
One time patterning processes make to be formed；
Or, the public electrode wire uses to make with a patterning processes with the grid to be formed.
By above-mentioned technical proposal, technical solution provided in an embodiment of the present invention is at least had the advantage that
The foreign steamer in orthographic projection region of the shielded layer for including due to the array substrate of the embodiment of the present invention on underlay substrate
Exterior feature is greater than the outer profile in orthographic projection region of the active layer on underlay substrate, and therefore, shielded layer can be to the area of entire active layer
Domain is blocked, and avoids active layer by the irradiation of environment light, and then improves the characteristic of thin film transistor (TFT)；In addition, due to this hair
Shielded layer is provided with the first via hole in bright embodiment, and the position that the position of the first via hole is contacted with source electrode with active layer is corresponding, this
Sample can reduce the parasitic capacitance between the source electrode and shielded layer at active layer contact position；And shielded layer is provided with
Two via holes, the position that the position of the second via hole is contacted with drain electrode with active layer is corresponding, can reduce contact position with active layer in this way
The parasitic capacitance between the drain electrode at place and shielded layer is set, the performance of array substrate is improved.
Above description is only the general introduction of technical solution of the embodiment of the present invention, in order to better understand the embodiment of the present invention
Technological means, and can be implemented in accordance with the contents of the specification, and in order to allow above and other mesh of the embodiment of the present invention
, feature and advantage can be more clearly understood, the special specific embodiment for lifting the embodiment of the present invention below.
Detailed description of the invention
By reading the detailed description of hereafter optional embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.Attached drawing is only used for showing the purpose of optional embodiment, and is not considered as to the present invention
The limitation of embodiment.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 is the structural schematic diagram of prior art array substrate；
Fig. 2 is the sectional view in Fig. 1 along A-A ' line；
Fig. 3 is the structural schematic diagram of the first embodiment of the array substrate of the embodiment of the present invention；
Fig. 4 is the sectional view in Fig. 3 along A-A ' line；
Fig. 5 is the structural schematic diagram of the second embodiment of the array substrate of the embodiment of the present invention；
Fig. 6 is the sectional view in Fig. 5 along A-A ' line；
Fig. 7 is the sectional view in Fig. 5 along B-B ' line；
Fig. 8 is the sectional view in Fig. 5 along C-C ' line；
Fig. 9 is the structural schematic diagram of the 3rd embodiment of the array substrate of the embodiment of the present invention；
Figure 10 is the sectional view in Fig. 9 along A-A ' line；
Figure 11 is the sectional view in Fig. 9 along B-B ' line；
Figure 12 is the sectional view in Fig. 9 along C-C ' line；
Figure 13 is the flow chart of the manufacturing method of the array substrate of the embodiment of the present invention.
Appended drawing reference is described below:
1- underlay substrate；2- shielded layer；3- insulating layer；4- active layer；5- gate insulating layer；6- grid；7- layer insulation
Layer；8- source electrode；9- drain electrode；
10- passivation layer；11- pixel electrode；12- data line；13- grid line；14- public electrode wire；The first via hole of 15-；16-
Second via hole；17- via hole；171- third via hole；18- public electrode；19- second insulating layer.
Specific embodiment
Exemplary embodiments of the present disclosure are described in more detail below with reference to accompanying drawings.Although showing the disclosure in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is limited.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
It is fully disclosed to those skilled in the art.
Those skilled in the art of the present technique are appreciated that unless expressly stated, singular " one " used herein, " one
It is a ", " described " and "the" may also comprise plural form.It is to be further understood that being arranged used in the description of the present application
Diction " comprising " refer to that there are the feature, integer, step, operation, element and/or component, but it is not excluded that in the presence of or addition
Other one or more features, integer, step, operation, element, component and/or their group.It should be understood that when we claim member
When part is "connected" to another element, it can be directly connected to other elements, or there may also be intermediary elements.In addition,
" connection " used herein may include being wirelessly connected.Wording "and/or" used herein includes one or more associated
The whole for listing item or any cell and all combination.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, all terms used herein (including technology art
Language and scientific term), there is meaning identical with the general understanding of those of ordinary skill in the application fields.Should also
Understand, those terms such as defined in the general dictionary, it should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless idealization or meaning too formal otherwise will not be used by specific definitions as here
To explain.
Inventor studies the structure for the thin film transistor (TFT) that array substrate in the prior art includes, such as Fig. 1 and Fig. 2
Shown, Fig. 1 is prior art array substrate plane structure chart, and Fig. 2 is the sectional view in Fig. 1 along A-A ' line, on underlay substrate 1 according to
It is secondary be provided with shielded layer 2, insulating layer 3, active layer 4, gate insulating layer 5, grid 6, interlayer insulating film 7, source electrode 8, drain electrode 9, it is blunt
Change layer 10, pixel electrode 11, wherein data line 12 is located on the same floor with source electrode 8, and is connect with source electrode 8；Grid line 13 and grid 6
It is located on the same floor, and is connect with grid 6.
Inventors have found that if the area in orthographic projection region of the shielded layer 2 on underlay substrate 1 is greater than or waits in the prior art
When area of the active layer 4 in the orthographic projection region on underlay substrate 1, position and shielded layer 2 that source electrode 8 is contacted with active layer 4
Between distance it is close, parasitic capacitance between the two is bigger, similarly, the position and shielded layer that drain electrode 9 is contacted with active layer 4
Distance is close between 2, and parasitic capacitance between the two is also bigger, this will affect the performance of array substrate.
Therefore, still, such to set inventors have found that the shielded layer 2 of the prior art only blocks the channel region of active layer 4
Meter mode can make shielded layer 2 that can not block to the region of entire active layer 4, so that active layer 4 is easy by environment light
Irradiation, to influence the characteristic of thin film transistor (TFT).
In order to solve above-mentioned technical problem of the existing technology, the embodiment of the invention provides a kind of new array substrates
Structure.
The embodiment of the invention provides a kind of array substrates, and as shown in Figures 3 to 12, which includes: substrate base
Plate 1 and the active layer 4 being successively set on underlay substrate 1, grid 6, source electrode 8 and drain electrode 9, the array substrate further include shielding
Layer 2, between underlay substrate 1 and active layer 4.The outer profile in orthographic projection region of the shielded layer 2 on underlay substrate 1, which is greater than, to be had
The outer profile in orthographic projection region of the active layer 4 on underlay substrate 1.Shielded layer 2 is provided with the first via hole 15, the position of the first via hole 15
It is corresponding to set the position contacted with source electrode 8 with active layer 4；And/or shielded layer 2 is provided with the second via hole 16, the position of the second via hole 16
It is corresponding to set the position contacted with drain electrode 9 with active layer 4.
Orthographic projection region of the shielded layer 2 for including due to the array substrate of the embodiment of the present invention on underlay substrate 1 it is outer
Profile is greater than the outer profile in orthographic projection region of the active layer 4 on underlay substrate 1, and therefore, shielded layer 2 can be to entire active layer
4 region is blocked, and avoids active layer 4 by the irradiation of environment light, and then improves the characteristic of thin film transistor (TFT)；In addition, by
Shielded layer 2 is provided with the first via hole 15 in the embodiment of the present invention, and the position of the first via hole 15 is contacted with source electrode 8 with active layer 4
Position it is corresponding, can reduce the parasitic capacitance between the source electrode 8 and shielded layer 2 at 4 contact position of active layer in this way；With
And shielded layer 2 is provided with the second via hole 16, the position that the position of the second via hole 16 is contacted with drain electrode 9 with active layer 4 is corresponding, this
Sample can reduce with the drain electrode 9 at 4 contact position of active layer and the parasitic capacitance between shielded layer 2, improve the property of array substrate
Energy.
Array substrate provided in an embodiment of the present invention is discussed in detail below by several specific embodiments.
Fig. 3 and Fig. 4 shows the structural schematic diagram of the first embodiment of the array substrate of the embodiment of the present invention, and Fig. 3 is this
The plane structure chart of invention first embodiment, Fig. 4 are the sectional view in Fig. 3 along A-A ' line.
As shown in Figure 3 and Figure 4, array substrate, comprising: underlay substrate 1 and be successively set on having on underlay substrate 1
Active layer 4, grid 6, source electrode 8 and drain electrode 9, further include shielded layer 2, between underlay substrate 1 and active layer 4.Shielded layer 2 is serving as a contrast
The outer profile in the orthographic projection region on substrate 1 is greater than the outer profile in orthographic projection region of the active layer 4 on underlay substrate 1.Screen
It covers layer 2 and is provided with the first via hole 15, the position that the position of the first via hole 15 is contacted with source electrode 8 with active layer 4 is corresponding.
In general, the signal intensity frequency on data line 12 is very high, when data line 12 is connected to source electrode 8, source electrode 8 and active layer 4
Distance is close between the position and shielded layer 2 of contact, and parasitic capacitance between the two is larger, influences the biography of 12 signal of data line
It is defeated, cause data line signal distorting transformation.And the embodiment of the present invention is at the position that source electrode 8 is contacted with active layer 4, shielded layer 2
It is provided with the first via hole 15, thus reduce the parasitic capacitance between the source electrode 8 and shielded layer 2 at 4 contact position of active layer,
Reduce the load of data line 12.
Optionally, area of the shielded layer 2 in the orthographic projection region on underlay substrate 1 is greater than active layer 4 on underlay substrate 1
Orthographic projection region area；In this way, shielded layer 2 is enabled to shelter from active layer 4 completely, occlusion effect is promoted, further
Active layer 4 is avoided to be improved the characteristic of thin film transistor (TFT) by the irradiation of environment light.
Optionally, it in general, before making source electrode, needs to make the source electrode mistake for running through gate insulating layer 5 and interlayer insulating film 7
Hole, so that source electrode can be electrically connected by the source electrode via hole with active layer 4 after production source electrode.In order to realize the skill of the present embodiment
Art effect, the outer profile in orthographic projection region of first via hole 15 on underlay substrate 1 are greater than or equal to source electrode via hole in substrate base
The outer profile in the orthographic projection region on plate 1.
Optionally, frontal projected area of first via hole 15 on underlay substrate 1 is greater than or equal to source electrode 8 and connects with active layer 4
Frontal projected area of the region of touching on underlay substrate 1；In this way, can not be generated at the position for contacting source electrode 8 with active layer 4
Parasitic capacitance further decreases the influence that parasitic capacitance transmits data line signal.
Fig. 5 to Fig. 8 shows the structural schematic diagram of the second embodiment of the array substrate of the embodiment of the present invention, and Fig. 5 is this
The plane structure chart of invention second embodiment, Fig. 6 are the sectional view in Fig. 5 along A-A ' line, and Fig. 7 is cuing open along B-B ' line in Fig. 5
Face figure, Fig. 8 are the sectional view in Fig. 5 along C-C ' line.
As shown in Figure 5 and Figure 6, array substrate, comprising: underlay substrate 1 and be successively set on having on underlay substrate 1
Active layer 4, grid 6, source electrode 8 and drain electrode 9, further include shielded layer 2, between underlay substrate 1 and active layer 4.Shielded layer 2 is serving as a contrast
The outer profile in the orthographic projection region on substrate 1 is greater than the outer profile in orthographic projection region of the active layer 4 on underlay substrate 1.Screen
It covers layer 2 and is provided with the first via hole 15, the position that the position of the first via hole 15 is contacted with source electrode 8 with active layer 4 is corresponding.
As shown in Fig. 5, Fig. 7 and Fig. 8, which further includes public electrode wire 14, public electrode wire 14 and shielded layer 2
It is located on the same floor, and is electrically connected with shielded layer 2.Since public electrode wire 14 is electrically connected with shielded layer 2, accumulated on shielded layer 2
Electrostatic charge can be dispersed by public electrode wire 14, and the electrostatic charge accumulated on shielded layer 2 can be prevented to thin film transistor (TFT)
Characteristic have an impact.
Optionally, public electrode wire 14 is structure as a whole with shielded layer 2, can reduce manufacture difficulty, promotes market competition
Power.
Fig. 9 to Figure 12 respectively illustrates the structural schematic diagram of the 3rd embodiment of the array substrate of the embodiment of the present invention, Fig. 9
For the plane structure chart of third embodiment of the invention, Figure 10 is the sectional view in Fig. 9 along A-A ' line, and Figure 11 is in Fig. 9 along B-B '
The sectional view of line, Figure 12 are the sectional view in Fig. 9 along C-C ' line.
As shown in Figure 9 and Figure 10, array substrate, comprising: underlay substrate 1 and be successively set on underlay substrate 1
Active layer 4, grid 6, source electrode 8 and drain electrode 9, further include shielded layer 2, between underlay substrate 1 and active layer 4.Shielded layer 2 exists
The outer profile in the orthographic projection region on underlay substrate 1 is greater than the outer profile in orthographic projection region of the active layer 4 on underlay substrate 1.
Shielded layer 4 is provided with the first via hole 15, and the position that the position of the first via hole 15 is contacted with source electrode 8 with active layer 4 is corresponding, and shields
Layer 2 is provided with the second via hole 16, and the position that the position of the second via hole 16 is contacted with drain electrode 9 with active layer 4 is corresponding.
Optionally, the second via hole 16 1 frontal projected area on underlay substrate is greater than or equal to drain electrode 9 and connects with active layer 4
Frontal projected area of the region of touching on underlay substrate 1；In this way, can not be generated at the position for contacting drain electrode 9 with active layer 4
Parasitic capacitance further decreases the influence that parasitic capacitance transmits data line signal.
Optionally, it in general, before making source electrode, needs to make the source electrode mistake for running through gate insulating layer 5 and interlayer insulating film 7
Hole, so that source electrode can be electrically connected by the source electrode via hole with active layer 4 after production source electrode.In order to realize the skill of the present embodiment
Art effect, the outer profile in orthographic projection region of first via hole 15 on underlay substrate 1 are greater than or equal to source electrode via hole in substrate base
The outer profile in the orthographic projection region on plate 1.
Similarly, it in general, before production drain electrode, needs to make the drain electrode for running through gate insulating layer 5 and interlayer insulating film 7
Hole, so that drain electrode can be electrically connected by the drain via with active layer 4 after production drain electrode.In order to realize the skill of the present embodiment
Art effect, the outer profile in orthographic projection region of second via hole 16 on underlay substrate 1 are greater than or equal to drain via in substrate base
The outer profile in the orthographic projection region on plate 1.
Optionally, the first via hole 15 1 frontal projected area on underlay substrate is equal to the second via hole 16 on underlay substrate 1
Frontal projected area.The frontal projected area of first via hole 15 and the second via hole 16 is equal, manufacture difficulty and cost can be reduced,
Improve the market competitiveness.
As shown in Fig. 9, Figure 11 and Figure 12, which further includes public electrode wire 14, and is located at active layer 4 and screen
The insulating layer 3 between layer 2 is covered, the gate insulating layer 5 between active layer 4 and grid 6；Public electrode wire 14 with grid 6
In same layer, and by being electrically connected through the third via hole 171 of insulating layer 3 and gate insulating layer 5 with shielded layer 2.Due to public
Electrode wires 14 are electrically connected with shielded layer 2, and the electrostatic charge accumulated on shielded layer 2 can be dispersed by public electrode wire 14, can
To prevent the electrostatic charge accumulated on shielded layer 2 from having an impact to the characteristic of thin film transistor (TFT).
Specifically, as shown in Fig. 4, Fig. 6, Fig. 7, Fig. 8, Figure 10, Figure 11, Figure 12, the array substrate further include: be located at grid
Interlayer insulating film 7 on 6, the pixel electrode 11 on passivation layer 10, is located at the passivation layer 10 on interlayer insulating film 7
Second insulating layer 19 on pixel electrode 11, the public electrode 18 in second insulating layer 19.
As shown in fig. 7, public electrode 18 pass through it is exhausted through second insulating layer 19, passivation layer 10, interlayer insulating film 7, grid
The via hole of edge layer 5 and insulating layer 3 is connect with public electrode wire 14.As shown in figure 11, public electrode 18 passes through through the second insulation
The via hole of layer 19, passivation layer 10 and interlayer insulating film 7 is connect with public electrode wire 14.
Optionally, the material of shielded layer 2 be copper (Cu), aluminium (Al), molybdenum (Mo), titanium (Ti), in chromium (Cr) and tungsten (W) extremely
Few one kind.Specifically, one of copper, aluminium, molybdenum, titanium, chromium and tungsten can be selected, the alloy material of these materials can also be selected
Material, shielded layer 2 can be single-layer metal structure, be also possible to multi-layer metal structure, such as: can be golden using the multilayer of molybdenum, aluminium, molybdenum
Belong to, the multiple layer metal of titanium, copper, titanium can also be used, the multiple layer metal of molybdenum, titanium, copper can also be used.
It is similar with the material of shielded layer 2 in the embodiment of the present invention, grid 6, source electrode 8, drain electrode 9 can using copper, aluminium, molybdenum,
At least one of titanium, chromium and tungsten can also use the alloy material of these materials.Grid 6, source electrode 8, drain electrode 9 can use
Single-layer metal structure can also use multi-layer metal structure.
In the embodiment of the present invention, active layer 4 can be amorphous silicon, polysilicon, oxide material.
In the embodiment of the present invention, pixel electrode 11 and public electrode 18 can use tin indium oxide (ITO) or indium zinc oxide
(IZO)。
In the embodiment of the present invention, gate insulating layer 5 can use silicon nitride or silica.Gate insulating layer 5 can be list
Layer structure, is also possible to multilayered structure, such as: using the double-layer structure of silicon nitride and silica.
In the embodiment of the present invention, interlayer insulating film 7 can use silicon nitride or silica.Interlayer insulating film 7 can be list
Layer structure, is also possible to multilayered structure.
In the embodiment of the present invention, passivation layer 10 can use silicon nitride or silica.Passivation layer 10 can be single layer structure,
It is also possible to multilayered structure.
In the embodiment of the present invention, insulating layer 3 and second insulating layer 19 can use silicon nitride or silica.First insulating layer
3 and second insulating layer 19 can be single layer structure, be also possible to multilayered structure.
Based on the same inventive concept, the embodiment of the invention also discloses a kind of display panels, including above-mentioned array substrate.
Since display panel includes above-mentioned array substrate, so that display panel has beneficial effect identical with array substrate.Cause
This, the beneficial effect of it is no longer repeated herein display panel.
Based on the same inventive concept, the embodiment of the invention also discloses a kind of display devices, including above-mentioned display panel.
Since display device includes above-mentioned display panel, so that display device has beneficial effect identical with display panel.Cause
This, the beneficial effect for display device that it is no longer repeated herein.
Based on the same inventive concept, the embodiment of the invention also discloses a kind of manufacturing method of array substrate, including it is active
The production of layer, grid, source electrode and drain electrode.Also, as shown in figure 13, the manufacturing method of array substrate further include:
S101: shielded layer, forward projection region of the shielded layer on underlay substrate are made on underlay substrate by patterning processes
The outer profile in domain is greater than the outer profile in orthographic projection region of the active layer on underlay substrate.
S102: the first via hole and/or the second via hole, the position of the first via hole and source electrode and active layer are made on the shielding layer
The position of contact is corresponding, and the position that the position of the second via hole is contacted with drain electrode with active layer is corresponding.
Optionally, the embodiment of the present invention specifically includes after above-mentioned S102:
Insulating layer is made on the shielding layer.
Active layer, gate insulating layer, grid, interlayer insulating film, source electrode are successively made by patterning processes on the insulating layer
And drain electrode.Active layer of the embodiment of the present invention, gate insulating layer, grid, interlayer insulating film, source electrode and drain electrode specific production method
Similarly to the prior art, which is not described herein again.
Optionally, the manufacturing method of array substrate of the embodiment of the present invention further includes the production of public electrode wire, specifically, public
Common-battery polar curve uses to make with a patterning processes with shielded layer to be formed.Alternatively, public electrode wire and grid are used with a structure
Figure technique makes to be formed.
Include: using beneficial effect obtained of the embodiment of the present invention
1, orthographic projection region of the shielded layer for including due to the array substrate of the embodiment of the present invention on underlay substrate is outer
Profile is greater than the outer profile in orthographic projection region of the active layer on underlay substrate, and therefore, shielded layer can be to entire active layer
Region is blocked, and avoids active layer by the irradiation of environment light, and then improves the characteristic of thin film transistor (TFT)；In addition, due to this
In inventive embodiments at the position that source electrode is contacted with active layer, shielded layer is provided with the first via hole, can reduce and has in this way
The parasitic capacitance between source electrode and shielded layer at active layer contact position；And at the position that drain electrode is contacted with active layer, screen
It covers layer and is provided with the second via hole, can reduce the parasitism electricity with the drain electrode at active layer contact position and between shielded layer in this way
Hold, improves the performance of array substrate.
2, the region that frontal projected area of first via hole on underlay substrate is greater than or equal to that source electrode is contacted with active layer exists
Frontal projected area on underlay substrate；In this way, parasitic capacitance can not be generated at the position for contacting source electrode with active layer, into one
Step reduces the influence that parasitic capacitance transmits data line signal.
3, it is electrically connected due to public electrode wire with shielded layer, the electrostatic charge accumulated on shielded layer can pass through public electrode wire
Dispersed, can prevent the electrostatic charge accumulated on shielded layer from having an impact to the characteristic of thin film transistor (TFT).
The above is only some embodiments of the invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of array substrate, comprising: underlay substrate and the active layer being successively set on the underlay substrate, grid, source
Pole and drain electrode, which is characterized in that further include shielded layer, between the underlay substrate and the active layer；
The outer profile in orthographic projection region of the shielded layer on the underlay substrate is greater than the active layer in the substrate base
The outer profile in the orthographic projection region on plate；And
The shielded layer is provided with the first via hole, the position that the position of first via hole is contacted with the source electrode with the active layer
Set correspondence；And/or
The shielded layer is provided with the second via hole, the position that the position of second via hole is contacted with the drain electrode with the active layer
Set correspondence.
2. array substrate as described in claim 1, which is characterized in that orthographic projection of the shielded layer on the underlay substrate
The area in region is greater than the area in orthographic projection region of the active layer on the underlay substrate.
3. array substrate as described in claim 1, which is characterized in that positive throwing of first via hole on the underlay substrate
The outer profile in shadow zone domain is greater than or equal to the outer profile in orthographic projection region of the source electrode via hole on the underlay substrate；
The outer profile in orthographic projection region of second via hole on the underlay substrate is greater than or equal to drain via described
The outer profile in the orthographic projection region on underlay substrate.
4. array substrate as described in claim 1, which is characterized in that positive throwing of first via hole on the underlay substrate
Shadow area is greater than or equal to frontal projected area of the region that contacts with the active layer of the source electrode on the underlay substrate.
5. array substrate as described in claim 1, which is characterized in that positive throwing of second via hole on the underlay substrate
Shadow area is greater than or equal to the frontal projected area of the region contacted with the active layer on the underlay substrate that drain.
6. array substrate as described in claim 1, which is characterized in that positive throwing of first via hole on the underlay substrate
Shadow area is equal to frontal projected area of second via hole on the underlay substrate.
7. array substrate as claimed in any one of claims 1 to 6, which is characterized in that it further include public electrode wire, it is described public
Electrode wires are located on the same floor with the shielded layer, and are electrically connected with the shielded layer.
8. array substrate as claimed in claim 7, which is characterized in that the public electrode wire and the shielded layer are integrated knot
Structure.
9. array substrate as described in claim 1, which is characterized in that further include: public electrode wire, and be located at described active
Insulating layer between layer and the shielded layer, the gate insulating layer between the active layer and the grid；
The public electrode wire is located on the same floor with the grid, and by through the insulating layer and the gate insulating layer
Third via hole is electrically connected with the shielded layer.
10. array substrate as described in claim 1, which is characterized in that the material of the shielded layer is copper, aluminium, molybdenum, titanium, chromium
At least one of with tungsten.
11. a kind of display panel, which is characterized in that including such as described in any item array substrates of claim 1-10.
12. a kind of display device, which is characterized in that including display panel as claimed in claim 11.
13. a kind of manufacturing method of array substrate, the production including active layer, grid, source electrode and drain electrode, which is characterized in that also
Include:
Shielded layer, orthographic projection region of the shielded layer on the underlay substrate are made on underlay substrate by patterning processes
Outer profile be greater than orthographic projection region of the active layer on the underlay substrate outer profile；
The first via hole and/or the second via hole, the position of first via hole and the source electrode and institute are made on the shielded layer
The position for stating active layer contact is corresponding, the position pair that the position of second via hole is contacted with the drain electrode with the active layer
It answers.
14. manufacturing method as claimed in claim 13, which is characterized in that made on the shielded layer the first via hole and/or
After second via hole, specifically include:
Insulating layer is made on the shielded layer；
Active layer, gate insulating layer, grid, interlayer insulating film, source electrode are successively made by patterning processes on the insulating layer
And drain electrode.
15. manufacturing method as claimed in claim 14, which is characterized in that it further include the production of public electrode wire, it is described public
Electrode wires use to make with a patterning processes with the shielded layer to be formed；
Or, the public electrode wire uses to make with a patterning processes with the grid to be formed.
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