CN109166864A - Array substrate and its manufacturing method, display panel - Google Patents
Array substrate and its manufacturing method, display panel Download PDFInfo
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- CN109166864A CN109166864A CN201810895821.4A CN201810895821A CN109166864A CN 109166864 A CN109166864 A CN 109166864A CN 201810895821 A CN201810895821 A CN 201810895821A CN 109166864 A CN109166864 A CN 109166864A
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- 239000000758 substrate Substances 0.000 title claims abstract description 64
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- 230000004888 barrier function Effects 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 40
- 230000003287 optical effect Effects 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims description 41
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 239000003990 capacitor Substances 0.000 claims description 10
- 239000004925 Acrylic resin Substances 0.000 claims description 3
- 229920000178 Acrylic resin Polymers 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims 1
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- 238000005286 illumination Methods 0.000 abstract description 6
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- 238000011161 development Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910017464 nitrogen compound Inorganic materials 0.000 description 2
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
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- 239000010409 thin film Substances 0.000 description 2
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- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910000423 chromium oxide Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
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- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/81—Anodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
Abstract
The application discloses a kind of array substrate and its manufacturing method, display panel.The application designs source electrode pattern and drain pattern is formed directly on etching barrier layer; replace traditional flatness layer and passivation layer by etching barrier layer; and drain pattern is simultaneously also as the anode pattern of OLED device; so as to reduce optical cover process; and etching barrier layer is made using light screening material; the channel layer of TFT can be protected not by illumination effect, it is advantageously ensured that its performance is stablized.
Description
Technical field
This application involves display fields, and in particular to a kind of array substrate and its manufacturing method, display panel.
Background technique
Currently, with metal oxide (Oxide) semiconductor come prepare channel layer TFT (Thin Film Transistor,
Thin film transistor (TFT)), it is widely used to OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display
In panel.But light shield (Mask) processing procedure needed for preparing the array substrate (Array substrate) of the type TFT is more, causes to make
It is various to make process, can not reduce production cost, also, channel layer is easy by illumination effect and performance is unstable.
Summary of the invention
In view of this, the application provides a kind of array substrate and its manufacturing method, display panel, light shield system can be reduced
Journey, and advantageously reduce influence of the illumination to the channel layer of TFT.
The manufacturing method of the array substrate of one embodiment of the application, comprising:
One underlay substrate is provided；
First grid pattern and insulating layer are sequentially formed on the underlay substrate；
It is formed on the insulating layer the semiconductor pattern being located above the first grid pattern；
The etching barrier layer for covering the insulating layer is formed on the semiconductor pattern, the etching barrier layer is using screening
Luminescent material is made, and the etching barrier layer offer the source contact area of the exposure semiconductor pattern the first contact hole and
Second contact hole of drain contact region；
Source electrode pattern and drain pattern are formed on the etching barrier layer, and the source electrode pattern is in first contact hole
The interior source contact area with the semiconductor pattern contacts, the drain pattern in second contact hole with the semiconductor
The drain contact region of pattern contacts；
Pixel defining layer is formed on the source electrode pattern and drain pattern, the pixel defining layer is equipped with for limiting
State the luminous zone of array substrate；
Luminescent layer and cathode pattern in drain pattern are sequentially formed in the luminous zone.
The array substrate of one embodiment of the application, comprising:
Underlay substrate；
First grid pattern and the insulating layer being sequentially formed on the underlay substrate；
It is formed in the semiconductor pattern on the insulating layer and being located above the first grid pattern；
It is formed on the semiconductor pattern and the etching barrier layer of the covering insulating layer, the etching barrier layer uses
Light screening material is made, and the etching barrier layer offers the first contact hole of the source contact area of the exposure semiconductor pattern
With the second contact hole of drain contact region；
Source electrode pattern and the drain pattern being formed on the etching barrier layer, the source electrode pattern is in first contact
It is contacted in hole with the source contact area of the semiconductor pattern, the drain pattern is partly led in second contact hole with described
The drain contact region of body pattern contacts；
The pixel defining layer being formed in the source electrode pattern and drain pattern, the pixel defining layer are equipped with for limiting
The luminous zone of the array substrate；
The luminescent layer and cathode pattern for being sequentially formed in the luminous zone and being located in drain pattern.
The display panel of one embodiment of the application, including above-mentioned array substrate.
The utility model has the advantages that the application designs source electrode pattern and drain pattern is formed directly on etching barrier layer, pass through etching
Barrier layer replaces traditional flatness layer and passivation layer, and drain pattern is also used as anode pattern simultaneously, so as to reduce light shield
Processing procedure, and etching barrier layer is made using light screening material, and the channel layer of TFT can be protected not by illumination effect, be conducive to
Ensure that its performance is stablized.
Detailed description of the invention
Fig. 1 is the flow diagram of one embodiment of manufacturing method of the array substrate of the application；
Fig. 2 is the schematic diagram of a scenario based on the manufacture array substrate of method shown in Fig. 1；
Fig. 3 is the structural schematic diagram of the array substrate of one embodiment of the application.
Specific embodiment
Below with reference to the attached drawing in the embodiment of the present application, to the technology of each exemplary embodiment provided herein
Scheme is clearly and completely described.In the absence of conflict, the feature in following each embodiments and embodiment can be with
It is combined with each other.Also, directional terminology used by text of the statement, such as "upper", "lower" etc. are for preferably describing
The technical solution of each embodiment is not intended to limit the protection scope of the application.
Fig. 1 is the flow diagram of one embodiment of manufacturing method of the array substrate of the application, and Fig. 2 is based on shown in Fig. 1
The schematic diagram of a scenario of method manufacture array substrate.Referring to figs. 1 and 2, the manufacturing method may include steps of S11
~S17.
S11: a underlay substrate is provided.
The underlay substrate 20 can be glass matrix, plastic substrate or bendable matrix, and for manufacturing flexibility OLED
The scene of the array substrate of display panel, the underlay substrate 20 or flexible base board, such as (Polyimide, polyamides are sub- by PI
Amine) substrate.
Certainly, shape after the impurity on 20 surface of underlay substrate is diffused up in the subsequent process and influenced in order to prevent
At each layer structure quality, the application can the surface of the underlay substrate 20 formed a buffer layer (buffer
Layer), thickness can beThe buffer layer can be silicon oxide compound layer, such as silica (SiO2) layer,
Or it includes successively covering the silicon oxide compound layer and silicon-nitrogen compound layer of the underlay substrate 20, such as Si3N4(three nitridations
Silicon) layer or other non-conducting materials combination.Wherein, the buffer layer can using chemical vapor deposition (CVD), etc.
Method either in Plasma-activated Chemical Vapor Deposition (PACVD), sputtering, vacuum evaporation and low-pressure chemical vapor deposition (LPCVD)
It is formed.
S12: gate pattern and insulating layer are sequentially formed on underlay substrate.
It is whole that the application can form one using either method such as CVD, PECVD, sputtering, vacuum evaporations on underlay substrate 20
Face conductive layer, thickness can beThe one whole face conductive layer can by metal, such as aluminium, molybdenum, titanium, chromium,
Copper or metal oxide, such as the alloy or other conductive materials of titanium oxide or metal are constituted, then whole to this
Face conductive layer carries out patterned process, to obtain the gate pattern 211.
Specifically, the application can use one of optical cover process Mask-1 and realize the patterned process, whole described one
It is coated with a whole face photoresist on the conductive layer of face, then this whole face photoresist is exposed and is developed using light shield, is exposed
Photoresist is ashed removal in development, and the photoresist not being exposed is still retained in after development on underlay substrate 20, is connect
The conductive layer that is not covered by photoresist of etching removal, and remove remaining photoresist.
The optical cover process Mask-1 can use include phosphoric acid, nitric acid, acetic acid or deionized water etching solution erosion
Carve the conductive layer, naturally it is also possible to use dry etching.
The insulating layer 22 is also known as gate insulating layer (Gate Insulation Layer, GI layer), and material can be silicon
Oxide or the insulating layer 22 include the silicon oxide compound layer and silicon-nitrogen compound layer for successively covering gate pattern 211, thick
Spending to be
S13: the semiconductor pattern above gate pattern is formed on the insulating layer.
Firstly, a whole face semiconductor layer is formed on insulating layer 22, then by one of optical cover process Mask-2 to this
Whole face semiconductor layer carries out patterned process, with the semiconductor pattern 23 being only formed in right above gate pattern 211.It is described
Optical cover process Mask-2 is similar to the principle of optical cover process Mask-1 and process, and details are not described herein again.
Semiconductor pattern 23 is metal-oxide semiconductor (MOS) pattern, and thickness can be Its material includes
But it is not limited to IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), IZTO (Indium Zinc Tin
Oxide, indium zinc tin oxide), one in IGZTO (Indium Gallium Zinc Tin Oxide, indium gallium zinc tin oxide)
Person.
Then ion doping, such as n-type doping are carried out to the both ends of semiconductor pattern 23, can be obtained positioned at semiconductor figure
The source contact area and drain contact region at 23 both ends of case.And it is located in the middle that semiconductor pattern 23 is undoped, become the ditch of TFT
Channel layer.
S14: forming the etching barrier layer of covering insulating layer on semiconductor pattern, and the etching barrier layer uses lightproof material
Material is made, and etching barrier layer offers first contact hole and the drain contact region of the source contact area of exposed semiconductor pattern
Second contact hole.
Other than the opening of each contact hole, the upper surface of the etching barrier layer (Etch stop layer, ESL) 24
For flat surface, thickness can be 1~4 μm.
The etching barrier layer 24 using opaque material be made, such as its can use black photoresist, acrylic resin with
And at least one of polyimides formation.
The application can open up first contact using one of optical cover process Mask-3 on a whole face etching barrier layer
Hole 241 and the second contact hole 242.Specifically, the application can use first CVD, PECVD, sputtering, vacuum evaporation etc. either one
Method forms a whole face etching barrier layer of covering semiconductor pattern 23 and insulating layer 22, then in the whole face etching barrier layer
One whole face photoresist of upper coating, the wherein positive negativity phase of the photoresist and black photoresist used by the etching barrier layer 24
Instead, then this whole face photoresist is exposed and development treatment using light shield, is exposed (i.e. the first contact hole 241 and the
Region corresponding to two contact holes 242) photoresist be ashed removal in development, and the photoresist not being exposed is after development still
It is retained on etching barrier layer, the etching barrier layer that then etching removal is not covered by photoresist finally removes remaining light
The etching barrier layer 24 can be obtained in photoresist.
Wherein, the first contact hole 241 is source contact openings, and the source contact area of semiconductor pattern 23 first is contacted by this
The exposure of hole 241, the second contact hole 242 are drain contact hole, and the drain contact region of semiconductor pattern 23 passes through second contact hole
242 exposures.
S15: forming source electrode pattern and drain pattern on etching barrier layer, the source electrode pattern in the first contact hole with
The source contact area of semiconductor pattern contacts, the drain pattern in the second contact hole with the drain contact region of semiconductor pattern
Contact.
The thickness that source electrode pattern 251 and drain pattern 252 are located on the etching barrier layer 24 can beAnd it is aluminium, molybdenum, titanium, chromium, copper, metal oxide or gold that the manufacture material of the two, which includes but is not limited to,
The alloy of category or other conductive materials, naturally it is also possible to be ITO (Indium tin oxide, tin indium oxide), or successively wrap
Include this three-decker of ITO, silver and ITO.The application can carry out pattern to a whole face conductive layer by one of optical cover process Mask-4
Change processing, obtains source electrode pattern 251 and drain pattern 252 with this.The optical cover process Mask-4's and optical cover process Mask-1
Principle and process are similar, and details are not described herein again.
Wherein, source contact of the source electrode pattern 251 in first contact hole 241 with the semiconductor pattern 23
Area's contact, the drain pattern 252 are contacted in second contact hole 242 with the drain contact region of the semiconductor pattern 23.
It should be appreciated that the application can also be synchronized on the etching barrier layer 24 by the optical cover process Mask-4
Form the various types of signal cabling of array substrate, such as data line etc..The signal lead and source electrode pattern 251 and drain pattern
252 material is identical.
By the above-mentioned means, can be prepared by the TFT of the application array substrate.
Further, for the application scenarios of the array substrate of manufacture OLED display panel, the drain pattern 252 is also made
For the anode pattern (Anode) of OLED display panel.And it is based on this, and after the step s 15, the manufacturing method further include:
S16: forming pixel defining layer on source electrode pattern and drain pattern, and the pixel defining layer is equipped with for limiting battle array
The luminous zone of column substrate.
The pixel defining layer (Pixel Define Layer, PDL) 26 sets the luminous zone to form array substrate for enclosing
261, i.e., for limiting pixel openings area.
S17: luminescent layer and cathode pattern in drain pattern are sequentially formed in luminous zone.
Certainly, the array substrate of the application further includes being sequentially formed in anode pattern (i.e. drain pattern) 252 and luminescent layer
Electron injecting layer and electron transfer layer between 27, and the hole being sequentially formed between luminescent layer 27 and cathode pattern 28 pass
Defeated layer and hole injection layer.
It can be prepared by the application array substrate 30 as shown in Figure 3, in conjunction with shown in Fig. 2 and Fig. 3, source electrode by the above method
Pattern 251 and drain pattern 252 are formed directly on etching barrier layer 24, and traditional flatness layer is replaced by etching barrier layer 24
(PLN) and passivation layer (PV), i.e., no setting is required flatness layer and passivation layer, and the drain pattern 252 is also used as anode pattern simultaneously,
So as to reduce optical cover process, and the etching barrier layer 24 is made using light screening material, can protect the channel layer of TFT not
By illumination effect, it is advantageously ensured that its performance is stablized.
Please continue to refer to Fig. 2 and Fig. 3, the top of the underlay substrate 20 may include along the side for being parallel to underlay substrate 20
To adjacent first area 201 and second area 202, the two is respectively the area TFT and capacitive region of the array substrate 30, described
Gate pattern 211 and semiconductor pattern 23 are only formed in the first area 201, and the storage capacitance of the capacitive region can be used for compensating
The electric leakage of the pixel region of array substrate 30.In this, be also formed with two conductive layers in the second area 202, i.e., shown in Fig. 2
Two gate patterns 212 and capacitor electrode patterns 253, the gate pattern 211 for being now placed in first area 201 can be considered first grid
Pattern 211.The capacitor electrode patterns 253 are least partially overlapped with second grid pattern 212 and by being located between the two
Insulating layer 22 formed the storage capacitance.
The application can synchronize to form 212 He of second grid pattern by the optical cover process Mask-1 in step S12
First grid pattern 211.
In addition, the etching barrier layer 24 is equipped with open region 243 in the second area 202, the insulating layer 22 is in institute
State its surface of exposure of open region 243.The application can synchronize to form described first by the optical cover process Mask-3 in step S14
Contact hole 241, the second contact hole 242 and open region 243.
Similarly, the application can be synchronized by the optical cover process Mask-4 in step S15 to be formed the source electrode pattern 251,
Drain pattern 252 and capacitor electrode patterns 253.
The application also provides a kind of display panel.The display panel may include array base obtained by previous embodiment
Plate, therefore there is same beneficial effect.
In conclusion the main purpose of the application is: design source electrode pattern and drain pattern are formed directly into etch stopper
On layer, traditional flatness layer and passivation layer are replaced by etching barrier layer, i.e., no setting is required flatness layer and passivation layer, and the leakage
Pole figure case also as the anode pattern of OLED device, reduces optical cover process simultaneously with this, and the etching barrier layer is using screening
Luminescent material is made, to protect the channel layer of TFT not by illumination effect, it is advantageously ensured that its performance is stablized.
On this basis, above is only an example of the present application, it is not intended to limit the scope of the patents of the application, it is all
It is to utilize technology between equivalent structure or equivalent flow shift, such as each embodiment made by present specification and accompanying drawing content
Feature be combined with each other, and being applied directly or indirectly in other relevant technical fields, similarly includes patent in the application
In protection scope.
Claims (10)
1. a kind of manufacturing method of array substrate, which is characterized in that the described method includes:
One underlay substrate is provided；
First grid pattern and insulating layer are sequentially formed on the underlay substrate；
It is formed on the insulating layer the semiconductor pattern being located above the first grid pattern；
The etching barrier layer for covering the insulating layer is formed on the semiconductor pattern, the etching barrier layer uses lightproof material
Material is made, and the etching barrier layer offers the first contact hole and the drain electrode of the source contact area of the exposure semiconductor pattern
Second contact hole of contact zone；
Form source electrode pattern and drain pattern on the etching barrier layer, the source electrode pattern in first contact hole with
The source contact area of the semiconductor pattern contacts, the drain pattern in second contact hole with the semiconductor pattern
Drain contact region contact；
Pixel defining layer is formed on the source electrode pattern and drain pattern, the pixel defining layer is equipped with for limiting the battle array
The luminous zone of column substrate；
Luminescent layer and cathode pattern in drain pattern are sequentially formed in the luminous zone.
2. the method according to claim 1, wherein the top of the underlay substrate includes that edge is parallel to substrate base
The adjacent first area in the direction of plate and second area, the first grid pattern and semiconductor pattern are formed in firstth area
Domain, the etching barrier layer are equipped with open region in the second area, and the insulating layer exposes its surface in the open region,
The method also includes:
The second grid pattern for being located at second area is formed on the underlay substrate；And
The capacitor electrode patterns for covering the open region, the capacitor electrode patterns and described second are formed in the second area
Gate pattern is least partially overlapped and by being located in insulating layer one capacitor of formation between the two.
3. according to the method described in claim 2, it is characterized in that, by with along with optical cover process form the second gate pole figure
Case and first grid pattern, by with along with optical cover process form the source electrode pattern, drain pattern and capacitor electrode patterns.
4. the method according to claim 1, wherein the surface of the etching barrier layer is plane.
5. method according to any one of claims 1 to 4, which is characterized in that using black photoresist, acrylic resin and gather
At least one of acid imide forms the etching barrier layer.
6. a kind of array substrate, which is characterized in that the array substrate includes:
Underlay substrate；
First grid pattern and the insulating layer being sequentially formed on the underlay substrate；
It is formed in the semiconductor pattern on the insulating layer and being located above the first grid pattern；
It is formed on the semiconductor pattern and the etching barrier layer of the covering insulating layer, the etching barrier layer uses shading
Material is made, and the etching barrier layer offers the first contact hole and the leakage of the source contact area of the exposure semiconductor pattern
Second contact hole of pole contact zone；
Source electrode pattern and the drain pattern being formed on the etching barrier layer, the source electrode pattern is in first contact hole
Contacted with the source contact area of the semiconductor pattern, the drain pattern in second contact hole with the semiconductor figure
The drain contact region of case contacts；
The pixel defining layer being formed in the source electrode pattern and drain pattern, the pixel defining layer are equipped with described for limiting
The luminous zone of array substrate；
The luminescent layer and cathode pattern for being sequentially formed in the luminous zone and being located in drain pattern.
7. array substrate according to claim 6, which is characterized in that the top of the underlay substrate includes that edge is parallel to lining
The adjacent first area in the direction of substrate and second area, the first grid pattern and semiconductor pattern are formed in described
One region, the etching barrier layer are equipped with open region in the second area, and the insulating layer is in its table of open region exposure
Face, the array substrate further include the second grid pattern and shape for being formed on the underlay substrate and being located at second area
Second area described in Cheng Yu and the capacitor electrode patterns of the covering open region, the capacitor electrode patterns and the second grid
Pattern is least partially overlapped and by being located in insulating layer one capacitor of formation between the two.
8. array substrate according to claim 7, which is characterized in that the surface of the etching barrier layer is plane.
9. array substrate according to claim 7, which is characterized in that the material of the etching barrier layer includes black light
At least one of resistance, acrylic resin and polyimides.
10. a kind of display panel, which is characterized in that the display panel includes as the claims 6~9 are described in any item
Array substrate.
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| CN201810895821.4A CN109166864A (en) | 2018-08-08 | 2018-08-08 | Array substrate and its manufacturing method, display panel |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034131A (en) * | 2019-04-17 | 2019-07-19 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel and display device |
| CN111524859A (en) * | 2020-04-23 | 2020-08-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2021051509A1 (en) * | 2019-09-16 | 2021-03-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method therefor |
| CN112968031A (en) * | 2021-02-02 | 2021-06-15 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN113488543A (en) * | 2021-06-29 | 2021-10-08 | 惠科股份有限公司 | Thin film transistor, preparation method thereof and display panel |
| US11495650B2 (en) | 2020-01-30 | 2022-11-08 | Samsung Display Co., Ltd. | Display apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030127650A1 (en) * | 2001-12-29 | 2003-07-10 | Jae-Yong Park | Active matrix organic electroluminescent display device and fabricating method thereof |
| CN103107181A (en) * | 2011-11-14 | 2013-05-15 | 三星显示有限公司 | Organic light-emitting display device and method of manufacturing the same |
| CN104393017A (en) * | 2014-10-31 | 2015-03-04 | 京东方科技集团股份有限公司 | Array substrate manufacturing method, array substrate and display device |
| CN108172592A (en) * | 2016-12-05 | 2018-06-15 | 三星显示有限公司 | Flexible organic light-emitting display device and its manufacturing method |
-
2018
- 2018-08-08 CN CN201810895821.4A patent/CN109166864A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030127650A1 (en) * | 2001-12-29 | 2003-07-10 | Jae-Yong Park | Active matrix organic electroluminescent display device and fabricating method thereof |
| CN103107181A (en) * | 2011-11-14 | 2013-05-15 | 三星显示有限公司 | Organic light-emitting display device and method of manufacturing the same |
| CN104393017A (en) * | 2014-10-31 | 2015-03-04 | 京东方科技集团股份有限公司 | Array substrate manufacturing method, array substrate and display device |
| CN108172592A (en) * | 2016-12-05 | 2018-06-15 | 三星显示有限公司 | Flexible organic light-emitting display device and its manufacturing method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034131A (en) * | 2019-04-17 | 2019-07-19 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel and display device |
| WO2021051509A1 (en) * | 2019-09-16 | 2021-03-25 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method therefor |
| US11495650B2 (en) | 2020-01-30 | 2022-11-08 | Samsung Display Co., Ltd. | Display apparatus |
| CN111524859A (en) * | 2020-04-23 | 2020-08-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof and display device |
| WO2021212579A1 (en) * | 2020-04-23 | 2021-10-28 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and method for manufacturing same, and display apparatus |
| CN112968031A (en) * | 2021-02-02 | 2021-06-15 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN113488543A (en) * | 2021-06-29 | 2021-10-08 | 惠科股份有限公司 | Thin film transistor, preparation method thereof and display panel |
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Application publication date: 20190108 |