CN110034131B - Array substrate, manufacturing method thereof, display panel and display device - Google Patents
Array substrate, manufacturing method thereof, display panel and display device Download PDFInfo
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- CN110034131B CN110034131B CN201910308991.2A CN201910308991A CN110034131B CN 110034131 B CN110034131 B CN 110034131B CN 201910308991 A CN201910308991 A CN 201910308991A CN 110034131 B CN110034131 B CN 110034131B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
An embodiment of the present invention provides an array substrate, including: the semiconductor device comprises a substrate base plate, an active layer, a grid electrode, a source electrode and a drain electrode which are sequentially arranged on the substrate base plate, and a shielding layer which is positioned between the substrate base plate and the active layer. The outline of the orthographic projection area of the shielding layer on the substrate base plate is larger than the outline of the orthographic projection area of the active layer on the substrate base plate. The shielding layer is provided with a first through hole, and the position of the first through hole corresponds to the position of the source electrode in contact with the active layer; and/or the shielding layer is provided with a second through hole, and the position of the second through hole corresponds to the position of the drain electrode in contact with the active layer. The embodiment of the invention also discloses a display panel, a display device and a manufacturing method of the array substrate. The outer contour of the shielding layer is larger than that of the active layer, so that the shielding effect of the shielding layer is enhanced. Meanwhile, the shielding layer is provided with the first through hole and/or the second through hole, so that parasitic capacitance among the source electrode, the drain electrode and the shielding layer is avoided.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate, a display panel and a display device.
Background
The conventional display panel comprises an array substrate and a color film substrate which are oppositely arranged, wherein the array substrate comprises a plurality of thin film transistors, and when an active layer of each thin film transistor is illuminated by light, the characteristics of the thin film transistor are easy to drift, so that the normal use of the thin film transistor is influenced. In order to prevent the ambient light from directly or indirectly irradiating the active layer, a shielding layer is generally disposed below the active layer to shield the ambient light.
The inventor finds that the position shielded by the shielding layer only corresponds to the position of the channel region of the active layer at present, and does not shield the whole area of the active layer, so that the active layer is easily irradiated by ambient light, thereby affecting the characteristics of the thin film transistor.
Disclosure of Invention
In view of the above, the present invention provides an array substrate, a manufacturing method thereof, a display panel and a display device, which solve the technical problem that in the prior art, an active layer is easily irradiated by ambient light, so that characteristics of a thin film transistor are affected.
In order to solve the above problems, embodiments of the present invention mainly provide the following technical solutions:
in a first aspect, an embodiment of the present invention discloses an array substrate, including: the semiconductor device comprises a substrate base plate, an active layer, a grid electrode, a source electrode and a drain electrode, wherein the active layer, the grid electrode, the source electrode and the drain electrode are sequentially arranged on the substrate base plate;
the outline of an orthographic projection area of the shielding layer on the substrate is larger than that of an orthographic projection area of the active layer on the substrate; and
the shielding layer is provided with a first through hole, and the position of the first through hole corresponds to the position of the source electrode in contact with the active layer; and/or the presence of a gas in the gas,
the shielding layer is provided with a second through hole, and the position of the second through hole corresponds to the position of the drain electrode in contact with the active layer.
Optionally, an area of an orthographic projection area of the shielding layer on the substrate base plate is larger than an area of an orthographic projection area of the active layer on the substrate base plate.
Optionally, an outer contour of an orthographic projection area of the first via hole on the substrate is greater than or equal to an outer contour of an orthographic projection area of the source via hole on the substrate;
the outline of the orthographic projection area of the second through hole on the substrate is larger than or equal to the outline of the orthographic projection area of the drain through hole on the substrate.
Optionally, an orthographic projection area of the first via hole on the substrate is greater than or equal to an orthographic projection area of a region, contacting the source electrode and the active layer, of the substrate.
Optionally, an orthographic projection area of the second via hole on the substrate is greater than or equal to an orthographic projection area of a region, in contact with the active layer, of the drain electrode on the substrate.
Optionally, an orthographic projection area of the first via hole on the substrate base plate is equal to an orthographic projection area of the second via hole on the substrate base plate.
Optionally, the display device further comprises a common electrode line, and the common electrode line and the shielding layer are located in the same layer and electrically connected with the shielding layer.
Optionally, the common electrode line and the shielding layer are of an integral structure.
Optionally, the method further comprises: the common electrode wire, the insulating layer positioned between the active layer and the shielding layer, and the gate insulating layer positioned between the active layer and the gate;
the common electrode wire and the grid are located on the same layer and are electrically connected with the shielding layer through a third through hole penetrating through the insulating layer and the grid insulating layer.
Optionally, the material of the shielding layer is at least one of copper, aluminum, molybdenum, titanium, chromium, and tungsten.
In a second aspect, an embodiment of the present invention discloses a display panel, including the array substrate according to the first aspect.
In a third aspect, an embodiment of the invention discloses a display device, which includes the display panel described in the second aspect.
In a fourth aspect, an embodiment of the present invention discloses a manufacturing method of an array substrate, including fabrication of an active layer, a gate electrode, a source electrode, and a drain electrode, further including:
manufacturing a shielding layer on a substrate through a composition process, wherein the outline of an orthographic projection area of the shielding layer on the substrate is larger than the outline of an orthographic projection area of the active layer on the substrate;
and manufacturing a first via hole and/or a second via hole on the shielding layer, wherein the position of the first via hole corresponds to the position of the source electrode in contact with the active layer, and the position of the second via hole corresponds to the position of the drain electrode in contact with the active layer.
Optionally, after the first via and/or the second via are/is formed on the shielding layer, the method specifically includes:
manufacturing an insulating layer on the shielding layer;
and sequentially manufacturing an active layer, a gate insulating layer, a gate, an interlayer insulating layer, a source and a drain on the insulating layer by a composition process.
Optionally, the method further includes manufacturing a common electrode line, where the common electrode line and the shielding layer are manufactured and formed by using the same composition process;
or, the common electrode line and the grid are manufactured and formed by adopting the same composition process.
By the technical scheme, the technical scheme provided by the embodiment of the invention at least has the following advantages:
because the outline of the orthographic projection area of the shielding layer on the substrate is larger than the outline of the orthographic projection area of the active layer on the substrate, the shielding layer can shield the whole active layer area, the active layer is prevented from being irradiated by ambient light, and the characteristics of the thin film transistor are improved; in addition, because the shielding layer is provided with the first through hole, the position of the first through hole corresponds to the position of the source electrode in contact with the active layer, so that the parasitic capacitance between the source electrode in the position of contact with the active layer and the shielding layer can be reduced; and the shielding layer is provided with a second through hole, and the position of the second through hole corresponds to the position of the contact between the drain electrode and the active layer, so that the parasitic capacitance between the drain electrode and the shielding layer at the position of the contact between the drain electrode and the active layer can be reduced, and the performance of the array substrate is improved.
The foregoing description is only an overview of the technical solutions of the embodiments of the present invention, and the embodiments of the present invention can be implemented according to the content of the description in order to make the technical means of the embodiments of the present invention more clearly understood, and the detailed description of the embodiments of the present invention is provided below in order to make the foregoing and other objects, features, and advantages of the embodiments of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the alternative embodiments. The drawings are only for purposes of illustrating alternative embodiments and are not to be construed as limiting the embodiments of the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic structural diagram of a prior art array substrate;
FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1;
fig. 3 is a schematic structural diagram of an array substrate according to a first embodiment of the invention;
FIG. 4 is a cross-sectional view taken along line A-A' of FIG. 3;
fig. 5 is a schematic structural diagram of an array substrate according to a second embodiment of the invention;
FIG. 6 is a cross-sectional view taken along line A-A' of FIG. 5;
FIG. 7 is a cross-sectional view taken along line B-B' of FIG. 5;
FIG. 8 is a cross-sectional view taken along line C-C' of FIG. 5;
fig. 9 is a schematic structural diagram of an array substrate according to a third embodiment of the invention;
FIG. 10 is a cross-sectional view taken along line A-A' of FIG. 9;
FIG. 11 is a cross-sectional view taken along line B-B' of FIG. 9;
FIG. 12 is a cross-sectional view taken along line C-C' of FIG. 9;
fig. 13 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention.
The reference numerals are introduced as follows:
1-a substrate base plate; 2-a shielding layer; 3-an insulating layer; 4-an active layer; 5-a gate insulating layer; 6-a grid; 7-an interlayer insulating layer; an 8-source electrode; 9-a drain electrode;
10-a passivation layer; 11-a pixel electrode; 12-a data line; 13-a gate line; 14-common electrode lines; 15-a first via; 16-a second via; 17-a via hole; 171-a third via; 18-a common electrode; 19-second insulating layer.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Further, "connected" as used herein may include wirelessly connected. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The inventor has studied the structure of a thin film transistor included in an array substrate in the prior art, as shown in fig. 1 and fig. 2, fig. 1 is a plan view of the array substrate in the prior art, fig. 2 is a cross-sectional view taken along a line a-a' in fig. 1, a shielding layer 2, an insulating layer 3, an active layer 4, a gate insulating layer 5, a gate electrode 6, an interlayer insulating layer 7, a source electrode 8, a drain electrode 9, a passivation layer 10, and a pixel electrode 11 are sequentially disposed on a substrate 1, wherein a data line 12 and the source electrode 8 are located in the same layer and connected to the source electrode 8; the gate line 13 is located at the same layer as the gate electrode 6 and is connected to the gate electrode 6.
The inventor finds that, in the prior art, if the area of the orthographic projection area of the shielding layer 2 on the substrate 1 is larger than or equal to the area of the orthographic projection area of the active layer 4 on the substrate 1, the distance between the position where the source electrode 8 is in contact with the active layer 4 and the shielding layer 2 is close, the parasitic capacitance between the source electrode 8 and the shielding layer 2 is relatively large, and similarly, the distance between the position where the drain electrode 9 is in contact with the active layer 4 and the shielding layer 2 is close, the parasitic capacitance between the source electrode 9 and the shielding layer 2 is relatively large, and the performance of the array substrate is affected.
Therefore, the inventor finds that the shielding layer 2 of the prior art only shields the channel region of the active layer 4, but the shielding layer 2 cannot shield the whole region of the active layer 4, so that the active layer 4 is easily irradiated by the ambient light, thereby affecting the characteristics of the thin film transistor.
In order to solve the above technical problems in the prior art, embodiments of the present invention provide a new array substrate structure.
An embodiment of the present invention provides an array substrate, as shown in fig. 3 to 12, the array substrate includes: the array substrate comprises a substrate base plate 1, and an active layer 4, a grid electrode 6, a source electrode 8 and a drain electrode 9 which are sequentially arranged on the substrate base plate 1, and further comprises a shielding layer 2 which is positioned between the substrate base plate 1 and the active layer 4. The outline of the orthographic projection area of the shielding layer 2 on the substrate base plate 1 is larger than the outline of the orthographic projection area of the active layer 4 on the substrate base plate 1. The shielding layer 2 is provided with a first through hole 15, and the position of the first through hole 15 corresponds to the position of the source electrode 8 contacting the active layer 4; and/or the shielding layer 2 is provided with a second via hole 16, and the position of the second via hole 16 corresponds to the position of the drain electrode 9 contacting the active layer 4.
Because the outline of the orthographic projection area of the shielding layer 2 on the substrate base plate 1 is larger than the outline of the orthographic projection area of the active layer 4 on the substrate base plate 1, the shielding layer 2 can shield the whole area of the active layer 4, the active layer 4 is prevented from being irradiated by ambient light, and the characteristics of the thin film transistor are improved; in addition, since the shielding layer 2 is provided with the first via 15 in the embodiment of the invention, the position of the first via 15 corresponds to the position where the source electrode 8 contacts the active layer 4, so that the parasitic capacitance between the source electrode 8 and the shielding layer 2 at the position where the source electrode 8 contacts the active layer 4 can be reduced; and the shielding layer 2 is provided with a second through hole 16, and the position of the second through hole 16 corresponds to the contact position of the drain electrode 9 and the active layer 4, so that the parasitic capacitance between the drain electrode 9 and the shielding layer 2 at the contact position of the drain electrode 9 and the active layer 4 can be reduced, and the performance of the array substrate is improved.
The array substrate provided by the embodiment of the invention is described in detail by several specific embodiments.
Fig. 3 and 4 are schematic structural views illustrating a first embodiment of an array substrate according to an embodiment of the present invention, fig. 3 is a plan structural view illustrating the first embodiment of the present invention, and fig. 4 is a cross-sectional view taken along a line a-a' in fig. 3.
As shown in fig. 3 and 4, the array substrate includes: the semiconductor device comprises a substrate base plate 1, an active layer 4, a grid electrode 6, a source electrode 8 and a drain electrode 9 which are sequentially arranged on the substrate base plate 1, and a shielding layer 2 which is positioned between the substrate base plate 1 and the active layer 4. The outline of the orthographic projection area of the shielding layer 2 on the substrate base plate 1 is larger than the outline of the orthographic projection area of the active layer 4 on the substrate base plate 1. The shielding layer 2 is provided with a first via 15, and the position of the first via 15 corresponds to the position where the source electrode 8 contacts the active layer 4.
Generally, the signal change frequency on the data line 12 is very high, when the data line 12 is connected to the source electrode 8, the distance between the position where the source electrode 8 contacts the active layer 4 and the shielding layer 2 is close, the parasitic capacitance between the two is large, the signal transmission of the data line 12 is affected, and the signal distortion deformation of the data line is caused. In the embodiment of the invention, the shielding layer 2 is provided with the first via hole 15 at the position where the source electrode 8 is in contact with the active layer 4, so that the parasitic capacitance between the source electrode 8 and the shielding layer 2 at the position where the source electrode is in contact with the active layer 4 is reduced, and the load of the data line 12 is reduced.
Optionally, the area of the orthographic projection area of the shielding layer 2 on the substrate base plate 1 is larger than that of the orthographic projection area of the active layer 4 on the substrate base plate 1; like this for shielding layer 2 can shelter from active layer 4 completely, promotes and shelters from the effect, further avoids active layer 4 to receive the shining of ambient light, improves thin film transistor's characteristic.
Alternatively, it is generally necessary to make a source via penetrating the gate insulating layer 5 and the interlayer insulating layer 7 before making the source so that the source can be electrically connected to the active layer 4 through the source via after making the source. In order to achieve the technical effect of the present embodiment, the outer contour of the orthographic projection area of the first via 15 on the substrate 1 is greater than or equal to the outer contour of the orthographic projection area of the source via on the substrate 1.
Optionally, the orthographic projection area of the first via 15 on the substrate base plate 1 is greater than or equal to the orthographic projection area of the area, contacting the source electrode 8 and the active layer 4, of the substrate base plate 1; thus, parasitic capacitance cannot be generated at the position where the source electrode 8 is in contact with the active layer 4, and the influence of the parasitic capacitance on signal transmission of the data line is further reduced.
Fig. 5 to 8 are schematic structural views illustrating a second embodiment of an array substrate according to an embodiment of the present invention, fig. 5 is a plan view of the second embodiment of the present invention, fig. 6 is a sectional view taken along a line a-a ' in fig. 5, fig. 7 is a sectional view taken along a line B-B ' in fig. 5, and fig. 8 is a sectional view taken along a line C-C ' in fig. 5.
As shown in fig. 5 and 6, the array substrate includes: the semiconductor device comprises a substrate base plate 1, an active layer 4, a grid electrode 6, a source electrode 8 and a drain electrode 9 which are sequentially arranged on the substrate base plate 1, and a shielding layer 2 which is positioned between the substrate base plate 1 and the active layer 4. The outline of the orthographic projection area of the shielding layer 2 on the substrate base plate 1 is larger than the outline of the orthographic projection area of the active layer 4 on the substrate base plate 1. The shielding layer 2 is provided with a first via 15, and the position of the first via 15 corresponds to the position where the source electrode 8 contacts the active layer 4.
As shown in fig. 5, 7 and 8, the array substrate further includes a common electrode line 14, and the common electrode line 14 is located at the same layer as the shielding layer 2 and is electrically connected to the shielding layer 2. Since the common electrode line 14 is electrically connected to the shielding layer 2, static charges accumulated on the shielding layer 2 can be dispersed by the common electrode line 14, and the static charges accumulated on the shielding layer 2 can be prevented from affecting the characteristics of the thin film transistor.
Optionally, the common electrode line 14 and the shielding layer 2 are of an integral structure, so that the manufacturing difficulty can be reduced, and the market competitiveness can be improved.
Fig. 9 to 12 are schematic structural views illustrating a third embodiment of an array substrate according to an embodiment of the present invention, respectively, fig. 9 is a plan view of the third embodiment of the present invention, fig. 10 is a sectional view taken along a line a-a ' in fig. 9, fig. 11 is a sectional view taken along a line B-B ' in fig. 9, and fig. 12 is a sectional view taken along a line C-C ' in fig. 9.
As shown in fig. 9 and 10, the array substrate includes: the semiconductor device comprises a substrate base plate 1, an active layer 4, a grid electrode 6, a source electrode 8 and a drain electrode 9 which are sequentially arranged on the substrate base plate 1, and a shielding layer 2 which is positioned between the substrate base plate 1 and the active layer 4. The outline of the orthographic projection area of the shielding layer 2 on the substrate base plate 1 is larger than the outline of the orthographic projection area of the active layer 4 on the substrate base plate 1. The shielding layer 4 is provided with a first via hole 15, the position of the first via hole 15 corresponds to the position where the source electrode 8 contacts the active layer 4, the shielding layer 2 is provided with a second via hole 16, and the position of the second via hole 16 corresponds to the position where the drain electrode 9 contacts the active layer 4.
Optionally, the orthographic projection area of the second via hole 16 on the substrate base plate 1 is greater than or equal to the orthographic projection area of the region where the drain electrode 9 is in contact with the active layer 4 on the substrate base plate 1; thus, parasitic capacitance cannot be generated at the position where the drain electrode 9 contacts the active layer 4, and the influence of the parasitic capacitance on the signal transmission of the data line is further reduced.
Alternatively, it is generally necessary to make a source via penetrating the gate insulating layer 5 and the interlayer insulating layer 7 before making the source so that the source can be electrically connected to the active layer 4 through the source via after making the source. In order to achieve the technical effect of the present embodiment, the outer contour of the orthographic projection area of the first via 15 on the substrate 1 is greater than or equal to the outer contour of the orthographic projection area of the source via on the substrate 1.
Similarly, in general, before the drain electrode is fabricated, a drain via hole penetrating the gate insulating layer 5 and the interlayer insulating layer 7 needs to be fabricated so that the drain electrode can be electrically connected to the active layer 4 through the drain via hole after the drain electrode is fabricated. In order to achieve the technical effect of the present embodiment, the outer contour of the orthographic projection area of the second via hole 16 on the substrate base plate 1 is greater than or equal to the outer contour of the orthographic projection area of the drain via hole on the substrate base plate 1.
Optionally, an orthographic area of the first via 15 on the substrate base 1 is equal to an orthographic area of the second via 16 on the substrate base 1. The orthographic projection areas of the first through hole 15 and the second through hole 16 are equal, so that the manufacturing difficulty and cost can be reduced, and the market competitiveness can be improved.
As shown in fig. 9, 11 and 12, the array substrate further includes a common electrode line 14, an insulating layer 3 between the active layer 4 and the shielding layer 2, and a gate insulating layer 5 between the active layer 4 and the gate electrode 6; the common electrode line 14 is located at the same layer as the gate electrode 6 and is electrically connected to the shield layer 2 through a third via 171 penetrating the insulating layer 3 and the gate insulating layer 5. Since the common electrode line 14 is electrically connected to the shielding layer 2, static charges accumulated on the shielding layer 2 can be dispersed by the common electrode line 14, and the static charges accumulated on the shielding layer 2 can be prevented from affecting the characteristics of the thin film transistor.
Specifically, as shown in fig. 4, 6, 7, 8, 10, 11, and 12, the array substrate further includes: an interlayer insulating layer 7 on the gate electrode 6, a passivation layer 10 on the interlayer insulating layer 7, a pixel electrode 11 on the passivation layer 10, a second insulating layer 19 on the pixel electrode 11, and a common electrode 18 on the second insulating layer 19.
As shown in fig. 7, the common electrode 18 is connected to the common electrode line 14 through a via hole penetrating the second insulating layer 19, the passivation layer 10, the interlayer insulating layer 7, the gate insulating layer 5, and the insulating layer 3. As shown in fig. 11, the common electrode 18 is connected to the common electrode line 14 through a via hole penetrating the second insulating layer 19, the passivation layer 10, and the interlayer insulating layer 7.
Optionally, the material of the shielding layer 2 is at least one of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), and tungsten (W). Specifically, one of copper, aluminum, molybdenum, titanium, chromium, and tungsten, or an alloy material of these materials may be selected, and the shielding layer 2 may have a single-layer metal structure or a multi-layer metal structure, such as: multilayer metals of molybdenum, aluminum and molybdenum, multilayer metals of titanium, copper and titanium, and multilayer metals of molybdenum, titanium and copper can be adopted.
In the embodiment of the present invention, similar to the material of the shielding layer 2, at least one of copper, aluminum, molybdenum, titanium, chromium, and tungsten may be used for the gate electrode 6, the source electrode 8, and the drain electrode 9, and an alloy material of these materials may also be used. The gate electrode 6, the source electrode 8, and the drain electrode 9 may have a single-layer metal structure or a multi-layer metal structure.
In the embodiment of the present invention, the active layer 4 may be amorphous silicon, polysilicon, or an oxide material.
In the embodiment of the present invention, the pixel electrode 11 and the common electrode 18 may be Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
In the embodiment of the present invention, the gate insulating layer 5 may be made of silicon nitride or silicon oxide. The gate insulating layer 5 may have a single-layer structure or a multi-layer structure, such as: a double-layer structure of silicon nitride and silicon oxide is used.
In the embodiment of the present invention, the interlayer insulating layer 7 may be made of silicon nitride or silicon oxide. The interlayer insulating layer 7 may have a single-layer structure or a multilayer structure.
In the embodiment of the present invention, the passivation layer 10 may be silicon nitride or silicon oxide. The passivation layer 10 may have a single-layer structure or a multi-layer structure.
In the embodiment of the present invention, the insulating layer 3 and the second insulating layer 19 may be made of silicon nitride or silicon oxide. The first insulating layer 3 and the second insulating layer 19 may have a single-layer structure or a multilayer structure.
Based on the same inventive concept, the embodiment of the invention also discloses a display panel, which comprises the array substrate. Because the display panel comprises the array substrate, the display panel has the same beneficial effects as the array substrate. Therefore, the beneficial effects of the display panel are not repeated herein.
Based on the same inventive concept, the embodiment of the invention also discloses a display device, which comprises the display panel. Since the display device comprises the display panel, the display device has the same beneficial effects as the display panel. Therefore, the advantageous effects of the display device will not be repeated herein.
Based on the same inventive concept, the embodiment of the invention also discloses a manufacturing method of the array substrate, which comprises the manufacturing of an active layer, a grid electrode, a source electrode and a drain electrode. As shown in fig. 13, the method for manufacturing an array substrate further includes:
s101: and manufacturing a shielding layer on the substrate base plate through a composition process, wherein the outline of an orthographic projection area of the shielding layer on the substrate base plate is larger than the outline of an orthographic projection area of the active layer on the substrate base plate.
S102: and manufacturing a first via hole and/or a second via hole on the shielding layer, wherein the position of the first via hole corresponds to the position of the source electrode in contact with the active layer, and the position of the second via hole corresponds to the position of the drain electrode in contact with the active layer.
Optionally, after S102, the embodiment of the present invention specifically includes:
and manufacturing an insulating layer on the shielding layer.
An active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode are sequentially formed on the insulating layer through a composition process. The specific manufacturing methods of the active layer, the gate insulating layer, the gate, the interlayer insulating layer, the source and the drain in the embodiments of the present invention are similar to those in the prior art, and are not described herein again.
Optionally, the manufacturing method of the array substrate according to the embodiment of the invention further includes manufacturing a common electrode line, and specifically, the common electrode line and the shielding layer are manufactured and formed by using the same patterning process. Or, the common electrode line and the grid are manufactured and formed by the same composition process.
The beneficial effects obtained by applying the embodiment of the invention comprise:
1. because the outline of the orthographic projection area of the shielding layer on the substrate is larger than the outline of the orthographic projection area of the active layer on the substrate, the shielding layer can shield the whole active layer area, the active layer is prevented from being irradiated by ambient light, and the characteristics of the thin film transistor are improved; in addition, because the shielding layer is provided with the first through hole at the position where the source electrode is in contact with the active layer in the embodiment of the invention, the parasitic capacitance between the source electrode and the shielding layer at the position where the source electrode is in contact with the active layer can be reduced; and the shielding layer is provided with a second through hole at the position where the drain electrode is in contact with the active layer, so that the parasitic capacitance between the drain electrode and the shielding layer at the position where the drain electrode is in contact with the active layer can be reduced, and the performance of the array substrate is improved.
2. The orthographic projection area of the first through hole on the substrate is larger than or equal to the orthographic projection area of the area, contacting the source electrode with the active layer, of the substrate; therefore, parasitic capacitance cannot be generated at the position where the source electrode is in contact with the active layer, and the influence of the parasitic capacitance on signal transmission of the data line is further reduced.
3. Since the common electrode line is electrically connected to the shielding layer, static charges accumulated on the shielding layer can be dispersed through the common electrode line, and the static charges accumulated on the shielding layer can be prevented from affecting the characteristics of the thin film transistor.
The foregoing is only a partial embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (11)
1. An array substrate, comprising: the semiconductor device comprises a substrate base plate, and an active layer, a grid electrode, a source electrode and a drain electrode which are sequentially arranged on the substrate base plate, and is characterized by further comprising a shielding layer and a common electrode wire which are positioned between the substrate base plate and the active layer;
the outline of an orthographic projection area of the shielding layer on the substrate is larger than that of an orthographic projection area of the active layer on the substrate; and
the shielding layer is provided with a first through hole, and the position of the first through hole corresponds to the position of the source electrode in contact with the active layer;
the shielding layer is provided with a second through hole, and the position of the second through hole corresponds to the position of the drain electrode in contact with the active layer; the common electrode wire is electrically connected with the shielding layer;
the orthographic projection area of the first through hole on the substrate is larger than or equal to the orthographic projection area of the area, contacting the source electrode with the active layer, of the substrate;
the orthographic projection area of the second through hole on the substrate is larger than or equal to the orthographic projection area of the region, in contact with the active layer, of the drain electrode on the substrate;
the orthographic projection area of the first through hole on the substrate base plate is equal to the orthographic projection area of the second through hole on the substrate base plate.
2. The array substrate of claim 1, wherein an area of an orthographic projection area of the shielding layer on the substrate is larger than an area of an orthographic projection area of the active layer on the substrate.
3. The array substrate of claim 1, wherein an outer contour of an orthographic projection area of the first via on the substrate is greater than or equal to an outer contour of an orthographic projection area of a source via on the substrate;
the outline of the orthographic projection area of the second through hole on the substrate is larger than or equal to the outline of the orthographic projection area of the drain through hole on the substrate.
4. The array substrate of any one of claims 1-3, wherein the common electrode lines and the shielding layer are located at the same layer.
5. The array substrate of claim 4, wherein the common electrode line and the shielding layer are of an integral structure.
6. The array substrate of claim 1, further comprising: an insulating layer between the active layer and the shielding layer, and a gate insulating layer between the active layer and the gate electrode;
the common electrode wire and the grid are located on the same layer and are electrically connected with the shielding layer through a third through hole penetrating through the insulating layer and the grid insulating layer.
7. The array substrate of claim 1, wherein the material of the shielding layer is at least one of copper, aluminum, molybdenum, titanium, chromium, and tungsten.
8. A display panel comprising the array substrate according to any one of claims 1 to 7.
9. A display device characterized by comprising the display panel according to claim 8.
10. The manufacturing method of the array substrate comprises the manufacturing of an active layer, a grid electrode, a source electrode and a drain electrode, and is characterized by further comprising the following steps:
manufacturing a shielding layer on a substrate through a composition process, wherein the outline of an orthographic projection area of the shielding layer on the substrate is larger than the outline of an orthographic projection area of the active layer on the substrate;
manufacturing a first via hole and/or a second via hole on the shielding layer, wherein the position of the first via hole corresponds to the position of the source electrode in contact with the active layer, and the position of the second via hole corresponds to the position of the drain electrode in contact with the active layer; the orthographic projection area of the first through hole on the substrate is larger than or equal to the orthographic projection area of the area, contacting the source electrode with the active layer, of the substrate; the orthographic projection area of the second through hole on the substrate is larger than or equal to the orthographic projection area of the region, in contact with the active layer, of the drain electrode on the substrate; the orthographic projection area of the first through hole on the substrate base plate is equal to the orthographic projection area of the second through hole on the substrate base plate;
the manufacturing method also comprises the manufacturing of a common electrode wire, wherein the common electrode wire and the shielding layer are manufactured and formed by adopting the same composition process; or the common electrode wire and the grid electrode are manufactured and formed by the same composition process; the common electrode line is electrically connected with the shielding layer.
11. The manufacturing method according to claim 10, wherein after the first via and/or the second via is/are formed on the shielding layer, the method specifically comprises:
manufacturing an insulating layer on the shielding layer;
and sequentially manufacturing an active layer, a gate insulating layer, a gate, an interlayer insulating layer, a source and a drain on the insulating layer by a composition process.
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