WO2020192083A1

WO2020192083A1 - Display panel

Info

Publication number: WO2020192083A1
Application number: PCT/CN2019/110544
Authority: WO
Inventors: 郭旺回
Original assignee: 武汉华星光电半导体显示技术有限公司
Priority date: 2019-03-28
Filing date: 2019-10-11
Publication date: 2020-10-01
Also published as: CN110047880B; CN110047880A

Abstract

A display panel, which is provided with a transparent display region (111) and a conventional display region (112). The display panel comprises a touch control layer (400) and a light-shielding layer (500), and the light-shielding layer (500) is disposed on the touch control layer (400) and is located in the transparent display region (111).

Description

Display panel

Technical field

This application relates to the technical field of display panels, in particular to a display panel.

Background technique

In order to achieve a larger screen-to-body ratio of mobile phones, or even a full screen, the structural design of placing the camera below the display area of the display panel has become a mainstream research direction, but there are still many technical problems that need to be overcome. First of all, the imaging quality of the camera is an important measure. The current main research direction is to improve the light transmittance of the transparent display area.

technical problem

By reducing the pixel density (PPI) of the transparent display area, the transmittance can be increased and the imaging quality can be improved. However, during the experiment, there are the following problems: the diffraction of light generated by the slits between the grid-like metal traces of each layer Or diffraction makes the camera image blur, so a method is needed to overcome the above problems.

Technical solutions

The purpose of this application is to provide a display panel that includes an array substrate, an organic light-emitting device layer, a thin-film encapsulation layer, a touch layer, and a light-shielding layer that are stacked and arranged. The touch control layer is located in the transparent display area; the array substrate includes at least one first metal layer and at least one second metal layer that are insulated from each other. The light-shielding layer can ensure that no light passes through the metal traces of the transparent display area, avoiding diffraction or diffraction of light at the metal traces to cause blurry imaging of the transparent display area, and does not affect the organic light emission of the transparent display area. The display of the device layer improves the imaging quality of the camera.

In order to achieve the above objectives, the application adopts the following technical solutions.

The present application provides a display panel having a transparent display area and a conventional display area surrounding the transparent display area. The display panel includes:

An array substrate, the array substrate including at least one first metal layer and at least one second metal layer that are insulated from each other;

An organic light-emitting device layer, the organic light-emitting device layer is disposed on the array substrate;

A thin film encapsulation layer, the thin film encapsulation layer is disposed on the organic light emitting device layer and covers the organic light emitting device layer;

A touch layer, the touch layer is disposed on the thin film packaging layer; and,

A light shielding layer, the light shielding layer is disposed on the touch layer and located in the transparent display area;

And wherein, the first metal layer is a gate and a metal trace on the same layer as the gate, and the second metal layer is a source and drain and a metal trace on the same layer as the source and drain; The light shielding layer is made of an organic photoresist material with a light transmittance of less than 20%.

Further, the array substrate includes:

A base substrate, the base substrate including a first substrate layer, an inorganic film layer and a second substrate layer;

A thin film transistor layer, the thin film transistor layer includes at least one thin film transistor disposed on the base substrate;

A flat layer, the flat layer is disposed on the thin film transistor layer and covers the thin film transistor layer;

A pixel definition layer, the pixel definition layer is disposed on the flat layer and has at least one via;

At least one pixel electrode, the pixel electrode is disposed on the pixel definition layer and corresponds to the thin film transistor.

Further, the thin film transistor layer includes:

A buffer layer, the buffer layer is disposed on the base substrate and covers the base substrate;

An active layer, the active layer is disposed on the buffer layer;

A first gate insulating layer, the first gate insulating layer being disposed on the active layer and covering the active layer and the buffer layer;

A first layer of the first metal layer, the first layer of the first metal layer disposed on the first gate insulating layer;

A second gate insulating layer, the second gate insulating layer being disposed on the first metal layer and covering the first metal layer; and,

A second metal layer, the second metal layer being disposed on the second gate insulating layer.

Further, the thin film transistor layer further includes between the second gate insulating layer and the second metal layer:

A second layer of the first metal layer, the second layer of the first metal layer disposed on the second gate insulating layer; and,

A dielectric layer, the dielectric layer is disposed on the second layer of the first metal layer, and covers the second layer of the first metal layer and the second gate insulating layer.

Further, the pixel electrode is connected to the source or drain in the second metal layer of the corresponding thin film transistor through the via hole of the pixel definition layer, and the pixel electrode is a transparent electrode.

Further, the organic light emitting device layer includes at least one organic light emitting device, and the organic light emitting device includes:

A hole transport layer, the hole transport layer is disposed on the pixel electrode,

A light-emitting layer, the light-emitting layer is disposed on the hole transport layer,

An electron transport layer, the electron transport layer is disposed on the light-emitting layer, and,

A cathode layer, the cathode layer is arranged on the electron transport layer.

Further, the thin film encapsulation layer includes a first inorganic layer, an organic layer, and a second inorganic layer that are stacked.

Further, the touch control layer is disposed on the second inorganic layer of the thin film encapsulation layer, and includes a first insulating layer, a third metal layer, a second insulating layer, and a fourth A metal layer and a passivation organic layer, and the light shielding layer is disposed on the passivation organic layer of the touch layer.

A display panel having a transparent display area and a conventional display area surrounding the transparent display area, the display panel comprising:

A touch layer, the touch layer is disposed on the film packaging layer;

A light-shielding layer The light-shielding layer is disposed on the touch layer and located in the transparent display area.

Further, the light shielding layer is made of black organic photoresist material.

Further, the black organic photoresist material is an organic photoresist material with a light transmittance of less than 20%.

Further, the first metal layer is a gate electrode and a metal trace on the same layer as the gate electrode.

Further, the second metal layer is source and drain electrodes and metal traces in the same layer as the source and drain electrodes.

Further, the array substrate includes:

Further, the thin film transistor layer includes:

An active layer, the active layer is disposed on the buffer layer;

A first gate insulating layer, the first gate insulating layer being disposed on the first gate insulating layer;

A second gate insulating layer, the second gate insulating layer is disposed on the first layer of the first metal layer, and covers the first layer of the first metal layer and the first gate Polar insulating layer

Further, the thin film transistor layer further includes between the second gate insulating layer and the second metal layer: a second layer of the first metal layer, and the second layer of the first metal layer Arranged on the second gate insulating layer; and,

Further, the organic light emitting device layer includes a plurality of organic light emitting devices, and each of the organic light emitting devices includes:

A cathode layer, the cathode layer is arranged on the electron transport layer.

Further, the touch layer includes a first insulating layer, a third metal layer, a second insulating layer, a fourth metal layer, and a passivation organic layer stacked in sequence, and the light shielding layer is disposed on the On the passivation organic layer of the touch layer.

Beneficial effect

The advantage of the present invention is that, in terms of the imaging quality of the camera, a light-shielding layer is provided on the touch layer of the transparent display area, so that the light-shielding layer and the first metal layer of the transparent display area are wired in the first direction Corresponding to the metal traces in the second direction of the second metal layer, it can ensure that no light passes through the metal traces in the transparent display area, and avoid diffraction or diffraction of light by the traces. The light shielding layer does not affect the display of the organic light-emitting device layer corresponding to the transparent display area, and improves the imaging quality of the camera.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

FIG. 1 is a plan view of a transparent display area and a conventional display area of a display panel of the present invention.

2 is a schematic diagram of the structure of the display panel of the present invention in a transparent display area.

FIG. 3 is a schematic diagram of the structure of the array substrate of the display panel of the present invention in the conventional display area.

Embodiments of the invention

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of the present invention.

The terms "first", "second", "third", etc. (if any) in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and not necessarily used to describe a specific order Or precedence. It should be understood that the objects described in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations of them are intended to cover non-exclusive inclusion.

In this patent document, the drawings discussed below and various embodiments used to describe the principle of the disclosure of the present invention are only for illustration, and should not be construed as limiting the scope of the disclosure of the present invention. Those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged system. Exemplary embodiments will be described in detail, and examples of these embodiments are shown in the drawings. In addition, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings refer to the same elements.

The terms used in the specification of the present invention are only used to describe specific embodiments, and are not intended to show the concept of the present invention. Unless there is a clearly different meaning in the context, the expression used in the singular form encompasses the expression in the plural form. In the specification of the present invention, it should be understood that terms such as "including", "having" and "containing" are intended to indicate the possibility of the features, numbers, steps, actions or combinations thereof disclosed in the specification of the present invention, but not The possibility that one or more other features, numbers, steps, actions or combinations thereof may exist or may be added is excluded. The same reference numerals in the drawings refer to the same parts.

1, the present invention discloses an organic light emitting display panel, the display panel has a transparent display area 111 and a conventional display area 112 surrounding the transparent display area 111, the transparent display area 111 corresponds to the position of the camera Wherein, the transparent display area 111 has a lower pixel density, and the conventional display area 112 has a higher pixel density.

2, in the transparent display area 111, the display panel includes an array substrate 100; an organic light emitting device layer 200, the organic light emitting device layer 200 is disposed on the array substrate 100; and a thin film encapsulation layer 300, the thin film encapsulation layer 300 is disposed on the organic light emitting device layer 200 and covers the organic light emitting device layer 200; a touch layer 400, the touch layer 400 is disposed on the thin film encapsulation layer 300; And, a light-shielding layer 500, the light-shielding layer 500 is disposed on the touch layer 400 and located in the transparent display area 111, the light-shielding layer 500 is a black organic photoresist material, the black organic The photoresist material is an organic photoresist material with a light transmittance of less than 20%. In this embodiment, metallic molybdenum (Mo) is used to prepare the light shielding layer 500.

1 and 2, in this embodiment, the array substrate 100 includes at least one first metal layer 113 and at least one second metal layer 114 that are insulated from each other. The first metal layer 113 is a gate and Metal traces in the same layer as the gate, the second metal layer 114 is source and drain and metal traces in the same layer as the source and drain, and the first metal layer 113 has at least one first direction Metal trace 115, the second metal layer 114 has at least one second direction metal trace 116; the light shielding layer 500 corresponds to the first direction metal trace 115 and the second direction metal trace 116 .

As shown in Fig. 2, in the embodiment of the display panel of the present invention, in the transparent display area 111, the array substrate 100 includes a base substrate 1, a buffer layer 2, at least one thin film transistor 110, The dielectric layer 6, a second metal layer 7, a flat layer 9, a pixel definition layer 10 and a pixel electrode layer 12, the specific embodiment of the array substrate 100 is as follows.

As shown in Figure 2, in the embodiment of the array substrate 100 of the present invention, the base substrate 1 includes a first substrate layer 101, an inorganic film layer 102, and a second substrate layer 101, an inorganic film layer 102, and a second substrate layer 101, which are sequentially deposited on a glass substrate (not shown). The substrate layer 103, the first substrate layer 101 and the second substrate layer 103 are made of flexible plastic substrate PI material or PET material, the inorganic film layer 102 is made of SiNx&a-Si, the first substrate The thickness of the layer 101 is 10 um, the thickness of the inorganic film layer 102 is 500 nm, and the thickness of the second substrate layer 103 is 6 um.

As shown in Figure 2, the buffer layer 2 is arranged on the base substrate 1, the buffer layer 2 is set as a first buffer layer 21 and a second buffer layer 22, and the buffer layer 2 is made of SiNx or SiO2. It can also be made of SiNx and SiO2 laminated materials. The thickness of the buffer layer 2 is 500nm. It should be mentioned that, as other embodiments of the present invention, the buffer layer 2 can be ignored, that is, In other words, there is no need to provide the structure of the buffer layer 2 on the base substrate 1.

As shown in FIG. 2, at least one thin film transistor 110 is provided in the transparent display area 111. In one embodiment, the thin film transistor 110 is a double gate thin film transistor, and the thin film transistor 110 includes an active layer 3. , A first gate insulating layer 41, a first layer of the first metal layer 51, a second gate insulating layer 42, a second layer of first metal layer 52, and a second metal layer 7.

Specifically, in the transparent display region 111, a plurality of the active layers 3 are disposed on the buffer layer 2, the active layer 3 may be an oxide semiconductor layer, and the active layer 3 is at least Contains one of indium, gallium, and zinc, the thickness of the active layer 3 is 45 nm, the buffer layer 2 as described above can be ignored, and the active layer 3 can be directly prepared on the base substrate 1 on.

The first gate insulating layer 41 is disposed on the base substrate 1 and the active layer 3 and covers the base substrate 1 and the active layer 3. The first gate insulating layer 41 It is composed of SiNx or SiO2, and the thickness of the one gate insulating layer 41 is 130 nm.

A plurality of the first metal layers 51 are arranged on the first gate insulating layer 41, and the first metal layers 51 of the first layer are arranged in a one-to-one correspondence with the active layer 3, so The first metal layer 51 of the first layer is made of Mo, and the thickness of the first metal layer 51 of the first layer is 250 nm.

The second gate insulating layer 42 covers the first layer of the first metal layer 51 and the first gate insulating layer 41, and the second gate insulating layer 42 is made of SiNx or SiO2, so The thickness of the second gate insulating layer 42 is 110 nm.

A plurality of the second layer of the first metal layer 52 is disposed on the second gate insulating layer 42, the second layer of the first metal layer 52 and the first layer of the first metal layer The layers 51 are arranged in a one-to-one correspondence and are arranged opposite to each other. The first metal layer 52 of the second layer is made of Mo, and the thickness of the first metal layer 52 of the second layer is 250 nm.

The dielectric layer 6 is disposed after the second gate insulating layer 42 and the second layer of the first metal layer 52. As shown in FIG. 2, the dielectric layer 6 covers the second layer The thickness of the first metal layer 52 and the second gate insulating layer 42 and the dielectric layer 6 is 500 nm.

The second metal layer 7 includes a plurality of source electrodes 7a and drain electrodes 7b, and the source electrodes 7a and drain electrodes 7b are arranged on the dielectric layer 6 at intervals and penetrate through the dielectric layer 6, the second The gate insulating layer 42 and the first gate insulating layer 41 are in contact with both ends of the active layer 3 respectively.

As shown in Figure 2, the flat layer 9 is provided on the dielectric layer 6, the source electrode 7a and the drain electrode 7b, and the flat layer 9 covers the dielectric layer 6, the thin film transistor 110 The thickness of the flat layer 9 is 1.5 um, and the flat layer 9 can protect the thin film transistor 110 from water and oxygen.

As shown in Figure 2, a pixel definition layer 10 is provided on the flat layer 9, and at least one via hole 11 is provided on the pixel definition layer 10. The via hole 11 is in the shape of an inverted trapezoid groove, and the pixel defines At least one PS photoresist 13 is further provided on the layer 10, and the thickness of the pixel definition layer 10 and the thickness of the PS photoresist 13 are both 1.5 um.

As shown in FIG. 2, a pixel electrode layer 12 is provided on the pixel definition layer 10. The pixel electrode layer 12 is electrically connected to the source and drain layer 7 through the via hole 11, and the pixel electrode layer 12 At the same time, it is also the anode layer of the OLED. The pixel electrode layer 12 is set as a transparent electrode to facilitate the observation of light-emitting display conditions. The thickness of the pixel electrode layer 12 is 140 nm.

In this embodiment, a double-gate thin film transistor is used. It should be particularly noted that in other embodiments, the present invention does not exclude that the thin film transistor is in the form of a top gate, a low gate, or other types of double gates. Those skilled in the art can choose the specific form according to the desired effect.

3, in the conventional display area 112, the array substrate 100 is different from the array substrate 100 of the transparent display area 111. The present invention provides a specific embodiment of the display panel in the conventional display area 112. The difference of the embodiment is that the thin film transistor 110 of the array substrate 100 is a double-gate dual-source-drain thin-film transistor, so the dielectric layer 6, the flat layer 9 and the source-drain layer 7 are different.

Specifically, as shown in FIG. 3, in the conventional display area 112, the dielectric layer 6 of the array substrate 100 is configured as a first dielectric layer 61 and a second dielectric layer 62. A dielectric layer 61 covers the second layer of the first metal layer 52 and the second gate insulating layer 42, the second dielectric layer 62 is disposed on the first dielectric layer 61, so The thickness of the first dielectric layer 61 is 300 nm, the thickness of the second dielectric layer 62 is 200 nm; a first and the second metal layer 71 is provided on the second dielectric layer 62, and the second A second metal layer 71 includes a first source 71a and a first drain 71b. Both the first source 71a and the first drain 71b penetrate the second dielectric layer 62, the A dielectric layer 61, a second gate insulating layer 42, and a first gate insulating layer 41 are in contact with both ends of the active layer 3, and the thickness of the first and second metal layers 71 are all 600 nm .

3, in the conventional display area 112, the array substrate 100 further includes a passivation layer 8, the passivation layer 8 is formed on the second dielectric layer 62 and the first On the second metal layer 71 and covering the first source electrode 71a and the first drain electrode 71b, the thickness of the passivation layer 8 is 250 nm.

3, in the conventional display area 112 also has a pad area 117, the buffer layer 2, the first gate insulating layer 41, the first gate insulating layer 42, The first dielectric layer 61 and the second dielectric layer 62 are provided with an opening area 63, and an organic dielectric layer is filled in the opening area 63, and the organic dielectric layer is in contact with the second dielectric layer of the substrate 1. The surface of the substrate layer 103 is in contact, the opening area 63 is in the shape of an inverted trapezoid step, and the thickness of the opening area 63 is 1500 nm, so as to improve the flexibility and bending strength.

3, in the conventional display area 112, the flat layer 9 of the array substrate 100 is provided with a first flat layer 91 and a second flat layer 92, the first flat layer 91 covers the passivation Layer 8, the second dielectric layer 62, the opening region 63 and the first source and drain layer 71 exposed by the pad region 114; a second flat layer 91 is provided on the first flat layer 91 The second metal layer 72 penetrates through the second flat layer 92, the passivation layer 8 and is connected to the first source of the first metal layer 71 The electrode 71a or the first drain electrode 71b is in contact; the second flat layer 92 is provided on the first flat layer 91 and covers the second second metal layer 72, and at the same time serves as the pixel electrode of the anode layer The layer 12 is in contact with the second metal layer 72. In this embodiment, the thickness of the first flat layer 91 and the thickness of the second flat layer 92 are both 1.5 um, and the thickness of the second second metal layer 72 is 600 nm.

It should be noted that, according to the present invention, the source electrode 7a and the drain electrode 7b of the second metal layer 7 shown in FIG. 2 and the first source electrode 71a of the first and second metal layer 71 shown in FIG. The first drain 71b and the second second metal layer 72 can be enlightened by those skilled in the art. In the thin film transistor 110, n+ layer source 7a, drain 7b and use The n+ layer second metal layer 7 is used as a wiring layer.

2, in the transparent display area 111, the organic light emitting device layer 200 of the display panel of the present invention is arranged on the side of the array substrate 100 away from the thin film transistor 110, and the organic light emitting device layer 200 is provided with At least one organic light emitting device (not numbered), each of the organic light emitting device layers 200 includes a hole transport layer 201, a light emitting layer 202, an electron transport layer 203, a cathode layer 204, a capping layer 205 and a modification Layer (LiF) 206, the organic light emitting device layer 200 has light emitting materials of different colors.

As shown in Figure 2, the thin film encapsulation layer 300 of the display panel of the present application covers the organic light emitting device layer 200. The thin film encapsulation layer 300 includes a first inorganic layer 301, an organic layer 302, and a second inorganic layer 303. The first inorganic layer 301 is prepared by the CVD1 method and the preparation material is SIN, the organic layer 302 is prepared by the IJP method and the preparation material is organic material, and the second inorganic layer 303 is prepared by the CVD2 method and the preparation material is SIN.

As shown in FIG. 2, in the transparent display area 111, the touch layer 400 of the display panel of the present invention is disposed on the thin film encapsulation layer 300, and the touch layer 400 includes a first insulating layer stacked in sequence. Layer 401, a third metal layer 402, a second insulating layer 403, a fourth metal layer 404, and a passivation organic layer 405, wherein the first insulating layer 401 and the second insulating layer 403 are composed of The thickness of the third metal layer 402 is made of metal Ti/Al/Ti, and the thickness of the third metal layer 402 is 50/200/80 nm. The thickness of the third metal layer 402 is 50/200/80 nm. The metal layer 404 also includes three layers made of metal Ti/Al/Ti materials, and the thickness of the fourth metal layer 404 is 50/200/50 nm respectively; the organic passivation layer 405 is made of organic materials and has a thickness of 2um.

Therefore, in the display panel of the present invention, in the transparent display area 111, after the array substrate 100, the organic light emitting device layer 200, the thin film encapsulation layer 300, and the touch layer 400 are prepared in sequence, A light-shielding layer 500 is provided on the touch layer 400, and two insulating layers of the first metal layer 113 and a second metal layer 114 are provided on the array substrate 100, and the first metal layer 113 is the first metal layer. Layer of the first metal layer 51, the second layer of the first metal layer 52, and the first layer of the first metal layer 51 and the second layer of the first metal layer 52 in the first direction Metal traces 115, the second metal layer 114 is the source 7a/drain 7b and the second direction metal trace 116 of the second metal layer 7. The light shielding layer 500 corresponds to the first direction metal wiring 115 and the second direction metal wiring 116, and the light shielding layer 500 can ensure the first direction metal wiring of the transparent display area 111 No light passes through the metal traces 115 and 116 in the second direction, which prevents the diffraction or diffraction of light at the metal traces from making the transparent display image blur, and the light shielding layer 500 does not affect the transparent display area 111 The light-emitting display of the organic light-emitting device layer 200 improves the imaging quality of the camera.

In summary, after the display panel of the present application has completed the preparation of the array substrate 100, the organic light emitting device layer 200, the thin film encapsulation layer 300 and the touch layer 400 in the transparent display area 111, a light shielding layer 400 is provided on the touch layer 400 The light-shielding layer 500 corresponds to the metal trace 115 in the first direction and the metal trace 116 in the second direction, so as to ensure that no light passes through the metal traces of the transparent display area 111 and avoid metal traces. Diffraction or diffraction of light at the line makes the camera image blur, and at the same time does not affect the display of the organic light emitting device layer 200 in the transparent display area 111, which improves the imaging quality of the camera.

Industrial applicability

The subject of this application can be manufactured and used in industry and has industrial applicability.

Claims

A display panel having a transparent display area and a conventional display area surrounding the transparent display area, wherein the display panel includes:

An array substrate, the array substrate including at least one first metal layer and at least one second metal layer that are insulated from each other;

An organic light-emitting device layer, the organic light-emitting device layer is disposed on the array substrate;

A thin-film encapsulation layer, the thin-film encapsulation layer is disposed on the organic light-emitting layer and covers the organic light-emitting device layer;

A touch layer, the touch layer is disposed on the thin film packaging layer; and,

A light shielding layer, the light shielding layer is disposed on the touch layer and located in the transparent display area;

And wherein, the first metal layer is a gate and a metal trace on the same layer as the gate, and the second metal layer is a source and drain and a metal trace on the same layer as the source and drain; The light shielding layer is made of an organic photoresist material with a light transmittance of less than 20%.
The display panel of claim 1, wherein the array substrate comprises:

A base substrate, the base substrate including a first substrate layer, an inorganic film layer and a second substrate layer;

A thin film transistor layer, the thin film transistor layer includes at least one thin film transistor disposed on the base substrate;

A flat layer, the flat layer is disposed on the thin film transistor layer and covers the thin film transistor layer;

A pixel definition layer, the pixel definition layer is disposed on the flat layer and has at least one via;

At least one pixel electrode, the pixel electrode is disposed on the pixel definition layer and corresponds to the thin film transistor.
3. The display panel of claim 2, wherein the thin film transistor layer comprises:

A buffer layer, the buffer layer is disposed on the base substrate and covers the base substrate;

An active layer, the active layer is disposed on the buffer layer;

A first gate insulating layer, the first gate insulating layer being disposed on the active layer and covering the active layer and the buffer layer;

A first layer of the first metal layer, the first layer of the first metal layer disposed on the first gate insulating layer;

A second gate insulating layer, the second gate insulating layer being disposed on the first metal layer and covering the first metal layer; and,

A second metal layer, the second metal layer being disposed on the second gate insulating layer.
3. The display panel of claim 3, wherein the thin film transistor layer further comprises between the second gate insulating layer and the second metal layer:

A second layer of the first metal layer, the second layer of the first metal layer disposed on the second gate insulating layer; and,

A dielectric layer, the dielectric layer is disposed on the second layer of the first metal layer, and covers the second layer of the first metal layer and the second gate insulating layer.
4. The display panel of claim 3, wherein the pixel electrode is connected to the source or drain in the second metal layer of the corresponding thin film transistor through the via hole of the pixel definition layer , The pixel electrode is a transparent electrode.
The display panel according to claim 1, wherein the organic light emitting device layer comprises at least one organic light emitting device, and the organic light emitting device comprises:

A hole transport layer, the hole transport layer is disposed on the pixel electrode,

A light-emitting layer, the light-emitting layer is disposed on the hole transport layer,

An electron transport layer, the electron transport layer is disposed on the light-emitting layer, and,

A cathode layer, the cathode layer is arranged on the electron transport layer.
4. The display panel of claim 1, wherein the thin film encapsulation layer comprises a first inorganic layer, an organic layer, and a second inorganic layer that are stacked.
The display panel according to claim 1, wherein the touch layer is disposed on the second inorganic layer of the thin-film encapsulation layer, and comprises a first insulating layer and a third metal layer stacked in sequence , A second insulating layer, a fourth metal layer and a passivation organic layer, the light shielding layer is disposed on the passivation organic layer of the touch layer.
A display panel having a transparent display area and a conventional display area surrounding the transparent display area, wherein the display panel includes:

An array substrate, the array substrate including at least one first metal layer and at least one second metal layer that are insulated from each other;

An organic light-emitting device layer, the organic light-emitting device layer is disposed on the array substrate;

A thin film encapsulation layer, the thin film encapsulation layer is disposed on the organic light emitting device layer and covers the organic light emitting device layer;

A touch layer, the touch layer is disposed on the thin film packaging layer; and,

A light-shielding layer, the light-shielding layer is disposed on the touch layer and located in the transparent display area.
9. The display panel of claim 9, wherein the light shielding layer is made of a black organic photoresist material.
10. The display panel of claim 10, wherein the black organic photoresist material is an organic photoresist material with a light transmittance of less than 20%.
9. The display panel of claim 9, wherein the first metal layer is a gate electrode and a metal trace on the same layer as the gate electrode.
9. The display panel of claim 9, wherein the second metal layer is source and drain electrodes and metal traces in the same layer as the source and drain electrodes.
The display panel of claim 9, wherein the array substrate comprises:

A base substrate, the base substrate including a first substrate layer, an inorganic film layer and a second substrate layer;

A thin film transistor layer, the thin film transistor layer includes at least one thin film transistor disposed on the base substrate;

A flat layer, the flat layer is disposed on the thin film transistor layer and covers the thin film transistor layer;

A pixel definition layer, the pixel definition layer is disposed on the flat layer and has at least one via;

At least one pixel electrode, the pixel electrode is disposed on the pixel definition layer and corresponds to the thin film transistor.
15. The display panel of claim 14, wherein the thin film transistor layer comprises: a buffer layer, the buffer layer being disposed on the base substrate and covering the base substrate;

An active layer, the active layer is disposed on the buffer layer;

A first gate insulating layer, the first gate insulating layer being disposed on the active layer and covering the active layer and the buffer layer;

A first layer of the first metal layer, the first layer of the first metal layer disposed on the first gate insulating layer;

A second gate insulating layer, the second gate insulating layer is disposed on the first layer of the first metal layer, and covers the first layer of the first metal layer and the first gate Polar insulating layer

A second metal layer, the second metal layer being disposed on the second gate insulating layer.
15. The display panel of claim 15, wherein the thin film transistor layer further comprises a second layer of the first metal layer between the second gate insulating layer and the second metal layer, so The second layer and the first metal layer are disposed on the second gate insulating layer; and,

A dielectric layer, the dielectric layer is disposed on the second layer of the first metal layer, and covers the second layer of the first metal layer and the second gate insulating layer.
14. The display panel of claim 14, wherein the pixel electrode is connected to the source or drain in the second metal layer of the corresponding thin film transistor through the via hole of the pixel definition layer , The pixel electrode is a transparent electrode.
10. The display panel of claim 10, wherein the organic light emitting device layer comprises at least one organic light emitting device, and the organic light emitting device comprises:

A hole transport layer, the hole transport layer is disposed on the pixel electrode,

A light-emitting layer, the light-emitting layer is disposed on the hole transport layer,

An electron transport layer, the electron transport layer is disposed on the light-emitting layer, and,

A cathode layer, the cathode layer is arranged on the electron transport layer.
10. The display panel of claim 10, wherein the thin film encapsulation layer comprises a first inorganic layer, an organic layer, and a second inorganic layer that are stacked.
10. The display panel of claim 10, wherein the touch layer comprises a first insulating layer, a third metal layer, a second insulating layer, a fourth metal layer, and a passivation organic layer stacked in sequence. Layer, the light shielding layer is arranged on the passivation organic layer of the touch layer.