CN114613815A

CN114613815A - Display panel and manufacturing method thereof

Info

Publication number: CN114613815A
Application number: CN202210195317.XA
Authority: CN
Inventors: 胡凯
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2022-06-10
Anticipated expiration: 2042-03-01
Also published as: CN114613815B

Abstract

The invention discloses a display panel and a manufacturing method thereof, wherein the display panel comprises: the array substrate is positioned in the GOA area and the display area; the organic light-emitting layer is arranged on the array substrate and comprises a first electrode layer, a second electrode layer and a light-emitting material layer, the light-emitting material layer is arranged between the first electrode layer and the second electrode layer, and the light-emitting material layer is positioned in the display area; the first electrode layer is located in the display area and extends to the GOA area. The first electrode layer is located in the display area and extends to the GOA area. And the second electrode layer is positioned in the display area and extends to the GOA area. Therefore, the influence caused by H ion diffusion in the packaging layer is blocked, and the negative bias failure problem of the GOA circuit is improved.

Description

Display panel and manufacturing method thereof

Technical Field

The invention relates to the technical field of display panels, in particular to a display panel and a manufacturing method thereof.

Background

At present, an Organic Light Emitting Diode (OLED) display panel has the advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of nearly 180 degrees, a wide use temperature range and the like, can realize large-area full-color display, is expected to become a next generation flat panel display technology following the LCD display technology, and is one of the technologies which attracts much attention in the flat panel display technology. An Active Matrix Organic Light Emitting Diode (AMOLED) display panel is one of OLED display panels, and mainly includes Thin Film Transistors (TFTs) and OLEDs.

With the continuous development of display technologies, the AMOLED technology is more and more applied to flexible displays, flexible product packages are completely protected by TFE, but a TFE film layer contains H ions, and the phenomenon of H ion diffusion can occur in a high-temperature or aging process.

Disclosure of Invention

The invention aims to provide a display panel and a manufacturing method thereof, which can solve the problem that the GOA circuit is invalid because no metal layer is arranged on the GOA area for protection and the device is easy to be negatively biased due to H ion diffusion.

According to an aspect of the present invention, there is provided a display panel including: the array substrate is positioned in the GOA area and the display area; the organic light-emitting layer is arranged on the array substrate and comprises a first electrode layer, a second electrode layer and a light-emitting material layer, the light-emitting material layer is arranged between the first electrode layer and the second electrode layer, and the light-emitting material layer is positioned in the display area; the first electrode layer is located in the display area and extends to the GOA area.

Further, the second electrode layer is located in the display area and extends to the GOA area.

Further, the array substrate includes: a substrate base plate; a light shielding layer disposed on the substrate; the buffer layer is arranged on the substrate and the shading layer; an active layer disposed on the buffer layer; a gate insulating layer disposed on the active layer; a gate electrode layer disposed on the gate insulating layer; an interlayer insulating layer disposed on the buffer layer, the active layer and the gate electrode layer; the source drain electrode layer is arranged on the interlayer insulating layer and is connected with the active layer through a through hole; the passivation layer is arranged on the interlayer insulating layer and the source drain electrode layer; and a planarization layer disposed on the passivation layer.

Furthermore, thin film transistors are formed by the active layer, the gate insulating layer, the gate layer and the source drain electrode layer, the thin film transistors are located in the display area and the GOA area, and the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the thin film transistors located in the GOA area on the substrate.

Further, the display panel further includes: and the packaging layer is arranged on the organic light-emitting layer.

According to another aspect of the present invention, there is also provided a method of manufacturing a display panel, the method including: providing an array substrate; depositing a first electrode layer on the array substrate, wherein the first electrode layer covers the display area and the GOA area; and depositing a layer of light emitting material on the first electrode layer; and evaporating a second electrode layer on the light-emitting material layer.

Further, the second electrode layer covers the display area and the GOA area.

Further, the providing an array substrate includes: providing a substrate base plate; forming a light-shielding layer on the substrate base plate; forming a buffer layer on the substrate and the light-shielding layer; forming an active layer on the buffer layer; forming a gate insulating layer on the active layer; forming a gate electrode layer on the gate insulating layer; forming an interlayer insulating layer on the buffer layer, the active layer and the gate electrode layer; forming a source drain electrode layer on the interlayer insulating layer and connecting the source drain electrode layer with the active layer through a through hole; forming a passivation layer on the interlayer insulating layer and the source drain electrode layer; and forming a planarization layer on the passivation layer.

Further, a thin film transistor is formed by the active layer, the gate insulating layer, the gate layer and the source drain electrode layer, the thin film transistor is located in the display area and the GOA area, and an orthographic projection of the first electrode layer on the substrate covers an orthographic projection of the thin film transistor located in the GOA area on the substrate.

Further, the method further comprises: and forming an encapsulation layer on the second electrode layer.

The display device has the advantages that the first electrode layer is positioned in the display area and extends to the GOA area. And the second electrode layer is positioned in the display area and extends to the GOA area. Therefore, the influence caused by H ion diffusion in the packaging layer is blocked, and the negative bias failure problem of the GOA circuit is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a display panel according to a second embodiment of the present invention;

fig. 3 is a flowchart illustrating a method for manufacturing a display panel according to a third embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.

Fig. 1 is a schematic view of a display panel structure according to an embodiment of the present invention. The display panel includes: an array substrate 100 and an organic light emitting layer 200.

Illustratively, the array substrate 100 is located in the GOA area 300 and the display area 400, the organic light emitting layer 200 is disposed on the array substrate 100, the organic light emitting layer 200 includes a first electrode layer 11, a second electrode layer 13 and a light emitting material layer 12, the light emitting material layer 12 is disposed between the first electrode layer 11 and the second electrode layer 13, the light emitting material layer 12 is located in the display area 400, and the first electrode layer 11 is located in the display area 400 and extends to the GOA area 300.

Wherein the array substrate 100 includes: the semiconductor device includes a substrate 10, a light-shielding layer 20, a buffer layer 30, an active layer 40, a gate insulating layer 50, a gate layer 60, an interlayer insulating layer 70, a source/drain electrode layer 80, a passivation layer 90, and a planarization layer 91.

Illustratively, the light shielding layer 20 is disposed on the substrate 10, which may be a flexible PI layer. The buffer layer 30 is disposed on the substrate 10 and the light-shielding layer 20, and for example, SiOx or SiNx thin film is deposited as the buffer layer 30.

Illustratively, the active layer 40 is disposed on the buffer layer 30, for example, IGZO is deposited as the active layer 40, In: ga: zn is 1:1:1 ratio, thickness 200-.

Illustratively, a gate insulating layer 50 is disposed on the active layer 40, a gate layer 60 is disposed on the gate insulating layer 50, and the gate layer 60 is formed by deposition, and may be made of Mo, Al, Cu, Ti, etc., with a thickness of 2000-.

In some embodiments, a yellow light is used to etch the gate layer 60, and then the gate insulating layer 50 is etched using the gate layer 60 with a self-aligned pattern, and a Plasma (Plasma) process is performed on the entire surface, so that the resistance is significantly reduced after the portion of the active layer 40 not protected by the gate insulating layer 50 and the gate layer 60 is processed, thereby forming an N + conductive layer, and the gate insulating layer 50 and the active layer 40 below the gate layer 60 are not processed, thereby maintaining the semiconductor characteristics and functioning as a conductive channel layer of the tft.

Illustratively, the interlayer insulating layer 70 is disposed on the buffer layer 30, the active layer 40 and the gate layer 60, and the interlayer insulating layer 70 is formed by deposition, for example, and may be a SiOx or SiNx film with a thickness of 2000A-10000A, and defines source and drain contact regions of the tft, and defines the anti-crack diffusion holes 21 in the bending region by using a mask.

Illustratively, the source drain electrode layer 80 is disposed on the interlayer insulating layer 70 and connected to the active layer 40 through the via 22, for example, the source drain electrode layer 80 is formed by deposition, and the material thereof may be Mo, Al, Cu, Ti, etc., with a thickness of 2000-.

Illustratively, the passivation layer 90 is disposed on the interlayer insulating layer 70 and the source/drain electrode layer 80, and the passivation layer 90 is formed by deposition, for example, and may be SiOx or SiNx thin film with a thickness of 1000-.

Illustratively, a planarization layer 91 is disposed on the passivation layer 90. The planarization layer 91 is formed, for example, by coating, to a thickness of 2-4 um.

Illustratively, a thin film transistor is formed by the active layer 40, the gate insulating layer 50, the gate layer 60 and the source drain electrode layer 80, the thin film transistor is located in the display region 400 and the GOA region 300, and an orthographic projection of the first electrode layer 11 on the substrate 10 covers an orthographic projection of the thin film transistor located in the GOA region 300 on the substrate 10. For example, depositing the first electrode layer 11, and defining the pattern of the display area 400 and the GOA area 300 through a mask, the first metal layer in the GOA area 300 needs to cover the thin film transistor in the GOA area 300. Wherein the first metal layer is an anode layer and the second metal layer is a cathode layer.

Organic materials are deposited again to form the light emitting material layer 12, and a light emitting region of the light emitting material layer 12 is defined by the pixel defining layer 23.

Illustratively, an encapsulation layer 24 is disposed on the organic light emitting layer 200. During development, the stability of the film needs to be improved during the manufacturing process, and the H-containing gas is added to the encapsulation layer 24 during the manufacturing process.

In the first embodiment, the first electrode layer 11 is located in the display region 400 and extends to the GOA region 300. Therefore, the influence caused by H ion diffusion in the packaging layer 24 is blocked, and the negative bias failure problem of the GOA circuit is improved.

Fig. 2 is a schematic view of a display panel structure according to an embodiment of the present invention. The display panel includes: an array substrate 100 and an organic light emitting layer 200.

Illustratively, the array substrate 100 is located in the GOA area 300 and the display area 400, the organic light emitting layer 200 is disposed on the array substrate 100, the organic light emitting layer 200 includes a first electrode layer 11, a second electrode layer 13 and a light emitting material layer 12, the light emitting material layer 12 is disposed between the first electrode layer 11 and the second electrode layer 13, the light emitting material layer 12 is located in the display area 400, and the first electrode layer 11 is located in the display area 400 and extends to the GOA area 300. The second electrode layer 13 is located in the display area 400 and extends to the GOA area 300.

Illustratively, a gate insulating layer 50 is disposed on the active layer 40, a gate layer 60 is disposed on the gate insulating layer 50, and the gate layer 60 is deposited, wherein the material may be Mo, Al, Cu, Ti, etc., and the thickness is 2000-.

In some embodiments, the gate insulating layer 50 is etched by first etching the pattern of the gate layer 60 using a yellow light, and then etching the pattern of the gate layer 60 in a self-aligned manner; the entire surface Plasma (Plasma) treatment is performed so that the resistance is significantly reduced after the portion of the active layer 40 not protected by the gate insulating layer 50 and the gate layer 60 is treated, thereby forming an N + conductive layer, and the portion of the active layer 40 under the gate insulating layer 50 and the gate layer 60 is not treated, thereby maintaining the semiconductor characteristics and functioning as a conductive channel layer of the thin film transistor.

Illustratively, the source/drain electrode layer 80 is disposed on the interlayer insulating layer 70 and connected to the active layer 40 through the via 22, for example, the source/drain electrode layer 80 is formed by deposition, and may be made of Mo, Al, Cu, Ti, etc., and has a thickness of 2000-.

Illustratively, a thin film transistor is formed by the active layer 40, the gate insulating layer 50, the gate layer 60 and the source drain electrode layer 80, the thin film transistor is located in the display region 400 and the GOA region 300, and an orthographic projection of the first electrode layer 11 on the substrate 10 covers an orthographic projection of the thin film transistor located in the GOA region 300 on the substrate 10. For example, depositing the first electrode layer 11, and defining the pattern of the display area 400 and the GOA area 300 through a mask, the first electrode layer 11 in the GOA area 300 needs to cover the thin film transistor in the GOA area 300. The second electrode layer 13 is formed by vapor deposition, and extends to the GOA region 300 by enlarging the cathode region, thereby protecting the GOA region 300. Wherein the first metal layer is an anode layer and the second metal layer is a cathode layer.

In an embodiment, the first electrode layer is disposed in the display region and extends to the GOA region. And the second electrode layer is positioned in the display area and extends to the GOA area. Therefore, the influence caused by H ion diffusion in the packaging layer is blocked, and the negative bias failure problem of the GOA circuit is improved.

Fig. 3 is a flowchart illustrating steps of a method for manufacturing a display panel according to an embodiment of the present invention. The method comprises the following steps:

step S310: an array substrate is provided.

Illustratively, the providing an array substrate includes:

a substrate is provided, which may illustratively be a flexible PI layer.

Forming a light-shielding layer on the substrate.

Buffer layers are formed on the substrate and the light-shielding layer, illustratively by depositing SiOx or SiNx films as buffer layers.

Forming an active layer on the buffer layer, illustratively, depositing IGZO as the active layer, In: ga: zn is 1:1:1 ratio, thickness 200-.

A gate insulating layer is formed on the active layer, and a gate layer is formed on the gate insulating layer, illustratively, by deposition, which may be Mo, Al, Cu, Ti, etc., with a thickness of 2000-.

In some embodiments, a gate layer pattern is etched using a yellow light, and then the gate insulating layer is etched using the gate layer pattern as a self-alignment; and performing Plasma (Plasma) treatment on the whole surface, so that the resistance of the part without the gate insulating layer and the gate layer protection above the active layer is obviously reduced after treatment, and an N + conductor layer is formed, and the active layer below the gate insulating layer and the gate layer is not treated, so that the semiconductor characteristic is kept and the semiconductor is used as a thin film transistor conducting channel layer.

Forming an interlayer insulating layer on the buffer layer, the active layer and the gate electrode layer, illustratively, forming the interlayer insulating layer by deposition, wherein the material of the interlayer insulating layer can be SiOx or SiNx film, the thickness of the interlayer insulating layer is 2000A-10000A, a source drain contact area of the thin film transistor is defined, and an anti-crack diffusion hole is defined in the bending area by using a photomask.

Forming a source drain electrode layer on the interlayer insulating layer, connecting the source drain electrode layer with the active layer through a via hole, illustratively, forming the source drain electrode layer through deposition, wherein the material of the source drain electrode layer can be Mo, Al, Cu, Ti and the like, the thickness is 2000-8000A, and then defining a graph.

A passivation layer is formed on the interlayer insulating layer and the source and drain electrode layers, and is formed by deposition, wherein the passivation layer can be made of SiOx or SiNx film with a thickness of 1000-5000A.

A planarization layer is formed on the passivation layer, illustratively by coating, to a thickness of 2-4 um.

Step S320: and depositing a first electrode layer on the array substrate, wherein the first electrode layer covers the display area and the GOA area.

Illustratively, a thin film transistor is formed by the active layer, the gate insulating layer, a gate layer and a source drain electrode layer, the thin film transistor is located in the display region and the GOA region, and an orthographic projection of the first electrode layer on the substrate covers an orthographic projection of the thin film transistor located in the GOA region on the substrate. For example, a first electrode layer is deposited, and patterns of a display area and a GOA area are defined through a photomask, wherein a first metal layer in the GOA area needs to cover the thin film transistor in the GOA area. And depositing organic material to form light emitting material layer, and defining light emitting region of the light emitting material layer via the pixel defining layer. Wherein the first metal layer is an anode layer and the second metal layer is a cathode layer.

Step S330: depositing a layer of light emitting material on the first electrode layer.

Illustratively, an organic material is deposited, a light emitting material layer is formed, and a light emitting region of the light emitting material layer is defined by the pixel defining layer.

Step S340: and evaporating a second electrode layer on the light-emitting material layer.

In some other embodiments, the second electrode layer covers the display region and the GOA region. For example, the second electrode layer is formed by evaporation, and the cathode region is enlarged and extended to the GOA region to protect the GOA region.

Step S350: and forming an encapsulation layer on the second electrode layer.

Illustratively, an encapsulation layer is disposed on the organic light emitting layer. During development, the stability of the film needs to be improved during the process, and the H-containing gas is increased in the packaging layer during the process.

In an embodiment, the first electrode layer is located in the display region and extends to the GOA region. And the second electrode layer is positioned in the display area and extends to the GOA area. Therefore, the influence caused by H ion diffusion in the packaging layer is blocked, and the negative bias failure problem of the GOA circuit is improved.

The foregoing detailed description is directed to a display panel provided by an embodiment of the present invention, and the principles and embodiments of the present invention are described herein by using specific examples, which are merely used to help understand the method and the core concept of the present invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A display panel, comprising:

the array substrate is positioned in the GOA area and the display area;

the organic light-emitting layer is arranged on the array substrate and comprises a first electrode layer, a second electrode layer and a light-emitting material layer, the light-emitting material layer is arranged between the first electrode layer and the second electrode layer, and the light-emitting material layer is positioned in the display area;

the first electrode layer is located in the display area and extends to the GOA area.

2. The display panel according to claim 1, wherein the second electrode layer is located in the display region and extends to the GOA region.

3. The display panel according to claim 1, wherein the array substrate comprises:

a substrate base plate;

a light shielding layer disposed on the substrate;

the buffer layer is arranged on the substrate and the shading layer;

an active layer disposed on the buffer layer;

a gate insulating layer disposed on the active layer;

a gate electrode layer disposed on the gate insulating layer;

an interlayer insulating layer disposed on the buffer layer, the active layer and the gate electrode layer;

the source drain electrode layer is arranged on the interlayer insulating layer and is connected with the active layer through a through hole;

the passivation layer is arranged on the interlayer insulating layer and the source drain electrode layer; and

and the flat layer is arranged on the passivation layer.

4. The display panel according to claim 3, wherein a thin film transistor is formed by the active layer, the gate insulating layer, a gate layer, and a source drain electrode layer, the thin film transistor is located in the display region and the GOA region, and an orthographic projection of the first electrode layer on the substrate covers an orthographic projection of the thin film transistor located in the GOA region on the substrate.

5. The display panel according to claim 1, further comprising: and the packaging layer is arranged on the organic light-emitting layer.

6. A method for manufacturing a display panel is characterized by comprising the following steps:

providing an array substrate;

depositing a first electrode layer on the array substrate, wherein the first electrode layer covers the display area and the GOA area; and

depositing a layer of light emitting material on the first electrode layer;

and evaporating a second electrode layer on the light-emitting material layer.

7. The method according to claim 6, wherein the second electrode layer covers the display region and the GOA region.

8. The method of claim 6, wherein the providing an array substrate comprises:

providing a substrate base plate;

forming a light-shielding layer on the substrate base plate;

forming a buffer layer on the substrate and the light-shielding layer;

forming an active layer on the buffer layer;

forming a gate insulating layer on the active layer;

forming a gate electrode layer on the gate insulating layer;

forming an interlayer insulating layer on the buffer layer, the active layer and the gate electrode layer;

forming a source drain electrode layer on the interlayer insulating layer and connecting the source drain electrode layer with the active layer through a through hole;

forming a passivation layer on the interlayer insulating layer and the source drain electrode layer; and

a planarization layer is formed on the passivation layer.

9. The manufacturing method of the display panel according to claim 8, wherein a thin film transistor is formed by the active layer, the gate insulating layer, the gate layer and the source drain electrode layer, the thin film transistor is located in the display region and the GOA region, and an orthographic projection of the first electrode layer on the substrate covers an orthographic projection of the thin film transistor located in the GOA region on the substrate.

10. The method for manufacturing a display panel according to claim 6, further comprising:

and forming an encapsulation layer on the second electrode layer.