KR20100068644A - Top emission type organic electro luminescent device and method of fabricating the same - Google Patents

Abstract

PURPOSE: A top emission type organic electro luminescent device and a method of fabricating the same are provided to prevent the deterioration of image quality due to partial brightness uniform by reducing the internal resistance of a second electrode. CONSTITUTION: A semiconductor layer, comprising of a driving area(DA), a first area(113a) and a semiconductor layer(113), is formed on the first top of a substrate. A gate insulating layer(116) is formed over the semiconductor. A gate electrode(120) is formed on the gate insulating layer. A switching thin film transistor and driving thin-film transistor are formed in a pixel region(P) on a first substrate. A drain contact hole(143) exposes the drain electrode(136) of the driving thin-film transistor to the outside.

Description

Top emission type organic electroluminescent device and method of manufacturing the same {Top emission type organic electroluminescent device and method of fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic electroluminescent device, and in particular, to reduce the internal resistance of the second electrode formed on the front surface of the top in an upper light emitting type structure to prevent display quality degradation due to uneven luminance of each part. It relates to a top emission type organic light emitting device and a method of manufacturing the same.

The organic light emitting diode, which is one of the flat panel displays (FPDs), has high luminance and low operating voltage characteristics. In addition, the self-luminous self-illuminating type provides high contrast ratio, enables ultra-thin display, easy response time with several microsecond response time, no restriction on viewing angle, and stable at low temperatures. Since it is driven at a low voltage of 5 to 15V DC, it is easy to manufacture and design a driving circuit.

In addition, the manufacturing process of the organic light emitting device is very simple because the deposition (deposition) and encapsulation (encapsulation) equipment is all.

The organic light emitting diode having such characteristics is largely divided into a passive matrix type and an active matrix type. In the passive matrix method, since the scan lines and the signal lines cross each other to form a device in a matrix form, each pixel Since the scan lines are sequentially driven over time in order to drive, the instantaneous luminance must be equal to the average luminance multiplied by the number of lines in order to represent the required average luminance.

However, in the active matrix method, a thin film transistor, which is a switching element for turning on / off a pixel, is positioned for each subpixel, and the first electrode connected to the thin film transistor is The second electrode, which is turned on / off in subpixel units and faces the first electrode, becomes a common electrode.

In the active matrix method, a voltage applied to a pixel is charged in a storage capacitor (C _ST ), so that power is applied until the next frame signal is applied, thereby relating to the number of scan lines. Run continuously for one screen without Therefore, since low luminance, high definition, and large size can be obtained even when a low current is applied, an active matrix type organic light emitting diode is mainly used in recent years.

Hereinafter, the basic structure and operation characteristics of the active matrix organic light emitting display device will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of one pixel of a typical active matrix organic electroluminescent device.

As shown, one pixel of the active matrix organic light emitting diode is a switching thin film transistor STr, a driving thin film transistor DTr, a storage capacitor StgC, and an organic light emitting diode E. Is made of.

That is, the gate line GL is formed in the first direction, is formed in the second direction crossing the first direction to define the pixel region P, and the data line DL is formed. A power supply line PL is formed to be spaced apart from the DL and to apply a power supply voltage.

In addition, a switching thin film transistor STr is formed at a portion where the data line DL and the gate wiring GL cross, and a driving thin film transistor DTr electrically connected to the switching thin film transistor STr is formed. have. The first electrode, which is one terminal of the organic light emitting diode E, is connected to the drain electrode of the driving thin film transistor DTr, and the second electrode, which is the other terminal, is connected to the power supply line PL. In this case, the power line PL transfers a power supply voltage to the organic light emitting diode E. In addition, a storage capacitor StgC is formed between the gate electrode and the source electrode of the driving thin film transistor DTr.

Therefore, when a signal is applied through the gate line GL, the switching thin film transistor STr is turned on, and the signal of the data line DL is transferred to the gate electrode of the driving thin film transistor DTr to drive the driving signal. Since the thin film transistor DTr is turned on, light is output through the organic light emitting diode E. At this time, when the driving thin film transistor DTr is in an on state, the level of the current flowing from the power supply line PL to the organic light emitting diode E is determined, and thus the organic light emitting diode E is The gray scale may be implemented, and the storage capacitor StgC maintains the gate voltage of the driving thin film transistor DTr constant when the switching thin film transistor STr is turned off. As a result, even when the switching thin film transistor STr is turned off, the level of the current flowing through the organic light emitting diode E may be maintained until the next frame.

The organic light emitting device for driving is classified into a top emission type and a bottom emission type according to the transmission direction of light emitted through the organic light emitting diode. In this case, the lower emission method has a problem that the aperture ratio is lowered, and thus, the upper emission method has been mainly used in recent years.

2 is a schematic cross-sectional view of a conventional top-emitting organic light emitting display device.

As illustrated, the first and second substrates 10 and 70 are disposed to face each other, and the edge portions of the first and second substrates 10 and 70 are sealed by a seal pattern 80. In addition, a driving thin film transistor DTr is formed in each pixel region P on the first substrate 10, and a first electrode 47 is formed by being connected to each of the driving thin film transistors DTr. The organic light emitting layer 55 is connected to the driving thin film transistor DTr on the first electrode 47 and includes a light emitting material corresponding to red, green, and blue colors. Is formed, and the second electrode 58 is formed on the entire surface of the organic light emitting layer 55. In this case, the first and second electrodes 47 and 58 serve to apply an electric field to the organic light emitting layer 55.

The second electrode 47 and the second substrate 58 formed on the first substrate 10 are spaced apart by a predetermined interval by the seal pattern 80 described above.

3 is a cross-sectional view of one pixel area including the driving thin film transistor of the above-described top emission type organic light emitting diode.

As shown, on the first substrate 10, the semiconductor layer 13, the gate insulating film 16, and the gate electrode composed of the first region 13a of pure polysilicon and the second region 13b doped with impurities 20), an interlayer insulating film 23 having a semiconductor layer contact hole 25 exposing the second region 13b, and source and drain electrodes 33 and 36 are sequentially stacked to form a driving thin film transistor DTr. The source and drain electrodes 33 and 36 are connected to a power supply wiring (not shown) and an organic light emitting diode E, respectively.

In addition, the organic light emitting diode E includes a first electrode 47 and a second electrode 58 facing each other with the organic light emitting layer 55 interposed therebetween. In this case, the first electrode 47 is formed in contact with one electrode of the driving thin film transistor DTr for each pixel region P, and the second electrode 58 is formed on the entire surface of the organic light emitting layer 55. It is becoming.

In addition, the second substrate 70 is configured to face the first substrate 10 having the above-described structure for encapsulation.

On the other hand, the first electrode 47 is an indium-tin-oxide (ITO) or indium, which is a transparent conductive material having a high work function value to serve as an anode electrode, especially when the driving thin film transistor DTr is p type. It is made of zinc oxide (IZO), and the second electrode 58 is made of a metal material having a low work function value to serve as a cathode electrode.

However, since the metal material having a low work function value constituting the second electrode 58 serving as a cathode electrode has opaque properties, the opaque metal may have a thickness of a general electrode or an insulating layer, that is, thousands of microwatts. If it is formed in the thickness of light can not transmit.

Accordingly, the second electrode serving as the cathode electrode cannot be formed to have a thickness corresponding to a general electrode thickness, whereby the second electrode formed on the front surface has a luminance distribution due to a voltage drop due to its internal resistance. The defect which becomes nonuniform arises.

On the other hand, when the driving thin film transistor is formed of n type, the second electrode is formed of a transparent conductive material having a relatively high work function value to serve as an anode electrode. As the distance from the applied portion increases, a voltage distribution unevenness occurs due to a voltage drop according to the internal resistance of the second electrode made of a transparent conductive material.

The present invention has been made to solve the above problems, the present invention is due to the voltage drop due to the internal resistance of the second electrode of the organic light emitting diode formed on the uppermost layer of the organic light emitting device of the top emission method It aims at preventing a brightness nonuniformity phenomenon.

According to an aspect of the present invention, there is provided a top emission organic light emitting device, including: a first substrate; Gate and data lines formed on the first substrate to define pixel regions by crossing each other with an insulating layer therebetween; A common wiring formed on the first substrate on the same layer with the gate wiring spaced apart from the gate wiring; A switching thin film transistor and a driving thin film transistor formed in the pixel area on the first substrate; A protective layer formed on the pixel region, the protective layer having a drain contact hole covering the switching and driving thin film transistor and exposing a drain electrode of the driving thin film transistor and a first common contact hole exposing the common wiring; A common auxiliary pattern formed in contact with the common electrode through the first common contact hole and spaced apart from the first electrode formed in contact with the drain electrode of the driving thin film transistor through the drain contact hole on the passivation layer in the pixel area; and; A bank overlapping an edge of the first electrode and having a second common contact hole exposing the common auxiliary pattern at a boundary of the pixel region; A partition wall having an inverse taper shape at an upper end of the bank, the upper end of which is located outside the second common contact hole, and the side wall of which covers the second common contact hole; A first organic layer formed on an upper surface of the bank, the first electrode, and the partition without any pixel region; An organic light emitting layer formed in an area surrounded by the bank above the first organic layer; A second electrode covering one side surface and an upper surface of the barrier rib on the organic emission layer and contacting the common auxiliary pattern through the second common contact hole without division of a pixel area; A second substrate facing the first substrate; And seal patterns formed along edges of the first and second substrates.

A reflective plate may be formed between the protective layer and the first electrode, and an auxiliary electrode may be formed on the front surface of the second electrode using a transparent conductive material.

Preferably, a second organic layer is formed between the organic light emitting layer and the second electrode to improve the luminous efficiency of the organic light emitting layer.

The first organic layer has a double layer structure of a hole injection layer / hole transporting layer or a double layer structure of an electron injection layer / electron transporting layer. In this case, the second organic layer is a double layer of an electron transporting layer / electron injection layer when the first organic layer is a hole injection layer / hole transporting layer. When the first organic layer is an electron injection layer / electron transporting layer, it has a double layer structure of a hole transporting layer / hole injection layer. Is characteristic.

The first substrate may include a power line disposed parallel to the layer on which the data line is formed, and the gate and the data line may be connected to a gate electrode and a source electrode of the switching thin film transistor, respectively.

In the method of manufacturing the top emission type organic light emitting device according to the present invention, a gate and a data wiring are formed on the first substrate to form a pixel area crossing each other with an insulating layer therebetween to define a pixel region, and the same gate wiring is formed. Forming common wiring spaced apart in parallel to the gate wiring in the layer and power wiring spaced apart in parallel to the data wiring in the same layer on which the data wiring is formed; Forming a switching thin film transistor connected to a gate and a data line and a driving thin film transistor electrically connected to the pixel region on the first substrate; Forming a protective layer covering the switching and driving thin film transistor and having a drain contact hole exposing a drain electrode of the driving thin film transistor and a first common contact hole exposing the common wiring; A common auxiliary pattern is formed on the passivation layer in the pixel area, the first electrode contacting the drain electrode of the driving thin film transistor through the drain contact hole, the common auxiliary pattern contacting the common wiring through the first common contact hole. Making a step; Forming a bank overlapping an edge of the first electrode and having a second common contact hole exposing the common auxiliary pattern at a boundary of the pixel region; Forming a partition wall having an inverse taper shape on an end surface of the bank, the top end of which is located outside the second common contact hole, and the side wall of which covers the second common contact hole; Forming a first organic layer by performing vertical thermal deposition on the front surface of the bank, the first electrode, and the partition wall; Forming an organic emission layer by performing thermal deposition on the region surrounded by the bank above the first organic layer by using a shadow mask; The deposition particles do not enter the substrate surface perpendicularly to the substrate surface but are subjected to thermal evaporation or ion beam deposition such that oblique incidence is deposited so as to cover one side and the upper surface of the partition wall and the pixel region is not classified. Forming a second electrode contacting the common auxiliary pattern through a common contact hole; Opposing the first substrate so as to face the second substrate, forming a seal pattern along an edge, and bonding the first and second substrates together.

Forming the first electrode includes forming a reflector between the first electrode and the protective layer.

In the deposition for forming the second electrode, an angle between the direction in which the deposition particles are incident and the surface of the substrate is 20 to 70 degrees.

The organic light emitting diode according to the present invention includes a contact hole in each pixel area so that a second electrode formed on the front of the display area through the contact hole contacts the VDD wiring made of a low resistance metal material at the bottom. Therefore, there is an effect of preventing partial luminance unevenness in the display area by suppressing the distance difference from the portion to which the voltage is applied and the voltage strengthening caused by the internal resistance.

In addition, due to the formation of the VDD wiring serving as the auxiliary electrode of the second electrode in the display area, the internal resistance of the second electrode is lowered, thereby reducing power consumption.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a cross-sectional view of one pixel area including a driving thin film transistor and an organic light emitting diode, according to an exemplary embodiment of the present invention. 6 is a cross-sectional view of a pixel area including a driving thin film transistor and an organic light emitting diode according to a modified example of the embodiment, and FIG. A partial plan view of one pixel area of the top emission type organic light emitting diode is shown. In this case, for convenience of description, the region in which the driving thin film transistor DTr is formed is defined as the driving region DA and the region in which the switching thin film transistor is formed, although not shown in the drawing, is called a switching region.

As shown in FIG. 4, the top emission type organic light emitting diode 101 according to the present invention includes a first substrate 110 in which a driving and switching thin film transistor DTr (not shown) and an organic light emitting diode E are formed. ) And a second substrate 170 for encapsulation.

First, the configuration of the first substrate 110 will be described.

The first substrate 100 is formed of pure polysilicon corresponding to the driving area DA and the switching area (not shown), and a central part thereof includes a first area 113a forming a channel and the first area 113a. The semiconductor layer 113 including the second region 113b doped with a high concentration of impurities is formed at both sides. In this case, a buffer layer (not shown) made of an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) may be further formed between the semiconductor layer 113 and the first substrate 110. . The buffer layer (not shown) is to prevent deterioration of the characteristics of the semiconductor layer 113 due to the release of alkali ions from the inside of the first substrate 110 when the semiconductor layer 113 is crystallized.

In addition, a gate insulating layer 116 is formed on the entire surface of the semiconductor layer 113, and the gate electrode 116 is formed on the gate insulating layer 116 to correspond to the first region 113a of the semiconductor layer 113. 120 is formed. In addition, the gate insulating layer 116 is connected to a gate electrode (not shown) formed in the switching region (not shown), extends in one direction, and a gate wiring (not shown) is formed. In parallel with each other, a VDD line 122 is formed to apply a common signal voltage to the second electrode.

In addition, an interlayer insulating layer 123 is formed over the gate electrode 120, the gate line (not shown), and the VDD line 122. In this case, the interlayer insulating layer 123 and the gate insulating layer 116 thereunder are formed with a semiconductor layer contact hole 125 exposing each of the second regions 113b located on both sides of the first region 113a. .

Next, on the interlayer insulating layer 123 including the semiconductor layer contact hole 125, a data line 130 crossing the gate line (not shown) to define the pixel region P, and a power line spaced apart from the data line 130. (Not shown) is being formed. In addition, the driving area DA and the switching area (not shown) are spaced apart from each other on the interlayer insulating layer 123 and contact the second area 113b exposed through the semiconductor layer contact hole 125, respectively. Drain electrodes 133 and 136 are formed. In this case, the semiconductor layer 113 including the source and drain electrodes 133 and 136, the second region 113b in contact with the electrodes 133 and 136, and a gate formed on the semiconductor layer 113. The insulating layer 116 and the gate electrode 120 form a driving thin film transistor DTr and a switching thin film transistor (not shown), respectively. In this case, the switching thin film transistor (not shown) is electrically connected to the driving thin film transistor DTr, the gate line (not shown), and the data line (not shown). The data line (not shown) is connected to a source electrode (not shown) of the switching thin film transistor (not shown).

In this case, the driving and switching thin film transistor DTr (not shown) forms a p-type or n-type thin film transistor according to the impurities doped in the second region 113b. In the case of the p-type thin film transistor, the second region 113b is formed by doping an element of Group 3, for example, boron (B). In the case of the n-type thin film transistor, the group 5 is formed in the second region 113b. This is done by doping an element of eg phosphorus (P). The p-type thin film transistor uses holes as a carrier, and the n-type thin film transistor uses electrons as a carrier.

Therefore, the first electrode 147 connected to the drain electrode 136 of the driving thin film transistor DTr serves as an anode or a cathode according to the type of the driving thin film transistor DTr. When the driving thin film transistor DTr is p type, the first electrode 147 serves as an anode electrode, and when n type, the first electrode 147 serves as a cathode electrode.

The passivation layer 140 is formed on a front surface of the driving and switching thin film transistor DTr (not shown). In this case, a drain contact hole 143 exposing the drain electrode 136 of the driving thin film transistor DTr is formed in the passivation layer 140, and the passivation layer 140 is formed in each pixel area P. Referring to FIG. A first common contact hole 144 exposing the VDD wiring 122 is further provided by patterning the lower insulating interlayer 123.

On the other hand, in the above-described embodiment, a driving and switching thin film transistor having a top gate type including a region doped with group 3 or group 5 elements is formed using polysilicon as a semiconductor layer. Referring to the cross-sectional view of one pixel region of the top emission type organic light emitting diode according to the modification of the embodiment of the present invention, the bottom gate type driving and switching thin film using pure and impurity amorphous silicon as the semiconductor layer 119. Transistor DTr (not shown) may be formed.

In this modified example, a gate wiring (not shown) is formed in one direction on the first substrate 110, and the VDD wiring 114 is spaced apart from the gate wiring (not shown).

In addition, a gate electrode 112 is formed in each switching region and a driving region (not shown, DA), and covers the gate wiring (not shown), the VDD wiring 114 and the gate electrode 112, and the gate is formed on the front surface thereof. The insulating film 115 is formed. In addition, a pixel line P is defined on the gate insulating layer 115 to cross the gate line (not shown), and a data line (not shown) is formed, and the driving and switching areas DA (not shown) are formed on the gate insulating layer 115. A semiconductor layer 119 composed of an ohmic contact layer 119b of impurity amorphous silicon, spaced apart from each other above the active layer 119a of pure amorphous silicon, and corresponding to the gate electrode 112, and above the semiconductor layer 119. Source and drain electrodes 121 and 123 are spaced apart from each other. In this case, the gate electrode 112, the gate insulating layer 115, and the source and drain electrodes 121 and 123 spaced apart from each other and sequentially stacked on the driving and switching region DA (not shown) are respectively driven and driven. A thin film transistor having a bottom gate structure using the pure and impurity amorphous silicon as the semiconductor layer 119 is formed as a switching thin film transistor DTr (not shown). Accordingly, the first electrode 147 connected to the drain electrode 123 of the driving thin film transistor DTr having the structure serves as a cathode electrode.

Although not shown in the drawing, the gate electrode of the switching thin film transistor is connected to the gate wiring, and the source electrode of the switching thin film transistor is connected to the data wiring.

A protective layer 140 having a drain contact hole 143 exposing the drain electrode 123 of the driving thin film transistor DTr is disposed on the switching and driving thin film transistor DTr having the bottom gate type structure. Formed. In this case, the passivation layer 140 and the gate insulating layer 115 under the patterned portion are provided with a first common contact hole 129 exposing the VDD wiring 114 for each pixel region P. FIG.

 In the modified example having the above structure, the structure formed on the passivation layer 140 is the same as the embodiment, and will be described below with reference to FIG. 4.

The drain electrode 136 of the driving thin film transistor DTr and the drain contact hole 143 are in contact with each other over the passivation layer 140 having the drain contact hole 143. The first auxiliary layer 148 is formed, and the common auxiliary pattern 148 contacting the VDD line 114 through the first common contact hole 144 is made of the same material forming the first electrode 147. Formed.

In this case, when the driving thin film transistor DTr is p-type, the first electrode 147 has a relatively large work function to serve as an anode electrode, and a transparent conductive material such as indium tin oxide (ITO) or indium. It is made of zinc oxide (IZO), and in this case, a reflecting plate (metal), for example, aluminum (Al) or silver (Ag) having excellent reflection efficiency under the first electrode 147 to improve reflection efficiency. May be further formed.

On the other hand, when the driving thin film transistor DTr is n type, the first electrode 147 is a metal material having a relatively small work function value, for example, aluminum (Al), aluminum alloy, or silver (Ag) to serve as a cathode electrode. ), Magnesium (Mg), and gold (Au), and the common auxiliary pattern 148 is also made of the same material as the first electrode 147. In the case of a metal material having a relatively low work function value, since it is an opaque material by itself, when it is formed to have a thickness of 500 Å or more, the transmittance is almost 0% of light, so a separate reflector (not shown) is required. I never do that.

Next, as described above, a bank 150 is formed on the boundary of each pixel region P on the first electrode 147. In this case, the bank 150 is formed to overlap the edge of the first electrode 147 in a form surrounding the pixel area P, and the common auxiliary pattern 148 provided in the pixel area P is provided. ), A second common contact hole 153 exposing the same is provided.

In addition, a partition wall 156 having an inverted tapered cross-section is formed on the bank 150 adjacent to the second common contact hole 153. At this time, the partition wall 156 having the reverse taper structure is characterized in that the planar shape completely covering the second common contact hole 153, as shown in FIG. That is, since the second common contact hole 153 is positioned below the side surface of the partition 156, the partition wall 156 is formed to completely overlap with the partition wall 156. In this case, the partition wall 156 does not have a shape that borders the pixel areas P along the banks 150 formed along the boundary of the pixel areas P, but the second common contact hole 153 It is characterized in that it is formed so as to completely cover only the portion formed.

On the other hand, the first organic layer 158 having a multi-layer structure is formed on the bank 150 to improve the luminous efficiency of the organic light emitting layer 160 without dividing each pixel region P corresponding to the entire display area. In this case, the first organic layer 158 is formed on the upper surface of the partition wall 156 to correspond to a portion where the partition wall 156 is formed by cutting off based on the top end of the partition wall 156 and the partition wall 156. It is characterized in that it is not formed corresponding to the second common contact hole 153 that is covered by.

In addition, an organic emission layer 160 is formed in each pixel area P surrounded by the bank 150 on the first organic layer 158 to correspond to the first electrode 147.

The second electrode 163 is formed on the entire display area above the first organic layer 158 corresponding to the portion where the organic emission layer 160 and the bank 150 are formed. In this case, the second electrode 163 is formed to contact the common auxiliary pattern 148 through the second common contact hole 153 disposed under the partition wall 156 provided in each pixel area P. It is characteristic that there is.

In this case, the first and second electrodes 147 and 163 and the first organic layer 158 and the organic emission layer 160 formed therebetween form an organic light emitting diode (E).

In this case, although not shown in the drawings, a second organic layer (not shown) having a multilayer structure may be further formed between the organic light emitting layer 160 and the second electrode 163 to improve the light emission efficiency of the organic light emitting layer 160. .

In this case, when the first electrode 147 serves as an anode, the first organic layer 158 of the multilayer is formed of a hole injection layer / hole transporting layer. When the first electrode 147 serves as a cathode electrode, the first electrode 147 is formed of an electron injection layer / electron transporting layer.

In addition, although the second organic layer (not shown) is not shown in the drawing, when the first electrode 147 serves as an anode, an electron transporting layer / electron injection is performed on the organic emission layer 160. It is made of a layer (electron injection layer), when the first electrode 147 serves as a cathode electrode is made of a hole transporting layer (hole transporting layer) / hole injection layer (hole injection layer) on the organic light emitting layer .

On the other hand, the second electrode 163 formed on the organic light emitting layer 160 is an example of a metal material having a relatively low work function value to serve as a cathode electrode when the first electrode 147 serves as an anode electrode For example, one of aluminum (Al), aluminum alloy, silver (Ag), magnesium (Mg), and gold (Au) is formed to have a thickness of several to tens of micrometers so that light can be transmitted therethrough. An auxiliary second electrode (not shown) may be further formed of the conductive material.

In addition, when the first electrode 147 serves as a cathode, the second electrode 163 may be an indium tin oxide (ITO), which is a transparent conductive material having a relatively large work function value to serve as an anode electrode. Alternatively, the indium-zinc oxide (IZO) may be formed to have a thickness of about several hundreds to thousands of microns.

The second substrate 170 of the transparent material is opposed to the first substrate 110 having such a structure and bonded together by a seal pattern (not shown) along the edge thereof, so that the top emission type organic light emitting device 101 according to the present invention. )

In the case of the top emission type organic light emitting device 101 according to the present invention having the above-described structure, the second electrode 163 formed on the entire surface of the display area penetrates the pixel area P under the low-resistance metal. A common signal voltage is applied to the second electrode 163 by contacting and electrically connected to the VDD line 114 made of a material and through the first and second common contact holes 144 and 153 provided in each pixel region P. The display unevenness caused by the voltage drop can be suppressed by the distance difference between the applied portion and the outermost portion of the display area adjacent to the center of the display area.

Hereinafter, a brief description will be given of a method of manufacturing the top emission type organic light emitting device according to the embodiment of the present invention described above. In the case of the modification, only the structure of the switching and driving thin film transistor is different, and the steps after the formation of the characteristic protective layer of the present invention are the same as in the embodiment, so only the manufacturing method of the embodiment will be described.

In the case of the embodiment of the present invention, since all the components are formed on the first substrate will be described mainly on the manufacturing method of the first substrate. In this case, a method of manufacturing a top emission type organic light emitting diode in which a first electrode connected to a drain electrode of the driving thin film transistor serves as an anode electrode and a second electrode serves as a cathode will be described as an example. In the case of the top emission type organic light emitting device in which the first electrode serves as the cathode electrode and the second electrode serves as the anode electrode, only the configuration of the metal materials constituting the electrodes and the first and second organic layers in contact therewith are manufactured. Since the method is the same, it is omitted here.

7A to 7I are cross-sectional views illustrating manufacturing steps of one pixel area of the top emission type organic light emitting diode according to the embodiment of the present invention.

First, as shown in FIG. 7A, amorphous silicon is deposited on the insulating substrate 110 to form an amorphous silicon layer (not shown), and the amorphous silicon layer is formed by irradiating a laser beam or performing heat treatment. Crystallization with a polysilicon layer (not shown). Subsequently, the polysilicon layer (not shown) is patterned by performing a mask process to form the semiconductor layer 113 in a pure polysilicon state. In this case, before forming the amorphous silicon layer (not shown), an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface of the insulating substrate 110 to form a buffer layer (not shown). It may be.

Next, silicon oxide (SiO ₂ ) is deposited on the semiconductor layer 113 of pure polysilicon to form a gate insulating layer 116. Thereafter, a low resistance metal material, for example, aluminum (Al), aluminum alloy (AlNd), copper (Cu), or a copper alloy is deposited on the gate insulating layer 116 to form a first metal layer (not shown). The mask process is performed to form the gate electrode 120 corresponding to the central portion of the semiconductor layer 113. In this case, a gate line (not shown) connected to a gate electrode (not shown) formed in a switching region (not shown) of the gate electrode 120 and extending in one direction is uniformly parallel to the gate line (not shown). The VDD wiring 122 is formed spaced apart from each other.

Next, by using the gate electrode 120 as a blocking mask, a dopant, i.e., a trivalent element or a pentavalent element, is doped on the entire surface of the substrate 110 to be positioned outside the gate electrode 120 of the semiconductor layer 113. A portion of the second region 113b doped with the impurity is formed, and a portion corresponding to the doped gate electrode 120 forms the first region 113a of pure polysilicon.

Next, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 110 on which the semiconductor layer 113 divided into the first and second regions 113a and 113b is formed. A semiconductor layer contact hole for exposing the second region 113b by simultaneously or collectively patterning the interlayer insulating layer 123 and the lower gate insulating layer 116 by performing a mask process. Forms 125.

Subsequently, a second metal layer is deposited on the interlayer insulating layer 123 by depositing one of a metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, chromium (Cr), and molybdenum (Mo). (Not shown), and a mask process is performed to pattern the source and drain electrodes 133 and 136 in contact with the second region 113b through the semiconductor layer contact hole 125. At the same time, the data line 130 is connected to a source electrode (not shown) formed in the switching region (not shown) on the interlayer insulating layer 123 and crosses the gate line (not shown) to define the pixel region P. In addition, a power line (not shown) formed to be spaced apart from the data line 130 is formed. In this case, the semiconductor layer 113, the gate insulating layer 116, the gate electrode 120, the interlayer insulating layer 123, and the source and drain electrodes 133 and 136 spaced apart from each other are switched and driven thin film transistors (not shown, DTr). To achieve.

Next, as shown in FIG. 7B, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the source and drain electrodes 133 and 136, or an organic insulating material such as photo A drain contact hole 143 exposing the drain electrode 136 of the driving thin film transistor DTr by applying photo acryl or benzocyclobutene (BCB) to form a protective layer 140 and patterning the protective layer 140. The first common contact hole 144 exposing the VDD wiring 122 is formed.

Meanwhile, in the modified example, a method of simply forming a driving and switching thin film transistor and a protective layer will be described with reference to FIG. 5.

A gate wiring that extends in one direction by depositing and patterning one of a low resistance metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), and copper alloy on the insulating substrate 110. ) And a VDD wiring 114 spaced apart from each other, and the gate electrode 112 is formed in the switching region and the driving region DA (not shown). In this case, a gate electrode (not shown) formed in the switching region (not shown) is connected to the gate line (not shown).

Next, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the gate line and the gate electrode 112 to form a gate insulating layer 115. Thereafter, an active layer 119a of pure amorphous silicon and an impurity amorphous silicon pattern (not shown) made of impurity amorphous silicon are formed on the gate insulating layer 115 to correspond to each gate electrode 112.

Next, by depositing and patterning a metal material on the entire surface of the impurity amorphous silicon pattern (not shown) and patterning it, the data line crossing the gate line (not shown) on the gate insulating layer 115 to define the pixel region P ( And a power line (not shown) spaced apart from and parallel to each other, and at the same time, source and drain electrodes 121 and 123 are spaced apart from each other on the impurity amorphous silicon pattern (not shown). In this case, a source electrode (not shown) formed in the switching region (not shown) is connected to the data line (not shown).

Next, the ohmic contact layer 119b is formed by removing the impurity amorphous silicon pattern (not shown) exposed between the source and drain electrodes 121 and 123. In this case, the gate electrode 112, the gate insulating layer 115, the semiconductor layer 119 including the active layer 119a and the ohmic contact layer 119b, and the source and drain electrodes 121 and 123 spaced apart from each other A switching or driving thin film transistor (DTr) is formed.

Next, the protective layer 140 is formed on the driving and switching thin film transistor DTr (not shown) formed as described above and patterned to expose the drain electrode 123 of the driving thin film transistor DTr. The hole 143 and the first common contact hole 144 exposing the VDD wiring 114 are formed. The process then follows the process in accordance with the embodiment.

Meanwhile, in an embodiment, as shown in FIG. 7C, indium is a transparent conductive material having a relatively high work function value over the protective layer 140 having the drain contact hole 143 and the first common contact hole 144. Tin-oxide (ITO) or indium-zinc-oxide (IZO) is deposited and patterned to have a thickness of about several thousand micrometers, and thus, the driving thin film transistor DTr through the drain contact hole 143 for each pixel region P. The first electrode 147 is in contact with the drain electrode 136 of the first electrode 136, and is simultaneously spaced apart from the first electrode 147 and is in contact with the VDD wiring 122 through the first common contact hole 144. The common auxiliary pattern 148 is formed. At this time, although not shown in the drawing, before forming the first electrode 147, a metal material having excellent reflection characteristics for each pixel region P on the protective layer 140 to improve luminous efficiency, for example, aluminum (Al). ) Or silver (Ag), and then a reflective plate (not shown) may be further formed below the first electrode 147 by depositing and patterning the transparent conductive material. In this case, the common auxiliary pattern 148 also has a double layer structure.

Subsequently, as illustrated in FIG. 7D, a first organic insulating material, for example, photo acryl or benzocyclobutene (BCB) is coated on the first electrode 147 to form a first organic insulating material layer (not shown). A bank 150 having a second common contact hole 153 exposing each pixel region P and exposing the common auxiliary pattern 148 by forming a pattern.

Next, as shown in FIG. 7E, the second organic insulating material layer is coated to form a second organic insulating material layer (not shown), and patterned to form a bank located at one side boundary corresponding to each pixel area P. FIG. A partition wall 156 having an inverted taper cross section is formed on the 150 adjacent to the second common contact hole 153.

Formation of the partition wall 156 having such an inverse taper structure is possible by using an organic insulating material having negative photosensitive characteristics. The negative photosensitive material that remains when the lighted part is developed is a strong chemical reaction with light depending on the amount and time of light irradiation in the area to be irradiated so that it cannot be removed during development. 2 When light is irradiated onto the organic insulating material layer (not shown), a difference in the amount of light reaching the surface and the bottom thereof occurs. Therefore, when developed after exposure based on these characteristics, the cross-sectional structure has an inverse taper structure due to the difference in the degree of reaction with light.

In this case, the partition wall 156 is formed such that an upper end of the partition wall 156 is located outside the second common contact hole 153 formed in the bank 150, and the second common contact hole 153 is covered by the upper surface and the side surface. It is characteristic.

Next, as shown in FIG. 7F, the first organic layer is increased to increase the luminous efficiency of the organic light emitting layer 160 of FIG. 7G on the first electrode 147 exposed to the substrate 110 on which the partition wall 156 is formed. The material is formed through thermal evaporation. In this case, the thermal evaporation of the first organic material may be performed such that the deposited particles are incident perpendicularly to the surface of the substrate 110. Therefore, the first organic layer 158 formed by the vertical thermal deposition is formed on the entire display area without distinguishing each pixel area P, and corresponds to a portion where the partition wall 156 of each pixel area P is formed. In this case, the deposition is performed only on the upper surface of the partition wall 156 and is not deposited corresponding to the second common contact hole 153 located below the upper surface.

Next, as shown in FIG. 7G, the shadow mask 190 having the opening TA and the blocking area BA is positioned to correspond to the substrate 110 on which the first organic layer 158 is formed, and thereby the organic light is disposed. The organic light emitting layer 160 is formed in a region surrounded by the bank 150 in each pixel region P by thermally depositing a light emitting material using a shadow mask (not shown). In this case, the organic light emitting layer 160 may be formed to include red, green, and blue organic light emitting patterns (not shown) emitting red, green, and blue, or may be formed of only the white organic light emitting patterns 160 emitting white. It may be. When the organic light emitting pattern is composed of red, green, and blue organic light emitting patterns (not shown), thermal evaporation is performed using three shadow masks 190. When only the white organic light emitting pattern 160 is formed, one shadow mask 190 is used. Thermal evaporation is performed. In the drawing, the white organic light emitting pattern 160 is formed as an example.

In the case of thermal deposition using the shadow mask 190, the organic light emitting layer 160 is formed only at a portion corresponding to the opening BA of the shadow mask 190, so that the organic light emitting layer is formed with respect to the second common contact hole 153. 160 is not formed.

Next, as shown in FIG. 7H, a metal material having a relatively small work function value on the organic emission layer 160, for example, aluminum (Al), aluminum alloy, silver (Ag), magnesium (Mg), and gold (Au) The second electrode 163 is formed to have a relatively thin thickness on the front surface by performing thermal deposition or ion beam deposition. In this case, the thermal evaporation or ion beam deposition of the metal material is not inclined perpendicularly to the surface of the substrate 110 on which the deposition is performed, but is oblique to the direction of motion of the deposited particles. The substrate 110 has an angle of 20 to 70 degrees with respect to the direction of movement so that the particles to be deposited are obliquely incident on the surface of the substrate 110. Accordingly, the particles to be deposited with respect to the surface of the substrate 110 are not vertically incident, but are deposited to have a predetermined inclination to be deposited to one side portion of the partition wall 156, and at the bottom of the upper surface of the partition wall 156. The deposition of the second common contact hole 153 is performed to form a second electrode 163 contacting the common auxiliary pattern 148 through the second common contact hole 153. to be.

By the manufacturing method, the second electrode 163 is formed on the entire display area, and finally contacts the common auxiliary pattern 148 through the second common contact hole 153 for each pixel area P. It is electrically connected to the VDD wiring 122. Therefore, the second electrode 163 has a structure in which the common signal voltage is applied to each pixel region P through the plurality of common auxiliary patterns 148, so that the voltage drop due to the internal resistance hardly occurs. Therefore, it is possible to prevent the luminance unevenness in the display area thereby.

In the conventional case, the common voltage is applied to the second electrode at one or two places of the non-display area outside the display area. Thus, the distance between the outermost part and the center of the display area adjacent to the second electrode is several centimeters or more. In the present invention, a common signal voltage is applied to each pixel region P, and a distance between the pixel regions P is several tens to several hundreds of micrometers and a distance of 1 mm or less. Since the voltage drop due to its movement hardly occurs, luminance unevenness does not occur.

Although not shown in the drawings, a transparent conductive material, such as indium, may be disposed on the second electrode 163 to protect the second electrode 163 having a relatively thin thickness and to prevent moisture penetration into the organic light emitting layer 160. An auxiliary second electrode (not shown) having a thickness of about 500 kPa to 2000 kPa may be further formed of -tin-oxide (ITO) or indium-zinc-oxide (IZO).

On the other hand, when the first electrode is composed of a cathode electrode and the second electrode is an anode electrode, by changing only the material constituting the first and second electrodes and proceeds the same process described above, the first for the top emission type organic EL device The substrate can be completed.

Meanwhile, a seal pattern (not shown) is formed along the edge of the display area with respect to the first substrate 110 completed as described above, and the second substrate 170 is made of transparent material to face the inert gas. By bonding the first and second substrates 110 and 170 in an atmosphere or vacuum atmosphere, the top emission type organic light emitting diode 101 according to the embodiment of the present invention may be completed.

1 is a circuit diagram of one pixel of a typical active matrix organic electroluminescent device.

Figure 2 is a schematic cross-sectional view of a conventional top-emitting organic light emitting device.

3 is a cross-sectional view of one pixel area including a driving thin film transistor of the top emission type organic light emitting diode illustrated in FIG. 2.

FIG. 4 is a cross-sectional view of a pixel area including a driving thin film transistor and an organic light emitting diode as a part of an upper light emitting organic light emitting diode according to an embodiment of the present invention; FIG.

FIG. 5 is a cross-sectional view of one pixel area including a driving thin film transistor and an organic light emitting diode, as a portion of the top emission type organic light emitting diode according to a modified example of the embodiment of the present invention.

6 is a partial plan view of one pixel area of the top emission type organic light emitting diode according to the embodiment of the present invention;

7A to 7I are cross-sectional views illustrating manufacturing steps of one pixel area of the top emission type organic light emitting diode according to the embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

110: first substrate 113: semiconductor layer

113a and 113b: first and second regions 116: gate insulating film

120: gate electrode 123: interlayer insulating film

125: semiconductor layer contact hole 133: source electrode

136: drain electrode 140: protective layer

143: drain contact hole 144: first common contact hole

147: first electrode 148: common auxiliary pattern

150: bank 153: second common contact hole

156: partition 158: first organic layer

160: organic light emitting layer 163: second electrode

DA: driving region E: organic light emitting diode

P: pixel area

Claims (10)

A first substrate; Gate and data lines formed on the first substrate to define pixel regions by crossing each other with an insulating layer therebetween; A common wiring formed on the first substrate on the same layer with the gate wiring spaced apart from the gate wiring; A switching thin film transistor and a driving thin film transistor formed in the pixel area on the first substrate; A protective layer formed on the pixel region, the protective layer having a drain contact hole covering the switching and driving thin film transistor and exposing a drain electrode of the driving thin film transistor and a first common contact hole exposing the common wiring; A common auxiliary pattern formed in contact with the common electrode through the first common contact hole and spaced apart from the first electrode formed in contact with the drain electrode of the driving thin film transistor through the drain contact hole on the passivation layer in the pixel area; and; A bank overlapping an edge of the first electrode and having a second common contact hole exposing the common auxiliary pattern at a boundary of the pixel region; A partition wall having an inverse taper shape at an upper end of the bank, the upper end of which is located outside the second common contact hole, and the side wall of which covers the second common contact hole; A first organic layer formed on an upper surface of the bank, the first electrode, and the partition without any pixel region; An organic light emitting layer formed in an area surrounded by the bank above the first organic layer; A second electrode covering one side surface and an upper surface of the barrier rib on the organic emission layer and contacting the common auxiliary pattern through the second common contact hole without division of a pixel area; A second substrate facing the first substrate; Seal patterns formed along edges of the first and second substrates An upper light emitting organic light emitting device comprising a. The method of claim 1, An upper light emitting organic light emitting diode, characterized in that a reflective plate is formed between the protective layer and the first electrode. The method of claim 1, An upper light emitting organic light emitting diode having an auxiliary electrode formed on the front surface of the second electrode as a transparent conductive material. The method of claim 1, An upper light emitting organic light emitting diode having a second organic layer formed between the organic light emitting layer and the second electrode to improve the light emitting efficiency of the organic light emitting layer. The method of claim 1, The first organic layer has a double layer structure of a hole injection layer / hole transporting layer or a double layer structure of an electron injection layer / electron transporting layer. An upper light-emitting organic light emitting device characterized in that it has. The method of claim 5, The second organic layer has a double layer structure of an electron transporting layer / electron injection layer when the first organic layer is a hole injection layer / hole transporting layer. When the first organic layer is an electron injection layer / electron transporting layer, the upper layer has a double layer structure of a hole transporting layer / hole injection layer. Emission type organic light emitting device. The method of claim 1, The first substrate may include a power line disposed parallel to the layer on which the data line is formed, and the gate and the data line may be connected to a gate electrode and a source small electrode of the switching TFT, respectively. EL device. A gate and data lines formed on the first substrate to intersect each other with an insulating layer interposed therebetween to define pixel regions, and common wiring spaced apart from the gate lines on the same layer on which the gate lines are formed; Forming a power supply wiring spaced apart from the data wiring in the same layer on which the wiring is formed; Forming a switching thin film transistor connected to a gate and a data line and a driving thin film transistor electrically connected to the pixel region on the first substrate; Forming a protective layer covering the switching and driving thin film transistor and having a drain contact hole exposing a drain electrode of the driving thin film transistor and a first common contact hole exposing the common wiring; A common auxiliary pattern is formed on the passivation layer in the pixel area, the first electrode contacting the drain electrode of the driving thin film transistor through the drain contact hole, the common auxiliary pattern contacting the common wiring through the first common contact hole. Making a step; Forming a bank including a second common contact hole overlapping an edge of the first electrode and exposing the common auxiliary pattern at a boundary of the pixel region; Forming a partition wall having an inverse taper shape on an end surface of the bank, the top end of which is located outside the second common contact hole, and the side wall of which covers the second common contact hole; Forming a first organic layer by performing vertical thermal deposition on the front surface of the bank, the first electrode, and the partition wall; Forming an organic emission layer by performing thermal deposition on the region surrounded by the bank above the first organic layer by using a shadow mask; The deposition particles do not enter the substrate surface perpendicularly to the substrate surface but are subjected to thermal evaporation or ion beam deposition such that oblique incidence is deposited so as to cover one side and the upper surface of the partition wall and the pixel region is not classified. Forming a second electrode contacting the common auxiliary pattern through a common contact hole; Opposing the second substrate to face the first substrate, forming a seal pattern along an edge, and bonding the first and second substrates together; Method of manufacturing a top emission type organic light emitting device comprising a. The method of claim 8, The forming of the first electrode may include forming a reflecting plate between the first electrode and the protective layer. The method of claim 8, In the deposition for forming the second electrode, the direction in which the deposition particles are incident and the angle formed by the substrate surface are 20 degrees to 70 degrees.

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