CN114613815B

CN114613815B - Display panel and manufacturing method thereof

Info

Publication number: CN114613815B
Application number: CN202210195317.XA
Authority: CN
Inventors: 胡凯
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2023-06-02
Anticipated expiration: 2042-03-01
Also published as: CN114613815A

Abstract

The invention discloses a display panel and a manufacturing method thereof, wherein the display panel comprises: the array substrate is positioned in the GOA area and the display area; the organic light-emitting layer is arranged on the array substrate and comprises a first electrode layer, a second electrode layer and a light-emitting material layer, the light-emitting material layer is arranged between the first electrode layer and the second electrode layer, and the light-emitting material layer is positioned in the display area; the first electrode layer is positioned in the display area and extends to the GOA area. The invention is positioned in the display area through the first electrode layer and extends to the GOA area. And the second electrode layer is positioned in the display area and extends to the GOA area. Thereby blocking the influence caused by the diffusion of H ions in the packaging layer and improving the problem of negative bias failure of the GOA circuit.

Description

Display panel and manufacturing method thereof

Technical Field

The invention relates to the technical field of display panels, in particular to a display panel and a manufacturing method thereof.

Background

At present, the organic light emitting diode display panel (Organic Light Emitting Diode, abbreviated as OLED) has the advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180 ° viewing angle, wide use temperature range, and the like, can realize large-area full-color display, is expected to become the next generation flat panel display technology following the LCD display technology, and is one of the technologies attracting attention in the flat panel display technology. An active matrix organic light emitting diode (Active Matrix Organic Light Emitting Diode, abbreviated as AMOLED) display panel is one of OLED display panels, and mainly consists of a thin film transistor (Thin Film Transistor, abbreviated as TFT) and an OLED.

Along with the continuous development of display technology, AMOLED technology is increasingly applied to flexible display, flexible product packaging is completely protected by TFE, but H ions are contained in a TFE film layer, and in the high temperature or aging process, the phenomenon of H ion diffusion exists, because anode and cathode shielding exists on an AA area, no metal layer is arranged on a GOA area for protection, and the GOA circuit is more likely to be subjected to negative bias of a device caused by H ion diffusion, so that the GOA circuit is invalid.

Disclosure of Invention

The invention aims to provide a display panel and a manufacturing method thereof, which can solve the problem that the GOA circuit is invalid because no metal layer is arranged on the GOA area to protect the display panel and the display panel are easy to be subjected to negative bias of devices caused by H ion diffusion.

According to an aspect of the present invention, there is provided a display panel including: the array substrate is positioned in the GOA area and the display area; the organic light-emitting layer is arranged on the array substrate and comprises a first electrode layer, a second electrode layer and a light-emitting material layer, the light-emitting material layer is arranged between the first electrode layer and the second electrode layer, and the light-emitting material layer is positioned in the display area; the first electrode layer is positioned in the display area and extends to the GOA area.

Further, the second electrode layer is located in the display area and extends to the GOA area.

Further, the array substrate includes: a substrate base; a light shielding layer arranged on the substrate; the buffer layer is arranged on the substrate base plate and the shading layer; an active layer disposed on the buffer layer; a gate insulating layer disposed on the active layer; a gate layer disposed on the gate insulating layer; an interlayer insulating layer disposed on the buffer layer, the active layer, and the gate layer; a source-drain electrode layer disposed on the interlayer insulating layer and connected to the active layer through a via hole; a passivation layer disposed on the interlayer insulating layer and the source/drain electrode layer; and a planarization layer disposed on the passivation layer.

Further, a thin film transistor is formed by the active layer, the gate insulating layer, the gate layer and the source-drain electrode layer, the thin film transistor is located in the display region and the GOA region, and the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the thin film transistor located in the GOA region on the substrate.

Further, the display panel further includes: and the packaging layer is arranged on the organic light-emitting layer.

According to another aspect of the present invention, there is also provided a method for manufacturing a display panel, the method including: providing an array substrate; depositing a first electrode layer on the array substrate, wherein the first electrode layer covers a display area and a GOA area; and depositing a layer of luminescent material on the first electrode layer; and evaporating a second electrode layer on the luminescent material layer.

Further, the second electrode layer covers the display region and the GOA region.

Further, the providing an array substrate includes: providing a substrate base plate; forming a light shielding layer on the substrate base plate; forming a buffer layer on the substrate base plate and the light shielding layer; forming an active layer on the buffer layer; forming a gate insulating layer on the active layer; forming a gate electrode layer on the gate insulating layer; forming an interlayer insulating layer on the buffer layer, the active layer, and the gate layer; forming a source-drain electrode layer on the interlayer insulating layer and connected with the active layer through a via hole; forming a passivation layer on the interlayer insulating layer and the source/drain electrode layer; and forming a planarization layer on the passivation layer.

Further, the method further comprises: and forming an encapsulation layer on the second electrode layer.

The invention has the advantage that the first electrode layer is positioned in the display area and extends to the GOA area. And the second electrode layer is positioned in the display area and extends to the GOA area. Thereby blocking the influence caused by the diffusion of H ions in the packaging layer and improving the problem of negative bias failure of the GOA circuit.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display panel according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a display panel according to a second embodiment of the present invention;

fig. 3 is a flowchart illustrating steps of a method for manufacturing a display panel according to a third embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. The display panel includes: an array substrate 100 and an organic light emitting layer 200.

Illustratively, the array substrate 100 is located in the GOA area 300 and the display area 400, the organic light emitting layer 200 is disposed on the array substrate 100, the organic light emitting layer 200 includes a first electrode layer 11, a second electrode layer 13, and a light emitting material layer 12, the light emitting material layer 12 is disposed between the first electrode layer 11 and the second electrode layer 13, the light emitting material layer 12 is located in the display area 400, and the first electrode layer 11 is located in the display area 400 and extends to the GOA area 300.

Wherein the array substrate 100 includes: the substrate 10, the light shielding layer 20, the buffer layer 30, the active layer 40, the gate insulating layer 50, the gate layer 60, the interlayer insulating layer 70, the source and drain electrode layer 80, the passivation layer 90, and the planarization layer 91.

Illustratively, the light shielding layer 20 is disposed on the substrate 10, which may be a flexible PI layer. A buffer layer 30 is disposed on the substrate 10 and the light shielding layer 20, for example, a SiOx or SiNx thin film is deposited as the buffer layer 30.

Illustratively, an active layer 40 is disposed on the buffer layer 30, such as depositing IGZO as the active layer 40, in: ga: zn=1:1:1 ratio, thickness 200-800A.

Illustratively, a gate insulating layer 50 is disposed on the active layer 40, a gate layer 60 is disposed on the gate insulating layer 50, and the gate layer 60 is formed by deposition, and may be Mo, al, cu, ti, etc. to a thickness of 2000-8000A.

In some embodiments, a yellow light is used to etch the pattern of the gate layer 60, then the pattern of the gate layer 60 is used to self-align, and the gate insulating layer 50 is etched, so that the Plasma treatment is performed on the whole surface, so that the resistance is obviously reduced after the portions above the active layer 40, which are not protected by the gate insulating layer 50 and the gate layer 60, are treated, and an n+ conductor layer is formed, and the active layer 40 below the gate insulating layer 50 and the gate layer 60 are not treated, so that the semiconductor characteristics are maintained and the active layer serves as a conductive channel layer of the thin film transistor.

Illustratively, an interlayer insulating layer 70 is disposed on the buffer layer 30, the active layer 40 and the gate layer 60, and the interlayer insulating layer 70 is formed, for example, by deposition, and may be made of SiOx or SiNx thin film, with a thickness of 2000A-10000A, and defines source-drain contact regions of the thin film transistor, and defines the crack prevention diffusion holes 21 in the bending regions using a photomask.

Illustratively, the source/drain electrode layer 80 is disposed on the interlayer insulating layer 70 and connected to the active layer 40 through the via hole 22, for example, the source/drain electrode layer 80 is formed by deposition, which may be Mo, al, cu, ti, etc., with a thickness of 2000-8000A, and then a pattern is defined.

Illustratively, the passivation layer 90 is disposed on the interlayer insulating layer 70 and the source/drain electrode layer 80, and the passivation layer 90 is formed by deposition, for example, and the material may be SiOx or SiNx film, with a thickness of 1000-5000A.

Illustratively, a planarization layer 91 is disposed on the passivation layer 90. The flat layer 91 is formed, for example by coating, to a thickness of 2-4um.

Illustratively, the active layer 40, the gate insulating layer 50, the gate layer 60, and the source drain electrode layer 80 form a thin film transistor, the thin film transistor is located in the display region 400 and the GOA region 300, and the orthographic projection of the first electrode layer 11 on the substrate 10 covers the orthographic projection of the thin film transistor located in the GOA region 300 on the substrate 10. For example, the first electrode layer 11 is deposited, the display area 400 and the GOA area 300 are patterned by a photomask, and the first metal layer of the GOA area 300 is required to cover the thin film transistor of the GOA area 300. Wherein the first metal layer is an anode layer and the second metal layer is a cathode layer.

The organic material is deposited again to form the light emitting material layer 12, and the light emitting region of the light emitting material layer 12 is defined by the pixel defining layer 23.

Illustratively, the encapsulation layer 24 is disposed on the organic light emitting layer 200. The stability of the film layer needs to be improved during development, and the encapsulation layer 24 may be increased by the H-containing gas during the process.

In the first embodiment, the first electrode layer 11 is located in the display area 400 and extends to the GOA area 300. Thereby blocking the effect of the diffusion of H ions in the encapsulation layer 24 and improving the negative bias failure problem of the GOA circuit.

Fig. 2 is a schematic structural diagram of a display panel according to an embodiment of the present invention. The display panel includes: an array substrate 100 and an organic light emitting layer 200.

Illustratively, the array substrate 100 is located in the GOA area 300 and the display area 400, the organic light emitting layer 200 is disposed on the array substrate 100, the organic light emitting layer 200 includes a first electrode layer 11, a second electrode layer 13, and a light emitting material layer 12, the light emitting material layer 12 is disposed between the first electrode layer 11 and the second electrode layer 13, the light emitting material layer 12 is located in the display area 400, and the first electrode layer 11 is located in the display area 400 and extends to the GOA area 300. The second electrode layer 13 is located in the display area 400 and extends to the GOA area 300.

Illustratively, a gate insulating layer 50 is disposed on the active layer 40, a gate layer 60 is disposed on the gate insulating layer 50, and the gate layer 60 is deposited, which may be Mo, al, cu, ti, etc., with a thickness of 2000-8000A.

In some embodiments, a pattern of the gate layer 60 is etched first using a yellow light, and then the gate insulating layer 50 is etched using the pattern of the gate layer 60 to be self-aligned; the entire Plasma treatment is performed such that the resistance is significantly reduced after the portions of the active layer 40 above which the gate insulating layer 50 and the gate layer 60 are not protected are treated, forming an n+ conductor layer, while the active layer 40 below the gate insulating layer 50 and the gate layer 60 are not treated, maintaining the semiconductor characteristics, as a thin film transistor conductive channel layer.

Illustratively, the active layer 40, the gate insulating layer 50, the gate layer 60, and the source drain electrode layer 80 form a thin film transistor, the thin film transistor is located in the display region 400 and the GOA region 300, and the orthographic projection of the first electrode layer 11 on the substrate 10 covers the orthographic projection of the thin film transistor located in the GOA region 300 on the substrate 10. For example, the first electrode layer 11 is deposited, the display area 400 and the GOA area 300 are patterned by a photomask, and the first electrode layer 11 of the GOA area 300 needs to cover the thin film transistor of the GOA area 300. The second electrode layer 13 is vapor-deposited to expand the cathode region and extend to the GOA region 300 to protect the GOA region 300. Wherein the first metal layer is an anode layer and the second metal layer is a cathode layer.

In the second embodiment, the first electrode layer is located in the display area and extends to the GOA area. And the second electrode layer is positioned in the display area and extends to the GOA area. Thereby blocking the influence caused by the diffusion of H ions in the packaging layer and improving the problem of negative bias failure of the GOA circuit.

Fig. 3 is a flowchart illustrating steps of a method for manufacturing a display panel according to an embodiment of the present invention. The method comprises the following steps:

step S310: an array substrate is provided.

Illustratively, the providing an array substrate includes:

a substrate is provided, which may be, for example, a flexible PI layer.

And forming a light shielding layer on the substrate.

A buffer layer is formed on the base substrate and the light shielding layer, illustratively by depositing SiOx or SiNx thin film as the buffer layer.

An active layer is formed on the buffer layer, and IGZO is deposited as the active layer, in: ga: zn=1:1:1 ratio, thickness 200-800A.

A gate insulating layer is formed on the active layer, and a gate layer is formed on the gate insulating layer, and illustratively, the gate layer is formed by deposition, and the material thereof may be Mo, al, cu, ti, or the like, with a thickness of 2000-8000A.

In some embodiments, a pattern of the gate layer is etched first using a yellow light, and then the gate insulating layer is etched using the gate layer pattern as self-alignment; the Plasma treatment is carried out on the whole surface, so that the resistance is obviously reduced after the part without the gate insulating layer and the gate layer protection above the active layer is treated, an N+ conductor layer is formed, and the active layer below the gate insulating layer and the gate layer is not treated, thereby maintaining the semiconductor characteristic and being used as a thin film transistor conductive channel layer.

An interlayer insulating layer is formed on the buffer layer, the active layer and the gate layer, and illustratively, the interlayer insulating layer is formed by deposition, and can be made of SiOx or SiNx film with a thickness of 2000A-10000A, and defines source and drain contact regions of the thin film transistor, and crack-preventing diffusion holes are defined in the bending region by using a photomask.

A source/drain electrode layer is formed on the interlayer insulating layer and connected to the active layer through a via hole, and the source/drain electrode layer is formed by deposition, for example, of Mo, al, cu, ti, or the like, with a thickness of 2000-8000A, and then a pattern is defined.

The interlayer insulating layer and the source and drain electrode layer are formed with a passivation layer, which may be SiOx or SiNx thin film, for example, by deposition, and has a thickness of 1000-5000A.

A planarization layer is formed on the passivation layer, and is formed, for example, by coating, to a thickness of 2-4um.

Step S320: and depositing a first electrode layer on the array substrate, wherein the first electrode layer covers the display area and the GOA area.

Illustratively, a thin film transistor is formed from the active layer, the gate insulating layer, the gate layer, and the source-drain electrode layer, the thin film transistor is located in the display region and the GOA region, and an orthographic projection of the first electrode layer on the substrate covers an orthographic projection of the thin film transistor located in the GOA region on the substrate. For example, a first electrode layer is deposited, a pattern of a display area and a GOA area is defined by a photomask, and a first metal layer of the GOA area is required to cover the thin film transistor of the GOA area. And depositing an organic material to form a luminescent material layer, and defining a luminescent area of the luminescent material layer through the pixel definition layer. Wherein the first metal layer is an anode layer and the second metal layer is a cathode layer.

Step S330: a layer of luminescent material is deposited on the first electrode layer.

Illustratively, an organic material is deposited, a layer of light-emitting material is formed, and a light-emitting region of the layer of light-emitting material is defined by the pixel definition layer.

Step S340: and evaporating a second electrode layer on the luminescent material layer.

In some other embodiments, the second electrode layer covers the display region and the GOA region. For example, the second electrode layer is formed by vapor deposition, and the cathode region is enlarged to extend to the GOA region to protect the GOA region.

Step S350: and forming an encapsulation layer on the second electrode layer.

Illustratively, an encapsulation layer is disposed on the organic light emitting layer. In the development process, the stability of the film needs to be improved, and in the process, the packaging layer can increase the H-containing gas.

In an embodiment, the first electrode layer is located in the display area and extends to the GOA area. And the second electrode layer is positioned in the display area and extends to the GOA area. Thereby blocking the influence caused by the diffusion of H ions in the packaging layer and improving the problem of negative bias failure of the GOA circuit.

The foregoing has outlined a detailed description of a display panel provided by embodiments of the present invention, wherein specific examples are provided herein to illustrate the principles and embodiments of the present invention, and the above examples are provided to assist in understanding the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present invention, the present description should not be construed as limiting the present invention.

Claims

1. A display panel, comprising:

the array substrate is positioned in the GOA area and the display area;

the organic light-emitting layer is arranged on the array substrate and comprises a first electrode layer, a second electrode layer and a light-emitting material layer, the light-emitting material layer is arranged between the first electrode layer and the second electrode layer, and the light-emitting material layer is positioned in the display area;

the first electrode layer is positioned in the display area and extends to the GOA area;

wherein, the array substrate includes:

a substrate base;

a light shielding layer arranged on the substrate;

the buffer layer is arranged on the substrate base plate and the shading layer;

an active layer disposed on the buffer layer;

a gate insulating layer disposed on the active layer;

a gate layer disposed on the gate insulating layer;

an interlayer insulating layer disposed on the buffer layer, the active layer, and the gate layer;

a source-drain electrode layer disposed on the interlayer insulating layer and connected to the active layer through a via hole;

a passivation layer disposed on the interlayer insulating layer and the source/drain electrode layer; and

a planarization layer disposed on the passivation layer;

and forming a thin film transistor by the active layer, the gate insulating layer, the gate layer and the source-drain electrode layer, wherein the thin film transistor is positioned in the display area and the GOA area, and the orthographic projection of the first electrode layer on the substrate base plate covers the orthographic projection of the thin film transistor positioned in the GOA area on the substrate base plate.

2. The display panel of claim 1, wherein the second electrode layer is located in the display region and extends to the GOA region.

3. The display panel of claim 1, further comprising: and the packaging layer is arranged on the organic light-emitting layer.

4. A method for manufacturing a display panel, comprising:

providing an array substrate;

depositing a first electrode layer on the array substrate, wherein the first electrode layer covers a display area and a GOA area; and

depositing a layer of luminescent material on the first electrode layer;

evaporating a second electrode layer on the luminescent material layer;

wherein, the providing an array substrate includes:

providing a substrate base plate;

forming a light shielding layer on the substrate base plate;

forming a buffer layer on the substrate base plate and the light shielding layer;

forming an active layer on the buffer layer;

forming a gate insulating layer on the active layer;

forming a gate electrode layer on the gate insulating layer;

forming an interlayer insulating layer on the buffer layer, the active layer, and the gate layer;

forming a source-drain electrode layer on the interlayer insulating layer and connected with the active layer through a via hole;

forming a passivation layer on the interlayer insulating layer and the source/drain electrode layer; and

forming a planarization layer on the passivation layer;

5. The method of claim 4, wherein the second electrode layer covers the display region and the GOA region.

6. The method of manufacturing a display panel according to claim 4, further comprising:

and forming an encapsulation layer on the second electrode layer.