CN111063692A - Display device and manufacturing method thereof - Google Patents
Display device and manufacturing method thereof Download PDFInfo
- Publication number
- CN111063692A CN111063692A CN201911219949.XA CN201911219949A CN111063692A CN 111063692 A CN111063692 A CN 111063692A CN 201911219949 A CN201911219949 A CN 201911219949A CN 111063692 A CN111063692 A CN 111063692A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- display device
- thin film
- light shielding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000010409 thin film Substances 0.000 claims abstract description 55
- 239000000463 material Substances 0.000 claims abstract description 38
- 229910052755 nonmetal Inorganic materials 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 308
- 239000011229 interlayer Substances 0.000 claims description 16
- 238000002161 passivation Methods 0.000 claims description 15
- 229910044991 metal oxide Inorganic materials 0.000 claims description 14
- 150000004706 metal oxides Chemical class 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 239000002210 silicon-based material Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims 1
- 230000001808 coupling effect Effects 0.000 abstract description 12
- 230000008569 process Effects 0.000 abstract description 9
- 239000007769 metal material Substances 0.000 abstract description 2
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 3
- -1 IGZO Chemical class 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/126—Shielding, e.g. light-blocking means over the TFTs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present disclosure provides a display device and a method of manufacturing the display device, the display device including a substrate base plate; the thin film transistor layer is arranged on the substrate and comprises a plurality of thin film transistors, and each thin film transistor comprises an active layer, a grid line layer and a source drain electrode layer; the display device layer is arranged on one side of the thin film transistor layer, which is far away from the substrate; and the light shielding layer is arranged between the thin film transistor layer and the substrate and is made of a non-metal light shielding material, external light incident from one side of the substrate is shielded by the non-metal light shielding material, so that the active layer is prevented from being irradiated by the external light, meanwhile, due to the non-metal characteristic of the non-metal material, a capacitive coupling effect cannot be generated between the light shielding layer and the thin film transistor, the light shielding layer and the source drain electrode layer are connected without opening a hole in the buffer layer, the reliability of the thin film transistor is enhanced, meanwhile, a light shield etching process can be reduced, and the actual production efficiency.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display device and a manufacturing method of the display device.
Background
An organic light-emitting diode (OLED) display device, also called an organic electroluminescent display, is a new flat panel display device, and has the advantages of simple manufacturing process, low cost, low power consumption, high brightness, wide application range of operating temperature, light and thin volume, fast response speed, easy realization of color display and large-screen display, easy realization of matching with an integrated circuit driver, easy realization of flexible display, and the like, so that the OLED display device has a wide application prospect. A Thin Film Transistor (TFT) plays an important role as a switching device in an organic light emitting diode display device. Common thin film transistors include a gate electrode, a source electrode, a drain electrode, an active layer, and the like, and the thin film transistors may be divided into a top gate thin film transistor and a bottom gate thin film transistor according to a relative position relationship between the gate electrode and the active layer.
An oxide semiconductor device in a top gate thin film transistor is greatly influenced by light due to the characteristics of the material itself, and the reliability is seriously deteriorated under the illumination condition. In order to solve the problem of light influence, a common scheme at present is to use a layer of metal as a light shielding layer in a thin film transistor region to protect the thin film transistor. However, if the light shielding layer made of a metal material is formed in a floating (collapsing) state, a capacitive coupling effect may occur, which makes the characteristics of the thin film transistor device abnormal and the thin film transistor device not easily enter a saturation region.
In summary, the conventional display device has a problem that the buffer layer needs to be opened to connect the source electrode and the light-shielding layer in order to eliminate the capacitive coupling effect between the light-shielding layer and the thin film transistor, which results in a complicated process flow and increased production cost. Therefore, it is desirable to provide a display device and a method for manufacturing the display device to improve the defect.
Disclosure of Invention
The embodiment of the disclosure provides a display device and a manufacturing method of the display device, which are used for solving the problems that in order to eliminate the capacitive coupling effect of a light shielding layer and a thin film transistor, a buffer layer needs to be perforated to connect a source electrode and the light shielding layer, so that the process flow is complex and the production cost is increased.
An embodiment of the present disclosure provides a display device, including:
a substrate base plate;
the thin film transistor layer is arranged on the substrate and comprises a plurality of thin film transistors, and each thin film transistor comprises an active layer, a grid line layer and a source drain electrode layer;
the display device layer is arranged on one side of the thin film transistor layer, which is far away from the substrate; and
and the light shielding layer is arranged between the thin film transistor layer and the substrate and is made of a non-metal light shielding material.
According to an embodiment of the present disclosure, the gate line layer is disposed on a side of the active layer away from the substrate, and an orthographic projection area of the light shielding layer on the substrate covers an orthographic projection area of the active layer on the substrate.
According to an embodiment of the present disclosure, the thin film transistor further comprises a gate insulating layer, an orthographic projection area of the gate insulating layer on the substrate covers an orthographic projection area of the gate line layer on the substrate.
According to an embodiment of the present disclosure, the display device layer includes an anode layer, a light emitting layer, and a cathode layer, which are stacked, and an orthographic projection area of the light emitting layer on the substrate does not overlap with an orthographic projection area of the light shielding layer on the substrate.
According to an embodiment of the disclosure, the display device further includes a passivation protection layer, a flat layer and a pixel defining layer, which are stacked on the source and drain electrode layers, wherein the anode layer is disposed on one side of the flat layer, which is far away from the passivation protection layer, and is connected with the source and drain electrode layers through a via hole penetrating through the flat layer and the passivation protection layer.
According to an embodiment of the present disclosure, the non-metallic light shielding material includes an amorphous silicon material or a metal oxide material.
According to an embodiment of the present disclosure, the metal oxide material comprises: IGZO, IZTO or IGZTO.
According to an embodiment of the present disclosure, a thickness of the light-shielding layer is between 500A and 2000A.
The embodiment of the disclosure further provides a manufacturing method of a display device, including:
providing a substrate, and depositing a layer of non-metal shading material on the substrate to form a shading layer;
forming a buffer layer on one side of the substrate close to the light shielding layer, wherein the buffer layer covers the light shielding layer;
forming an active layer on the buffer layer;
forming a gate insulating layer on the active layer;
forming a gate line layer on a side of the gate insulating layer away from the active layer;
performing plasma treatment on the active layer which is not covered by the gate line layer and the gate insulating layer to form an N + semiconductor portion, wherein the active layer which is not subjected to plasma treatment is used as a channel portion;
forming an interlayer insulating layer on the buffer layer, the interlayer insulating layer covering the active layer, the gate insulating layer and the gate line layer;
etching the interlayer insulating layer to expose the N + semiconductor portion; and
and forming a source drain electrode layer on the interlayer insulating layer, wherein the source drain electrode layer is connected with the N + semiconductor part through the through hole.
According to an embodiment of the present disclosure, the non-metallic light shielding material includes an amorphous silicon material or a metal oxide material.
The beneficial effects of the disclosed embodiment are as follows: according to the embodiment of the disclosure, the light shielding layer made of the non-metal light shielding material is arranged between the substrate and the active layer of the thin film transistor, the non-metal light shielding material is used for shielding external light incident from one side of the substrate, the active layer is prevented from being irradiated by the external light, and meanwhile, due to the non-metal characteristic of the light shielding layer, the light shielding layer and the thin film transistor cannot form capacitance therebetween, so that a capacitive coupling effect cannot be generated, the light shielding layer and the source drain electrode layer are connected without opening a hole in the buffer layer, the reliability of the thin film transistor is enhanced, meanwhile, one light shield etching process can be reduced, and the actual production.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some of the disclosed embodiments, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic cross-sectional structure diagram of a display device according to an embodiment of the disclosure;
fig. 2A to 2H are schematic cross-sectional structures of a display device according to a second embodiment of the disclosure.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in this disclosure, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure. In the drawings, elements having similar structures are denoted by the same reference numerals.
The disclosure is further described with reference to the following drawings and specific embodiments:
the first embodiment is as follows:
the embodiment of the present disclosure provides a display device, which is described in detail below with reference to fig. 1.
As shown in fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a display device 100 according to an embodiment of the disclosure, where the display device 100 includes a substrate 11, a thin-film transistor layer 12, a display device layer 13, a light-shielding layer 14, and a buffer layer 15. The thin film transistor layer 12 is arranged on the substrate 11, the display device layer 13 is arranged on one side, far away from the substrate 11, of the thin film transistor layer 12, and the buffer layer 15 is arranged between the substrate 11 and the thin film transistor layer 12 and covers the light shielding layer 14.
In this embodiment, the thin film transistor layer 12 includes a plurality of thin film transistors 120, the thin film transistors 120 include an active layer 121, a gate insulating layer 125, a gate line layer 122, and a source drain electrode layer 123, and an orthographic projection area of the gate insulating layer 125 on the substrate 11 covers an orthographic projection area of the gate line layer 122 on the substrate 11.
The active layer 121 is made of a metal oxide including IGZO, IZTO, or IGZTO. The active layer 121 made of metal oxide helps to improve electron mobility of the thin film transistor 120 and reduce power consumption of the display device 100, but is easily affected by external light.
As shown in fig. 1, the thin film transistor 120 is a thin film transistor with a top gate structure, the gate line layer 122 is disposed on a side of the active layer 121 away from the substrate 11, and the light shielding layer 14 is disposed between the thin film transistor layer 12 and the substrate 11, and is configured to shield an external shielding line incident from a side of the substrate, so as to prevent the active layer 121 in the thin film transistor 120 from being irradiated by external light and affecting reliability of the thin film transistor 120.
Specifically, the orthographic projection area of the light shielding layer 14 on the substrate 11 covers the orthographic projection area of the active layer 121 on the substrate 11, and the larger coverage area of the light shielding layer 14 is beneficial to isolating the active layer 121 from external light, so that the reliability of the thin film transistor 120 is improved.
In this embodiment, the material of the light shielding layer 14 is a non-metal light shielding material, and the non-metal light shielding material has non-metal characteristics, so that the light shielding layer 14 does not form a capacitor with the thin film transistor 120, and a capacitive coupling effect is not generated, and therefore, it is not necessary to open the buffer layer 15, and it is not necessary to connect the light shielding layer 14 and the source electrode 124 in the source/drain electrode layer 123 with the light shielding layer 14, so as to eliminate the capacitive coupling effect.
Preferably, the non-metallic light shielding material includes an amorphous silicon material or a metal oxide. Wherein, the amorphous silicon material has higher light absorption coefficient, especially visible light wave band in the range of 0.3-0.75 μm, and the absorption coefficient is higher by an order of magnitude than that of monocrystalline silicon. Meanwhile, the forbidden bandwidth of the amorphous silicon material is small, generally between 1.7eV and 1.8eV, and the amorphous silicon material can not form capacitance with the thin film transistor and generate a capacitive coupling effect while absorbing light. The amorphous silicon material is used to form the light-shielding layer 14, so that the light-shielding layer 14 can absorb external light, and the active layer 121 is prevented from being affected by the external light. Similarly, the characteristics of the metal oxide are similar to those of the amorphous silicon material, and are also suitable for forming the light shielding layer 14.
Preferably, the material of the metal oxide includes IGZO, IZTO, or IGZTO.
Preferably, while the good light shielding effect of the light shielding layer 14 is ensured, the thickness of the inner film layer of the display device 100 is not increased, and the value of the thickness of the light shielding layer 14 is between 500A and 2000A.
In this embodiment, the display device 100 is a bottom emission structure, the display device layer 13 includes an anode layer 131, a light emitting layer 132, and a cathode layer 133, which are stacked, and an orthographic projection area of the light emitting layer 131 on the substrate 11 does not overlap with an orthographic projection area of the light shielding layer 14 on the substrate 11, so that light emitted by the light emitting layer 131 is not shielded by the light shielding layer 14, and a display effect of the display device 100 is ensured.
As shown in fig. 1, the display device 100 further includes a passivation protection layer 16, a flat layer 17, and a pixel defining layer 18 stacked on the source/drain electrode layer 12, wherein the anode layer 131 is disposed on a side of the flat layer 17 away from the passivation protection layer 16, and is connected to the source 124 of the source/drain electrode layer 123 through a via hole penetrating through the flat layer 17 and the passivation protection layer 18.
The beneficial effects of the disclosed embodiment are as follows: in the embodiment of the disclosure, the light shielding layer 14 made of the non-metal light shielding material is arranged between the substrate 11 and the active layer 121 of the thin film transistor layer 12, the non-metal light shielding material can absorb external light incident from one side of the substrate 11, so that the active layer 121 is prevented from being irradiated by the external light, and meanwhile, due to the non-metal characteristic of the light shielding layer 14, capacitance cannot be formed between the light shielding layer and the thin film transistor, so that a capacitive coupling effect cannot be generated, therefore, the light shielding layer and the source drain electrode layer 123 are connected without opening a hole in the buffer layer 15, while the reliability of the thin film transistor is enhanced, one-step light shield etching process can be reduced, and the actual.
Example two:
the present disclosure provides a method for manufacturing a display device, which is described in detail below with reference to fig. 2A to 2H.
As shown in fig. 2A to 2H, fig. 2A to 2H are schematic cross-sectional structural diagrams of a display device in an embodiment of the disclosure, and a manufacturing method according to the embodiment of the disclosure includes:
step S10: as shown in fig. 2A, a substrate 21 is provided, and a layer of non-metallic light-shielding material is deposited on the substrate 21 to form a light-shielding layer 24.
In this embodiment, the light shielding layer 24 is made of a non-metal light shielding material, and due to the non-metal property of the non-metal light shielding material, the light shielding layer 24 does not form a capacitor with the thin film transistor 220, and a capacitive coupling effect is not generated, so that the buffer layer 25 does not need to be perforated, and the light shielding layer 24 and the source 224 in the source/drain electrode layer 223 do not need to be connected to the light shielding layer 24, so as to eliminate the capacitive coupling effect, and at the same time, a mask etching process is also saved. Preferably, the non-metallic light shielding material includes an amorphous silicon material or a metal oxide.
In the embodiment, the light shielding layer 24 has a thickness of 500A, while ensuring good light shielding effect and not increasing the thickness of the inner film layer of the display device. In some embodiments, the thickness of the light shielding layer 24 may be between 500A and 2000A.
Step S20: as shown in fig. 2B, a buffer layer 25 is formed on a side of the base substrate 21 close to the light-shielding layer 24, and the buffer layer 25 also covers the light-shielding layer 24.
In this embodiment, the buffer layer 25 is made of SiOx, and has a thickness of 1000A. In other embodiments, the thickness of the buffer layer 25 may be between 1000A and 5000A.
Step S30: an active layer 221 is formed on the buffer layer 25 such that an orthographic projection area of the light shielding layer 24 on the base substrate 21 covers an orthographic projection area of the active layer 221 on the base substrate 21.
In the present embodiment, the material of the active layer 221 is IGZO, and the thickness thereof is 1000A. In other embodiments, the material of the active layer may also be a metal oxide such as IZTO or IGZTO, and the thickness of the active layer is between 1000A and 3000A.
Step S40: as shown in fig. 2C, a gate insulating layer 225 is formed on a side of the active layer 221 away from the base substrate 21.
In this embodiment, the gate insulating layer 225 is SiOx with a thickness of 1000A. In other embodiments, the thickness of the gate insulating layer 225 may be between 1000A and 3000A.
Step S50: a gate line layer 222 is formed on a side of the gate insulating layer 225 away from the active layer 221.
In the present embodiment, the gate line layer 222 is a Mo/Cu metal stack structure, and the thickness of the gate line layer 222 is 2000A. In some embodiments, the gate line layer 222 may also be Ti/Cu or an alloy/Cu stack structure, and the thickness thereof may be between 2000A and 8000A. Step S50 is to deposit a metal layer on the gate insulating layer 225, etch the gate line pattern to form the gate line layer 222 through a yellow light process, and self-align etch the excess gate insulating material with the gate line pattern.
Step S60: the active layer 221, which is not covered with the gate line layer 222 and the gate insulating layer 225, is plasma-treated to form an N + semiconductor portion a, and the active layer 221, which is not plasma-treated, serves as a channel portion b.
Step S70: as shown in fig. 2D, an interlayer insulating layer 226 is formed on the buffer layer 25, and the interlayer insulating layer 226 covers the active layer 221, the gate insulating layer 225, and the gate line layer 222.
In the present embodiment, the thickness of the interlayer insulating layer 226 is 100A. In some embodiments, the thickness of the interlayer insulating layer 226 may also be between 100A and 500A.
Step S80: the interlayer insulating layer 226 is etched to form a via hole penetrating the interlayer insulating layer 226 to expose the N + semiconductor portion a.
Step S90: as shown in fig. 2E, a source drain electrode layer 223 is formed on the interlayer insulating layer 226, and a drain electrode and a source electrode 224 of the source drain electrode layer 223 are respectively connected to the N + semiconductor portion a through the via hole.
In this embodiment, the source/drain electrode layer 223 is a Mo/Cu metal stacked structure, and the thickness of the source/drain electrode layer 223 is 2000A. In some embodiments, the source drain electrode layer 223 may also be Ti/Cu or a stacked structure of alloy/Cu, and the thickness thereof may be between 2000A and 8000A.
To this end, the thin-film transistor layer 22 is already manufactured, and in this embodiment, the method for manufacturing the display panel further includes:
step S100: as shown in fig. 2F, forming a passivation protection layer 26 on the interlayer insulating layer 226, where the passivation protection layer 26 covers the source and drain electrode layers; the passivation layer 26 is made of SiOx, and has a thickness of 1000A. In some embodiments, the passivation protection layer 26 may also be made of other materials with similar or identical properties, and the thickness thereof may also be between 1000A and 5000A.
Step S110: forming a flat layer 27 on the passivation protection layer 26, and forming a via hole penetrating through the passivation protection layer 26 and the flat layer 27 by a yellow light process; the material of the planarization layer 27 is the same as the photoresist material in the prior art, and the thickness thereof is 10000A. In some embodiments, the thickness of the planarization layer 27 may also be 10000A to 20000A.
Step S120: as shown in fig. 2G, an anode layer 231 is formed on the planarization layer 27, and the anode layer 231 is connected to the source electrode 224 through the via hole; the anode layer is made of transparent oxide such as Indium Tin Oxide (ITO) and the like, and the thickness of the anode layer is 500A. In some embodiments, the anode layer 231 may also be made of other transparent metal oxides, and the thickness thereof may also be between 500A and 1000A.
Step S130: forming a pixel defining layer 28 on the planarization layer 27, wherein the pixel defining layer 28 covers the anode layer 231, and then forming a via hole on the pixel defining layer 28 to expose a portion of the anode layer 231 under the pixel defining layer 28; the material of the pixel defining layer 28 is the same as that of the photoresist in the prior art, and the thickness thereof is 10000A. In some embodiments, the thickness of the pixel defining layer 28 may also be between 10000A and 20000A.
Step S140: a light emitting layer 232 is formed within the via. As shown in fig. 2H, an orthographic projection area of the light emitting layer 232 on the substrate 21 does not overlap with an orthographic projection area of the light shielding layer 24 on the substrate 21, so that light emitted by the light emitting layer 232 passes through the substrate 21 without being shielded by the light shielding layer 24, thereby ensuring a display effect of the display device.
Step S150: a cathode layer 233 is formed on the pixel defining layer 28, and the anode layer 231, the light emitting layer 232, and the cathode layer 233 collectively constitute a display device layer 23 of a display device.
The beneficial effects of the disclosed embodiment are as follows: the embodiment of the disclosure provides a manufacturing method of a display device, a light shielding layer made of a non-metal light shielding material is arranged between a thin film transistor and a substrate, the light shielding layer is used for shielding external light incident from one side of the substrate to prevent the external light from irradiating an active layer, and the light shielding layer does not form capacitance with the thin film transistor due to the non-metal characteristic of the material, so that a capacitance coupling effect cannot be generated, the light shielding layer is connected with a source drain electrode layer without perforating a buffer layer, the reliability of the thin film transistor is enhanced, a photomask etching process can be reduced, and the actual production efficiency is improved.
In summary, although the present disclosure has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present disclosure, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so that the scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A display device, comprising:
a substrate base plate;
the thin film transistor layer is arranged on the substrate and comprises a plurality of thin film transistors, and each thin film transistor comprises an active layer, a grid line layer and a source drain electrode layer;
the display device layer is arranged on one side of the thin film transistor layer, which is far away from the substrate; and
and the light shielding layer is arranged between the thin film transistor layer and the substrate and is made of a non-metal light shielding material.
2. The display device according to claim 1, wherein the gate line layer is disposed on a side of the active layer away from the substrate, and an orthographic projection area of the light shielding layer on the substrate covers an orthographic projection area of the active layer on the substrate.
3. The display device according to claim 2, wherein the thin film transistor further comprises a gate insulating layer, an orthographic projection area of the gate insulating layer on the substrate base plate covering an orthographic projection area of the gate line layer on the substrate base plate.
4. The display device according to claim 1, wherein the display device layer includes an anode layer, a light emitting layer, and a cathode layer which are stacked, and an orthographic projection area of the light emitting layer on the substrate does not overlap with an orthographic projection area of the light shielding layer on the substrate.
5. The display device according to claim 1, further comprising a passivation protection layer, a planarization layer, and a pixel defining layer, which are stacked on the source and drain electrode layers, wherein the anode layer is disposed on a side of the planarization layer away from the passivation protection layer, and is connected to the source and drain electrode layers through a via hole penetrating the planarization layer and the passivation protection layer.
6. The display device of claim 1, wherein the non-metallic light blocking material comprises an amorphous silicon material or a metal oxide material.
7. The display device of claim 6, wherein the metal oxide material comprises IGZO, IZTO, or IGZTO.
8. The display device according to claim 1, wherein a thickness of the light-shielding layer is between 500A and 2000A.
9. A method for manufacturing a display device, comprising:
providing a substrate, and depositing a layer of non-metal shading material on the substrate to form a shading layer;
forming a buffer layer on one side of the substrate close to the light shielding layer, wherein the buffer layer covers the light shielding layer;
forming an active layer on the buffer layer;
forming a gate insulating layer on the active layer;
forming a gate line layer on a side of the gate insulating layer away from the active layer;
performing plasma treatment on the active layer which is not covered by the gate line layer and the gate insulating layer to form an N + semiconductor portion, wherein the active layer which is not subjected to plasma treatment is used as a channel portion;
forming an interlayer insulating layer on the buffer layer, the interlayer insulating layer covering the active layer, the gate insulating layer and the gate line layer;
etching the interlayer insulating layer to expose the N + semiconductor portion; and
and forming a source drain electrode layer on the interlayer insulating layer, wherein the source drain electrode layer is connected with the N + semiconductor part through the through hole.
10. The method for manufacturing a display device according to claim 9, wherein the non-metal light shielding material comprises an amorphous silicon material or a metal oxide material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911219949.XA CN111063692A (en) | 2019-12-03 | 2019-12-03 | Display device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911219949.XA CN111063692A (en) | 2019-12-03 | 2019-12-03 | Display device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111063692A true CN111063692A (en) | 2020-04-24 |
Family
ID=70299622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911219949.XA Pending CN111063692A (en) | 2019-12-03 | 2019-12-03 | Display device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111063692A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111898517A (en) * | 2020-07-28 | 2020-11-06 | 北海惠科光电技术有限公司 | Optical fingerprint sensor, preparation method thereof and display device |
| CN112289841A (en) * | 2020-10-30 | 2021-01-29 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
| CN114171604A (en) * | 2021-12-09 | 2022-03-11 | 广州华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN114447081A (en) * | 2022-01-27 | 2022-05-06 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| WO2023070712A1 (en) * | 2021-10-25 | 2023-05-04 | 武汉华星光电半导体显示技术有限公司 | Display device and manufacturing method therefor |
| WO2023201807A1 (en) * | 2022-04-22 | 2023-10-26 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method therefor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681623A (en) * | 2013-11-26 | 2015-06-03 | 乐金显示有限公司 | Oxide thin film transistor and array substrate including the same |
| CN105226052A (en) * | 2014-06-23 | 2016-01-06 | 群创光电股份有限公司 | Display device |
| CN107134482A (en) * | 2017-05-09 | 2017-09-05 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device |
| CN107170762A (en) * | 2017-06-16 | 2017-09-15 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and preparation method thereof |
| CN107910375A (en) * | 2017-11-02 | 2018-04-13 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device |
| KR20180087167A (en) * | 2017-01-23 | 2018-08-01 | 인천대학교 산학협력단 | Inverter including depletion load having photosensitive channel layer and enhancement driver having light shielding layer and photo detector using the same |
-
2019
- 2019-12-03 CN CN201911219949.XA patent/CN111063692A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104681623A (en) * | 2013-11-26 | 2015-06-03 | 乐金显示有限公司 | Oxide thin film transistor and array substrate including the same |
| CN105226052A (en) * | 2014-06-23 | 2016-01-06 | 群创光电股份有限公司 | Display device |
| KR20180087167A (en) * | 2017-01-23 | 2018-08-01 | 인천대학교 산학협력단 | Inverter including depletion load having photosensitive channel layer and enhancement driver having light shielding layer and photo detector using the same |
| CN107134482A (en) * | 2017-05-09 | 2017-09-05 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, display panel, display device |
| CN107170762A (en) * | 2017-06-16 | 2017-09-15 | 武汉华星光电半导体显示技术有限公司 | OLED display panel and preparation method thereof |
| CN107910375A (en) * | 2017-11-02 | 2018-04-13 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device |
Non-Patent Citations (1)
| Title |
|---|
| 朱建国: "《电子与光电子材料》", 31 August 2007, 国防工业出版社 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111898517A (en) * | 2020-07-28 | 2020-11-06 | 北海惠科光电技术有限公司 | Optical fingerprint sensor, preparation method thereof and display device |
| CN112289841A (en) * | 2020-10-30 | 2021-01-29 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
| CN112289841B (en) * | 2020-10-30 | 2024-07-05 | 湖北长江新型显示产业创新中心有限公司 | Display panel and display device |
| WO2023070712A1 (en) * | 2021-10-25 | 2023-05-04 | 武汉华星光电半导体显示技术有限公司 | Display device and manufacturing method therefor |
| CN114171604A (en) * | 2021-12-09 | 2022-03-11 | 广州华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN114447081A (en) * | 2022-01-27 | 2022-05-06 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| WO2023201807A1 (en) * | 2022-04-22 | 2023-10-26 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111063692A (en) | Display device and manufacturing method thereof | |
| US11152443B2 (en) | Display panel having a storage capacitor and method of fabricating same | |
| KR102328494B1 (en) | OLED display panel and manufacturing method thereof | |
| US11610922B2 (en) | Array substrate and display panel design improving aperture ratio | |
| CN111725324B (en) | Thin film transistor, array substrate and manufacturing method thereof | |
| US20210167156A1 (en) | Display substrate and manufacture method thereof, display device | |
| WO2016107291A1 (en) | Array substrate and manufacturing method therefor, display panel and display device | |
| US11289685B2 (en) | Display panel with patterned light absorbing layer, and manufacturing method thereof | |
| CN102646699A (en) | Oxide TFT (thin film transistor) and manufacturing method thereof | |
| CN109461763B (en) | Preparation method of display panel and display panel | |
| CN110556406A (en) | OLED display panel and preparation method thereof | |
| CN111081737A (en) | Array substrate preparation method and array substrate | |
| US20220020836A1 (en) | Display panel and display device | |
| WO2021031312A1 (en) | Organic light-emitting display panel and preparation method thereof | |
| CN113629072A (en) | Array substrate, preparation method thereof and display panel | |
| CN110808276A (en) | OLED display panel, preparation method thereof and OLED display device | |
| US20200235321A1 (en) | Display panel, manufacturing method thereof, display device | |
| CN113745249B (en) | Display panel, preparation method thereof and mobile terminal | |
| CN109801952B (en) | Display panel and manufacturing method thereof | |
| CN113629073B (en) | TFT backboard and display panel | |
| CN110071148A (en) | Organic LED display device and its manufacturing method | |
| CN113421886B (en) | Display panel and preparation method thereof | |
| US11469328B2 (en) | TFT array substrate and preparation method thereof | |
| KR20100075058A (en) | Thin film transistor array substrate and method thereof | |
| CN111415963A (en) | Display panel and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200424 |