CN110021531A - Thin-film transistor array base-plate and preparation method thereof - Google Patents
Thin-film transistor array base-plate and preparation method thereof Download PDFInfo
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- CN110021531A CN110021531A CN201910225403.9A CN201910225403A CN110021531A CN 110021531 A CN110021531 A CN 110021531A CN 201910225403 A CN201910225403 A CN 201910225403A CN 110021531 A CN110021531 A CN 110021531A
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- drain electrode
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- active layer
- zinc oxide
- film transistor
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- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 239000010409 thin film Substances 0.000 title claims description 36
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims abstract description 111
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052733 gallium Inorganic materials 0.000 claims abstract description 56
- 239000011787 zinc oxide Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000002161 passivation Methods 0.000 claims abstract description 34
- 229910052738 indium Inorganic materials 0.000 claims abstract description 30
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims abstract description 28
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims description 24
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 239000002131 composite material Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000011701 zinc Substances 0.000 claims description 5
- 239000002023 wood Substances 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000012780 transparent material Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000002708 enhancing effect Effects 0.000 description 2
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
This application involves a kind of tft array substrate and preparation method thereof, which includes: substrate；Grid is formed in substrate；Insulating layer covers grid；Active layer is formed on insulating layer, and active layer includes indium gallium zinc oxide；Source electrode and drain electrode is formed on active layer, and source electrode and drain electrode includes gallium zinc oxide；Passivation layer is formed in source electrode and drain electrode, and via hole is offered on passivation layer；Pixel electrode is formed on passivation layer, and pixel electrode is connected by via hole and drain electrode, and pixel electrode includes indium tin oxide.Select indium gallium zinc oxide as active layer, gallium zinc oxide can reduce the contact berrier between pixel electrode and drain electrode and the contact berrier between source-drain electrode and active layer as pixel electrode, improve device performance as source electrode and drain electrode, indium tin oxide.
Description
Technical field
This application involves display fields, more particularly to a kind of thin-film transistor array base-plate and preparation method thereof.
Background technique
Film crystal is formed in thin film transistor (TFT) (Thin Film Transistor, hereinafter referred to as TFT) array substrate
Pipe array, thin film transistor (TFT) specifically include grid, insulating layer, active layer and the source electrode being formed on active layer successively folded and set
And drain electrode, wherein grid is connect with scan line, and source electrode is connect with data line, and drain electrode is connect with pixel electrode, when scan line is grid
Pole provides voltage, and thin film transistor (TFT) conducting, pixel electrode can pass sequentially through drain electrode and source electrode obtains the voltage of data line.So
And current thin film transistor (TFT), since leakage current is obvious, the current on/off ratio of thin film transistor (TFT) is low, and device performance is difficult to be mentioned
It rises.
Summary of the invention
Based on this, it is necessary to for the skill that thin-film transistor drain current in tft array substrate is obvious and current on/off ratio is low
Art problem provides a kind of thin-film transistor array base-plate and preparation method thereof.
A kind of thin-film transistor array base-plate preparation method, comprising:
Substrate is provided, forms grid on the substrate；
Insulating layer is covered on the grid；
It is formed on the insulating layer active layer, the active layer includes indium gallium zinc oxide；
Source electrode and drain electrode is formed on the active layer, and the source electrode and drain electrode includes gallium zinc oxide；
Passivation layer is formed on the source electrode and the drain electrode, and opens up via hole on the passivation layer；And
Pixel electrode is formed on the passivation layer, the pixel electrode is connected by the via hole and the drain electrode, institute
Stating pixel electrode includes indium tin oxide.
It is formed after source electrode and drain electrode on the active layer in one of the embodiments, further includes:
Annealing, the temperature range of the annealing are 250 DEG C 2250 DEG C, and the time range of the annealing is 5min215min.
The annealing is carried out in nitrogen environment in one of the embodiments,.
The atomic ratio of the indium gallium zinc oxide is In:Ga:Zn:O=1:1:1:1 in one of the embodiments,.
The thickness range of the active layer is 45nm250nm in one of the embodiments,.
The grid includes copper-molybdenum composite material in one of the embodiments,.
The thickness range of the grid is 500nm2550nm in one of the embodiments,.
Above-mentioned tft array substrate preparation method is used as pixel electrode using indium tin oxide (ITO), using indium gallium zinc oxygen
Compound (IGZO) is used as active layer, and is used as source electrode and drain electrode, gallium zinc oxide, the oxidation of indium tin using gallium zinc oxide (GZO)
The work function of object and indium gallium zinc oxide is closer to, and material is the drain electrode of gallium zinc oxide and source electrode and material are the oxidation of indium tin
The pixel electrode of object can form good Ohmic contact, and contact berrier is smaller, meanwhile, material be gallium zinc oxide drain electrode with
Material be indium gallium zinc oxide active layer can also form good Ohmic contact, contact berrier is also smaller, i.e., source-drain electrode and
Between active layer and can form good Ohmic contact between drain electrode and pixel electrode therefore can be to a certain extent
Leakage current is reduced, the current on/off ratio of thin film transistor (TFT) is improved, reduces threshold voltage.Meanwhile using gallium zinc oxide as source
Pole and drain electrode, since gallium zinc oxide is transparent material, compared to used in tradition opaque metal as source electrode and drain electrode,
In the application, drain electrode can also be penetrated by being incident to the light at drain electrode, participated in image and shown, to increase entire tft array substrate
Glazed area, improve display product image quality.
The application further relates to another thin-film transistor array base-plate preparation method, comprising:
Substrate is provided, forms grid on the substrate, the grid includes copper-molybdenum composite material；
Insulating layer is covered on the grid；
It is formed on the insulating layer active layer, the active layer includes indium gallium zinc oxide；
Source electrode and drain electrode is formed on the active layer, and the source electrode and drain electrode includes gallium zinc oxide；
Annealing, the temperature range of the annealing are 250 DEG C 2250 DEG C, and the time range of the annealing is 5min215min；
Passivation layer is formed on the source electrode and the drain electrode, and opens up via hole on the passivation layer；And
Pixel electrode is formed on the passivation layer, the pixel electrode is connected by the via hole and the drain electrode, institute
Stating pixel electrode includes indium tin oxide.
The application also provides a kind of thin-film transistor array base-plate, comprising:
Substrate；
Grid is formed in the substrate；
Insulating layer covers the grid；
Active layer is formed on the insulating layer, and the active layer includes indium gallium zinc oxide；
Source electrode and drain electrode is formed on the active layer, and the source electrode and drain electrode includes gallium zinc oxide；
Passivation layer is formed on the source electrode and the drain electrode, offers via hole on the passivation layer；And
Pixel electrode is formed on the passivation layer, and the pixel electrode is connected by the via hole and the drain electrode, institute
Stating pixel electrode includes indium tin oxide.
In one embodiment, the grid includes copper-molybdenum composite material.
Detailed description of the invention
Fig. 1 be this application involves a kind of thin-film transistor array base-plate preparation flow figure；
Fig. 2 be this application involves another thin-film transistor array base-plate preparation flow figure；
Fig. 3 is the partial sectional view of thin-film transistor array base-plate in one embodiment of the application.
Specific embodiment
The application in order to facilitate understanding is described more fully the application below with reference to relevant drawings.In attached drawing
Give the preferred embodiment of the application.But the application can realize in many different forms, however it is not limited to this paper institute
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to disclosure of this application.
Unless otherwise defined, all technical and scientific terms used herein and the technical field for belonging to the application
The normally understood meaning of technical staff is identical.The term used in the description of the present application is intended merely to description tool herein
The purpose of the embodiment of body, it is not intended that in limitation the application.Term " and or " used herein includes one or more phases
Any and all combinations of the listed item of pass.
It should be noted that it can be directly to separately when an element is considered as " connection " another element
One element may be simultaneously present centering elements.
It in this application, is as shown in Figure 1 the step flow chart of tft array substrate preparation method, which includes:
Step S110: substrate is provided, forms grid on the substrate.
In one embodiment, as shown in Fig. 2, providing substrate 110, grid 120 is formed in substrate 100.Substrate 110 is selected
Transparent or translucent material is made, generally selection substrate of glass.In one embodiment, the selection of grid 120 may include that copper-molybdenum is multiple
Condensation material.Copper-molybdenum composite material has lower resistivity, can reduce the decaying to electric signal, and the grid 120 formed has
The preferable uniformity, stability is good, and it is higher to repair success rate.In one embodiment, grid 120 is done using copper-molybdenum composite material
When, the thickness range of grid 120 is 500nm2550nm, and the grid in this thickness range has lower resistivity, thus
Reduce the delay and decaying of scanning-line signal.
Step S120: insulating layer is covered on the grid.
As shown in Fig. 2, covering insulating layer 120 on grid 120.Insulating layer 120 can be constituted for transparent material, such as silica or
Aluminium oxide etc..
Step S120: being formed on the insulating layer active layer, and the active layer includes indium gallium zinc oxide.
As shown in Fig. 2, forming active layer 140 on insulating layer 120, active layer 140 is exhausted by insulating layer 120 and grid 120
Edge, active layer 140 include indium gallium zinc oxide.Compared to traditional amorphous silicon film layer, indium gallium zinc oxide film layer has higher
Mobility and bigger aperture opening ratio, and membrane uniformity is more preferable.In indium gallium zinc oxide film layer, oxygen content is lower, electricity
Transport factor is higher, and studies have shown that In2+Compare Zn2+And Ga2+More advantageous to the conduction of electronics, the combination of Ga and oxygen is stronger, can
To inhibit the formation of Lacking oxygen, the stability of device can be improved, when wherein oxygen content is few, oxygen preferentially in conjunction with Ga, improves device
Part stability, therefore In2+Be conducive to improve the mobility of device, but it is a large amount of it is demonstrated experimentally that In2+Although can greatly improve
The mobility of device, but the substitution of In atom pair Zn atom, can discharge an excess electron, eventually lead to the carrier of active layer
Excessive concentration makes the operating mode of device become depletion type, meanwhile, In is used as kind of a rare metal, and it is expensive, so active layer
In should not add excessive In；Meanwhile when oxygen content is too many, Lacking oxygen is caused to increase, the electric conductivity of film is deteriorated, while more
Oxygen can and In and Zn combine, reduce the mobility of device, decline device performance.In one embodiment, indium gallium zinc oxide
Atomic ratio be In:Ga:Zn:O=1:1:1:1, the indium gallium zinc oxide film layer with the atomic ratio both had certain
Semiconducting behavior, and there is preferable electron mobility.In one embodiment, when active layer 140 is indium gallium zinc oxide film layer
When, the thickness range of active layer 140 is 45nm250nm.The output characteristics of the thickness effect thin film transistor (TFT) of active layer 140, has
The thickness of active layer 140 is excessively thin, and carrier transport function limitation, mobility is lower, and the thickness of active layer 140 is excessive, existing
Defect state number is more, the effect enhancing that carrier is captured or scattered, so as to cause subthreshold swing deterioration, in the present embodiment
In, the thickness of active layer 140 is in the range of 45nm250nm, can guarantee that thin film transistor (TFT) has preferable electron-transport energy
Power and lower subthreshold swing.
Step S140: forming source electrode and drain electrode on the active layer, and the source electrode and drain electrode includes gallium zinc oxide.
As shown in Fig. 2, forming source electrode 151 and drain electrode 152 on active layer 140, source electrode 151 and drain electrode 152 include gallium zinc
Oxide.In one embodiment, source electrode 151 and drain electrode 152, source electrode 151 and drain electrode 152 can be formed by magnetron sputtering technique
Thickness range be 200nm2250nm.
Step S150: passivation layer is formed on the source electrode and the drain electrode, and opens up via hole on the passivation layer.
As shown in Fig. 2, forming passivation layer 160 on source electrode 151 and drain electrode 152, via hole is offered on passivation layer 160, it should
Via hole is in right above drain electrode 152.Passivation layer 160 can be constituted for transparent material, such as silica or aluminium oxide
Step S160: forming pixel electrode on the passivation layer, and the pixel electrode passes through the via hole and the leakage
Pole connection, the pixel electrode includes indium tin oxide.
As shown in Fig. 2, forming pixel electrode 170 on passivation layer 160, pixel electrode 170 is connected by via hole and drain electrode 152
It connects, pixel electrode 170 includes indium tin oxide.
In thin film transistor (TFT), source-drain electrode and active layer contact, pixel electrode and drain contact, and the picture in traditional technology
The material of plain electrode is usually indium tin oxide, and the material of active layer is amorphous silicon, and source-drain electrode material is usually molybdenum, aluminium or copper
Equal metals, the contact berrier between drain electrode and pixel electrode is larger, and the contact berrier between active layer and source-drain electrode is also larger, connects
Touching potential barrier is bigger, and leakage current is bigger, and the current on/off ratio of thin film transistor (TFT) is lower, thus the performance of limit device.In the application
In, drain electrode 152 and pixel electrode 170 contact, wherein gallium zinc oxide, pixel electrode 170 are selected in source electrode 151 and drain electrode 152
Indium tin oxide is selected, since the work function of gallium zinc oxide and indium tin oxide is closer to, pixel electrode 170 and drain electrode
152 contacts, the contact berrier that contact interface is formed is lower, has good Ohmic contact；Active layer 140 selects indium simultaneously
The work function of gallium zinc oxide, indium gallium zinc oxide and gallium zinc oxide is also closer to so that source electrode 151 and drain electrode 152 with
Contact berrier between active layer 140 is relatively low, has good Ohmic contact, contact berrier is lower, the electricity of thin film transistor (TFT)
Stream on-off ratio is higher, and required threshold voltage is lower, therefore, uses gallium zinc oxide as source electrode and leakage simultaneously in the application
Pole uses indium tin oxide as pixel electrode, uses indium gallium zinc oxide as active layer, can improve the performance of device.Together
When, gallium zinc oxide is unable to light transmission compared to using metal as source-drain electrode as the material with certain translucency, at this
In embodiment, such as also light-permeable at Fig. 2 dotted line frame position, light can successively penetrate thin film transistor substrate 110, insulating layer 120,
Drain electrode 152 and pixel electrode 170, to improve the light-permeable area of tft array substrate.
In one embodiment, it anneals after forming the source electrode and the drain electrode, the temperature range of annealing is 250 DEG C
2250 DEG C, the time range of annealing is 5min215min.
After forming source electrode 151 and drain electrode 152, and then anneal source electrode 151 and drain electrode 152 to reduce source electrode
151 and drain electrode 152 defect, the temperature range of annealing is 250 DEG C 2250 DEG C, and the time range of annealing is 5min215min,
After being annealed under the parameter, on the one hand, the work function of gallium zinc oxide and the work content of indium tin oxide and indium gallium zinc oxide
Number is more nearly, and on the other hand, the transparency of gallium zinc oxide improves, the light transmittance enhancing of drain electrode, by the parameter area
Annealing after, the transparency of gallium zinc oxide increases, and light transmittance reaches 80% or more.In one embodiment, above-mentioned to move back
Fiery step carries out in nitrogen environment, and nitrogen belongs to inert gas, anneals in nitrogen, can avoid thin film transistor (TFT) and is moving back
It is influenced during fire by other impurities.In one embodiment, specifically optional 200 DEG C of the temperature of annealing, the time for corresponding to annealing are
10min。
The application further relates to the preparation method of another tft array substrate, as shown in Fig. 2, this method comprises:
Step S210: substrate is provided, forms grid on the substrate, the grid includes copper-molybdenum composite material.
Step S220: insulating layer is covered on the grid.
Step S220: being formed on the insulating layer active layer, and the active layer includes indium gallium zinc oxide.
Step S240: forming source electrode and drain electrode on the active layer, and the source electrode and drain electrode includes gallium zinc oxide.
Step S250: the temperature range of annealing, the annealing is 250 DEG C 2250 DEG C, and the time range of the annealing is
5min215min。
Step S260: passivation layer is formed on the source electrode and the drain electrode, and opens up via hole on the passivation layer.
Step S270: forming pixel electrode on the passivation layer, and the pixel electrode passes through the via hole and the leakage
Pole connection, the pixel electrode includes indium tin oxide.
Specific structure, relevant parameter and the corresponding beneficial effect of the tft array substrate formed through the above steps are
It is being described in detail above, details are not described herein.
The application further relates to a kind of tft array substrate, as shown in Fig. 2, including substrate 110, is formed with grid in substrate 110
Pole 120 covers insulating layer 120 on grid 120, forms active layer 140 on insulating layer 120, and active layer 140 passes through insulating layer 120
It insulate with grid 120, forms source electrode 151 and drain electrode 152 on active layer 140, be formed with passivation on source electrode 151 and drain electrode 152
Layer 160 opens up via hole on passivation layer 160, forms pixel electrode 170 on passivation layer 160, pixel electrode 170 by via hole with
152 connection of drain electrode, wherein source electrode 151 and drain electrode 152 include gallium zinc oxide, and active layer 140 includes indium gallium zinc oxide, as
Plain electrode includes indium tin oxide.In one embodiment, grid 120 includes copper-molybdenum composite material.The specific knot of tft array substrate
Structure and relevant parameter are being described in detail above, and details are not described herein.Tft array substrate in the application, active layer 140 select
With indium gallium zinc oxide, gallium zinc oxide is selected in source electrode 151 and drain electrode 152, and pixel electrode 170 selects indium tin oxide, due to
The work function of indium gallium zinc oxide, gallium zinc oxide and indium tin oxide is close, the tft array substrate of formation, active layer 140
Good Ohmic contact is formed between source electrode 151 and drain electrode 152, contact berrier is smaller, and drain 152 and pixel electrode 170
Between also form good Ohmic contact, contact berrier is smaller, therefore, the leakage current of the thin film transistor (TFT) on tft array substrate
Smaller, current switch is bigger, and device performance increases
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
The limitation to claim therefore cannot be interpreted as.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the concept of this application, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of thin-film transistor array base-plate preparation method characterized by comprising
Substrate is provided, forms grid on the substrate；
Insulating layer is covered on the grid；
It is formed on the insulating layer active layer, the active layer includes indium gallium zinc oxide；
Source electrode and drain electrode is formed on the active layer, and the source electrode and drain electrode includes gallium zinc oxide；
Passivation layer is formed on the source electrode and the drain electrode, and opens up via hole on the passivation layer；And
Pixel electrode is formed on the passivation layer, the pixel electrode is connected by the via hole and the drain electrode, the picture
Plain electrode includes indium tin oxide.
2. thin-film transistor array base-plate preparation method as described in claim 1, which is characterized in that shape on the active layer
After source electrode and drain electrode, further includes:
Annealing, the temperature range of the annealing are 250 DEG C 2250 DEG C, and the time range of the annealing is 5min215min.
3. thin-film transistor array base-plate preparation method as claimed in claim 2, which is characterized in that carried out in nitrogen environment
The annealing.
4. thin-film transistor array base-plate preparation method as described in claim 1, which is characterized in that the indium gallium zinc oxide
Atomic ratio be In:Ga:Zn:O=1:1:1:1.
5. thin-film transistor array base-plate preparation method as described in claim 1, which is characterized in that the thickness of the active layer
Range is 45nm250nm.
6. thin-film transistor array base-plate preparation method as described in claim 1, which is characterized in that the grid includes copper-molybdenum
Composite material.
7. thin-film transistor array base-plate preparation method as claimed in claim 6, which is characterized in that the thickness model of the grid
It encloses for 500nm2550nm.
8. a kind of thin-film transistor array base-plate preparation method characterized by comprising
Substrate is provided, forms grid on the substrate, the grid includes copper-molybdenum composite material；
Insulating layer is covered on the grid；
It is formed on the insulating layer active layer, the active layer includes indium gallium zinc oxide；
Source electrode and drain electrode is formed on the active layer, and the source electrode and drain electrode includes gallium zinc oxide；
Annealing, the temperature range of the annealing are 250 DEG C 2250 DEG C, and the time range of the annealing is 5min215min；
Passivation layer is formed on the source electrode and the drain electrode, and opens up via hole on the passivation layer；And
Pixel electrode is formed on the passivation layer, the pixel electrode is connected by the via hole and the drain electrode, the picture
Plain electrode includes indium tin oxide.
9. a kind of thin-film transistor array base-plate characterized by comprising
Substrate；
Grid is formed in the substrate；
Insulating layer covers the grid；
Active layer is formed on the insulating layer, and the active layer includes indium gallium zinc oxide；
Source electrode and drain electrode is formed on the active layer, and the source electrode and drain electrode includes gallium zinc oxide；
Passivation layer is formed on the source electrode and the drain electrode, offers via hole on the passivation layer；And
Pixel electrode is formed on the passivation layer, and the pixel electrode is connected by the via hole and the drain electrode, the picture
Plain electrode includes indium tin oxide.
10. thin-film transistor array base-plate as claimed in claim 9, which is characterized in that the grid includes copper-molybdenum composite wood
Material.
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| CN102832253A (en) * | 2011-06-14 | 2012-12-19 | 三星电子株式会社 | Thin film transistor, |
| CN103050544A (en) * | 2013-01-17 | 2013-04-17 | 北京大学 | Bottom-gate thin film transistor and preparation method thereof |
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| CN107527956A (en) * | 2017-08-17 | 2017-12-29 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and the method for preparing thin film transistor (TFT) |
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| CN103050544A (en) * | 2013-01-17 | 2013-04-17 | 北京大学 | Bottom-gate thin film transistor and preparation method thereof |
| US20140231810A1 (en) * | 2013-02-21 | 2014-08-21 | Samsung Display Co., Ltd. | Thin film transistor and manufacturing method thereof |
| CN107527956A (en) * | 2017-08-17 | 2017-12-29 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and the method for preparing thin film transistor (TFT) |
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