CN110021531B - Thin film transistor array substrate and preparation method thereof - Google Patents

Thin film transistor array substrate and preparation method thereof Download PDF

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CN110021531B
CN110021531B CN201910225403.9A CN201910225403A CN110021531B CN 110021531 B CN110021531 B CN 110021531B CN 201910225403 A CN201910225403 A CN 201910225403A CN 110021531 B CN110021531 B CN 110021531B
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electrode
drain electrode
array substrate
thin film
active layer
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CN110021531A (en
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孙松
葛邦同
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Chongqing HKC Optoelectronics Technology Co Ltd
Beihai HKC Optoelectronics Technology Co Ltd
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Chongqing HKC Optoelectronics Technology Co Ltd
Beihai HKC Optoelectronics Technology Co Ltd
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
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  • Thin Film Transistor (AREA)

Abstract

The application relates to a TFT array substrate and a preparation method thereof, wherein the TFT array substrate comprises: a substrate; a gate formed on the substrate; an insulating layer covering the gate electrode; an active layer formed on the insulating layer, the active layer including indium gallium zinc oxide; a source electrode and a drain electrode formed on the active layer, the source electrode and the drain electrode including gallium zinc oxide; the passivation layer is formed on the source electrode and the drain electrode, and a through hole is formed in the passivation layer; and the pixel electrode is formed on the passivation layer, is connected with the drain electrode through the through hole and comprises indium tin oxide. The indium gallium zinc oxide is used as an active layer, the gallium zinc oxide is used as a source electrode and a drain electrode, and the indium tin oxide is used as a pixel electrode, so that the contact potential barrier between the pixel electrode and the drain electrode and the contact potential barrier between the source electrode and the active layer can be reduced, and the performance of the device is improved.

Description

Thin film transistor array substrate and preparation method thereof
Technical Field
The present disclosure relates to the field of display, and more particularly, to a thin film transistor array substrate and a method for manufacturing the same.
Background
A Thin Film Transistor (TFT) array is formed on the Thin Film Transistor array substrate, and the Thin Film Transistor specifically includes a gate electrode, an insulating layer, an active layer, and a source electrode and a drain electrode formed on the active layer, which are sequentially stacked, wherein the gate electrode is connected to a scan line, the source electrode is connected to a data line, and the drain electrode is connected to a pixel electrode. However, the current leakage current of the current thin film transistor is significant, the current on-off ratio of the thin film transistor is low, and the device performance is difficult to improve.
Disclosure of Invention
Accordingly, it is necessary to provide a thin film transistor array substrate and a method for manufacturing the same, aiming at the technical problems of significant leakage current and low current on-off ratio of the thin film transistor in the TFT array substrate.
A preparation method of a thin film transistor array substrate comprises the following steps:
providing a substrate, and forming a grid electrode on the substrate;
covering an insulating layer on the grid;
forming an active layer on the insulating layer, the active layer including indium gallium zinc oxide;
forming a source electrode and a drain electrode on the active layer, the source electrode and the drain electrode including gallium zinc oxide;
forming a passivation layer on the source electrode and the drain electrode, and forming a through hole on the passivation layer; and
and forming a pixel electrode on the passivation layer, wherein the pixel electrode is connected with the drain electrode through the through hole, and the pixel electrode comprises indium tin oxide.
In one embodiment, after forming a source electrode and a drain electrode on the active layer, the method further includes:
and annealing, wherein the annealing temperature range is 250-350 ℃, and the annealing time range is 5-15 min.
In one embodiment, the annealing is performed in a nitrogen ambient.
In one embodiment, the atomic ratio of indium gallium zinc oxide is In: ga: zn: o ═ 1:1:1: 1.
In one embodiment, the thickness of the active layer is in a range of 45nm to 50 nm.
In one embodiment, the gate comprises a copper molybdenum composite.
In one embodiment, the thickness of the gate electrode ranges from 500nm to 550 nm.
The preparation method of the TFT array substrate adopts Indium Tin Oxide (ITO) as a pixel electrode, Indium Gallium Zinc Oxide (IGZO) as an active layer, gallium Zinc Oxide (GZO) is used as a source electrode and a drain electrode, the work functions of the gallium zinc oxide, indium tin oxide and indium gallium zinc oxide are relatively close, the drain electrode and the source electrode which are made of the gallium zinc oxide and the pixel electrode which is made of the indium tin oxide can form good ohmic contact, the contact barrier is small, meanwhile, the drain electrode made of the gallium zinc oxide and the active layer made of the indium gallium zinc oxide can form good ohmic contact, the contact barrier is also small, that is, good ohmic contact can be formed between the source and drain electrodes and the active layer, and between the drain electrode and the pixel electrode, and therefore, the leakage current can be reduced to a certain extent, the current switching ratio of the thin film transistor is improved, and the threshold voltage is reduced. Meanwhile, the gallium-zinc oxide is used as the source electrode and the drain electrode, and the gallium-zinc oxide is a transparent material, so that compared with the traditional method in which opaque metal is used as the source electrode and the drain electrode, in the application, light incident to the drain electrode can also penetrate through the drain electrode to participate in image display, thereby increasing the light transmission area of the whole TFT array substrate and improving the image quality of a display product.
The application also relates to another preparation method of the thin film transistor array substrate, which comprises the following steps:
providing a substrate, and forming a grid on the substrate, wherein the grid comprises a copper-molybdenum composite material;
covering an insulating layer on the grid;
forming an active layer on the insulating layer, the active layer including indium gallium zinc oxide;
forming a source electrode and a drain electrode on the active layer, the source electrode and the drain electrode including gallium zinc oxide;
annealing, wherein the annealing temperature range is 250-350 ℃, and the annealing time range is 5-15 min;
forming a passivation layer on the source electrode and the drain electrode, and forming a through hole on the passivation layer; and
and forming a pixel electrode on the passivation layer, wherein the pixel electrode is connected with the drain electrode through the through hole, and the pixel electrode comprises indium tin oxide.
The present application also provides a thin film transistor array substrate, including:
a substrate;
a gate formed on the substrate;
an insulating layer covering the gate electrode;
an active layer formed on the insulating layer, the active layer including indium gallium zinc oxide;
a source electrode and a drain electrode formed on the active layer, the source electrode and the drain electrode including gallium zinc oxide;
the passivation layer is formed on the source electrode and the drain electrode, and a through hole is formed in the passivation layer; and
and the pixel electrode is formed on the passivation layer and is connected with the drain electrode through the through hole, and the pixel electrode comprises indium tin oxide.
In one embodiment, the gate comprises a copper molybdenum composite.
Drawings
Fig. 1 is a flow chart illustrating a process for manufacturing a thin film transistor array substrate according to the present invention;
fig. 2 is a flow chart illustrating a manufacturing process of another thin film transistor array substrate according to the present application;
fig. 3 is a partial cross-sectional view of a thin film transistor array substrate according to an embodiment of the present disclosure.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
In the present application, as shown in fig. 1, a flow chart of steps of a method for manufacturing a TFT array substrate is shown, and the method includes:
step S110: providing a substrate, and forming a grid electrode on the substrate.
In one embodiment, as shown in fig. 3, a substrate 110 is provided, and a gate 120 is formed on the substrate 100. The substrate 110 is made of transparent or semitransparent material, and is generally a glass substrate. In one embodiment, the material of the gate 120 may include a copper molybdenum composite. The copper-molybdenum composite material has lower resistivity, can reduce the attenuation of electric signals, and the formed grid 120 has better uniformity, good stability and higher repairing success rate. In one embodiment, when the gate electrode 120 is made of a copper-molybdenum composite material, the thickness of the gate electrode 120 ranges from 500nm to 550nm, and the gate electrode in the thickness range has a lower resistivity, so that the delay and attenuation of the scan line signal are reduced.
Step S120: an insulating layer overlies the gate.
As shown in fig. 3, the gate 120 is covered with an insulating layer 130. The insulating layer 130 may be made of a transparent material, such as silicon oxide or aluminum oxide.
Step S130: an active layer is formed on the insulating layer, the active layer including indium gallium zinc oxide.
As shown in FIG. 3, an active layer 140 is formed on the insulating layer 130, and the active layer 140 passes through the insulating layer 130 and the gate electrode120 insulating and the active layer 140 comprises indium gallium zinc oxide. Compared with the traditional amorphous silicon film layer, the indium gallium zinc oxide film layer has higher mobility and aperture opening ratio and better uniformity. In the indium gallium zinc oxide film layer, the lower the oxygen content, the higher the electron mobility, and studies have shown that In3+Specific ratio of Zn to Zn2+And Ga3+The conductive material is more favorable for electron conduction, the combination of Ga and oxygen is stronger, the formation of oxygen vacancy can be inhibited, and the stability of the device can be improved, wherein when the oxygen content is less, the oxygen is preferentially combined with Ga to improve the stability of the device, so In3+Is favorable for improving the mobility of the device, but a large number of experiments prove that In3+Although the mobility of the device can be greatly improved, the substitution of In atoms for Zn atoms releases a redundant electron, and finally the carrier concentration of the active layer is too high, so that the working mode of the device is changed into a depletion mode; meanwhile, when the oxygen content is too much, the oxygen vacancy is increased, the conductivity of the film is deteriorated, and simultaneously, more oxygen is combined with In and Zn, so that the mobility of the device is reduced, and the performance of the device is reduced. In one embodiment, the atomic ratio of indium gallium zinc oxide is In: ga: zn: the indium gallium zinc oxide film layer with the atomic ratio has certain semiconductor performance and better electron mobility. In one embodiment, when the active layer 140 is an InGaZn oxide film, the thickness of the active layer 140 is in a range of 45nm to 50 nm. The thickness of the active layer 140 affects the output characteristics of the thin film transistor, the thickness of the active layer 140 is too thin, the carrier transport function is limited, the mobility is low, the thickness of the active layer 140 is too large, the number of existing defect states is large, and the carrier is enhanced by capturing or scattering, so that the sub-threshold swing amplitude is deteriorated.
Step S140: forming a source electrode and a drain electrode on the active layer, the source electrode and the drain electrode including a gallium zinc oxide.
As shown in fig. 3, a source electrode 151 and a drain electrode 152 are formed on the active layer 140, and the source electrode 151 and the drain electrode 152 include gallium zinc oxide. In one embodiment, the source electrode 151 and the drain electrode 152 may be formed by a magnetron sputtering process, and the thickness of the source electrode 151 and the drain electrode 152 ranges from 300nm to 350 nm.
Step S150: and forming a passivation layer on the source electrode and the drain electrode, and forming a through hole on the passivation layer.
As shown in fig. 3, a passivation layer 160 is formed on the source electrode 151 and the drain electrode 152, and a via hole is opened on the passivation layer 160 and is directly above the drain electrode 152. The passivation layer 160 may be made of a transparent material, such as silicon oxide or aluminum oxide
Step S160: and forming a pixel electrode on the passivation layer, wherein the pixel electrode is connected with the drain electrode through the through hole, and the pixel electrode comprises indium tin oxide.
As shown in fig. 3, a pixel electrode 170 is formed on the passivation layer 160, the pixel electrode 170 is connected to the drain electrode 152 through a via hole, and the pixel electrode 170 includes indium tin oxide.
In the thin film transistor, a source drain electrode is in contact with an active layer, a pixel electrode is in contact with a drain electrode, the pixel electrode in the traditional technology is usually made of indium tin oxide, the active layer is made of amorphous silicon, the source drain electrode is usually made of metals such as molybdenum, aluminum or copper, the contact barrier between the drain electrode and the pixel electrode is large, the contact barrier between the active layer and the source drain electrode is also large, the contact barrier is large, the leakage current is large, and the current on-off ratio of the thin film transistor is low, so that the performance of the device is limited. In the present application, the drain 152 is in contact with the pixel electrode 170, wherein the source 151 and the drain 152 are made of gallium zinc oxide, the pixel electrode 170 is made of indium tin oxide, and the pixel electrode 170 is in contact with the drain 152 because work functions of gallium zinc oxide and indium tin oxide are relatively close, and a contact barrier formed by a contact interface of the pixel electrode 170 and the drain 152 is relatively low, so that a good ohmic contact is provided; meanwhile, the active layer 140 is made of indium gallium zinc oxide, and the work functions of the indium gallium zinc oxide and the gallium zinc oxide are relatively close to each other, so that the contact potential barrier between the source 151 and the drain 152 and the active layer 140 is relatively low, and good ohmic contact is achieved. Meanwhile, as compared with the case of using metal as the source/drain electrode and not being transparent, in this embodiment, as shown in fig. 3, the dashed-line frame position can also be transparent, and light can sequentially pass through the TFT substrate 110, the insulating layer 130, the drain electrode 152 and the pixel electrode 170, thereby increasing the light-permeable area of the TFT array substrate.
In one embodiment, annealing is performed after the source electrode and the drain electrode are formed, wherein the annealing temperature ranges from 250 ℃ to 350 ℃, and the annealing time ranges from 5min to 15 min.
After the source electrode 151 and the drain electrode 152 are formed, annealing is carried out on the source electrode 151 and the drain electrode 152 to reduce defects of the source electrode 151 and the drain electrode 152, the annealing temperature range is 250-350 ℃, the annealing time range is 5-15 min, after annealing is carried out under the parameters, on one hand, the work function of the gallium zinc oxide is closer to that of indium tin oxide and indium gallium zinc oxide, on the other hand, the transparency of the gallium zinc oxide is improved, the light transmittance of the drain electrode is enhanced, after annealing in the parameter range, the transparency of the gallium zinc oxide is improved, and the light transmittance of the gallium zinc oxide is over 80%. In an embodiment, the annealing step is performed in a nitrogen atmosphere, the nitrogen is an inert gas, and the annealing is performed in the nitrogen atmosphere, so that the thin film transistor is prevented from being influenced by other impurities in the annealing process. In one embodiment, the annealing temperature may be 300 ℃, which corresponds to 10min of annealing time.
The present application also relates to another method for manufacturing a TFT array substrate, as shown in fig. 2, the method includes:
step S210: providing a substrate, and forming a grid electrode on the substrate, wherein the grid electrode comprises a copper-molybdenum composite material.
Step S220: an insulating layer overlies the gate.
Step S230: an active layer is formed on the insulating layer, the active layer including indium gallium zinc oxide.
Step S240: forming a source electrode and a drain electrode on the active layer, the source electrode and the drain electrode including a gallium zinc oxide.
Step S250: and annealing, wherein the annealing temperature range is 250-350 ℃, and the annealing time range is 5-15 min.
Step S260: and forming a passivation layer on the source electrode and the drain electrode, and forming a through hole on the passivation layer.
Step S270: and forming a pixel electrode on the passivation layer, wherein the pixel electrode is connected with the drain electrode through the through hole, and the pixel electrode comprises indium tin oxide.
The detailed structure, related parameters and corresponding beneficial effects of the TFT array substrate formed through the above steps are described in detail above, and are not described herein again.
The present application also relates to a TFT array substrate, as shown in fig. 3, which includes a substrate 110, a gate electrode 120 formed on the substrate 110, an insulating layer 130 covering the gate electrode 120, an active layer 140 formed on the insulating layer 130, the active layer 140 insulated from the gate electrode 120 by the insulating layer 130, a source electrode 151 and a drain electrode 152 formed on the active layer 140, a passivation layer 160 formed on the source electrode 151 and the drain electrode 152, a via hole formed on the passivation layer 160, a pixel electrode 170 formed on the passivation layer 160, the pixel electrode 170 connected to the drain electrode 152 by the via hole, wherein the source electrode 151 and the drain electrode 152 include gallium zinc oxide, the active layer 140 includes indium gallium zinc oxide, and the pixel electrode includes indium tin oxide. In one embodiment, the gate 120 comprises a copper molybdenum composite. The detailed structure and related parameters of the TFT array substrate are described above, and will not be described herein. In the TFT array substrate of the present application, the active layer 140 is selected from an indium gallium zinc oxide, the source 151 and the drain 152 are selected from a gallium zinc oxide, and the pixel electrode 170 is selected from an indium tin oxide, because work functions of the indium gallium zinc oxide, the gallium zinc oxide, and the indium tin oxide are close to each other, a good ohmic contact is formed between the active layer 140 and the source 151 and the drain 152, a contact barrier is small, and a good ohmic contact is also formed between the drain 152 and the pixel electrode 170, and the contact barrier is small, therefore, a leakage current of a thin film transistor on the TFT array substrate is small, a current switch is large, and device performance is improved to some extent
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A preparation method of a thin film transistor array substrate is characterized by comprising the following steps:
providing a substrate, and forming a grid electrode on the substrate;
covering an insulating layer on the grid;
forming an active layer on the insulating layer, the active layer including indium gallium zinc oxide;
forming a source electrode and a drain electrode on the active layer, the source electrode and the drain electrode including gallium zinc oxide;
annealing, wherein the annealing temperature range is 250-350 ℃, and the annealing time range is 5-15 min;
forming a passivation layer on the source electrode and the drain electrode, and forming a through hole on the passivation layer; and
and forming a pixel electrode on the passivation layer, wherein the pixel electrode is connected with the drain electrode through the through hole, and the pixel electrode comprises indium tin oxide.
2. The method of manufacturing a thin film transistor array substrate of claim 1, wherein the annealing is performed in a nitrogen atmosphere.
3. The method of manufacturing a thin film transistor array substrate of claim 1, wherein an atomic ratio of the indium gallium zinc oxide is In: ga: zn: o =1:1:1: 1.
4. The method of manufacturing a thin film transistor array substrate of claim 1, wherein the active layer has a thickness ranging from 45nm to 50 nm.
5. The method of manufacturing a thin film transistor array substrate of claim 1, wherein the gate electrode comprises a copper molybdenum composite.
6. The method of manufacturing a thin film transistor array substrate of claim 5, wherein the gate electrode has a thickness ranging from 500nm to 550 nm.
7. The method of manufacturing a thin film transistor array substrate of claim 1, wherein the source and drain electrodes have a thickness ranging from 300nm to 350 nm.
8. The method of manufacturing a thin film transistor array substrate of claim 1, wherein the insulating layer is made of silicon oxide or aluminum oxide.
9. A thin film transistor array substrate, comprising:
a substrate;
a gate formed on the substrate;
an insulating layer covering the gate electrode;
an active layer formed on the insulating layer, the active layer including indium gallium zinc oxide;
a source electrode and a drain electrode formed on the active layer, the source electrode and the drain electrode including gallium zinc oxide;
the passivation layer is formed on the source electrode after annealing treatment and the drain electrode after annealing treatment, a through hole is formed in the passivation layer, the temperature range of the annealing treatment is 250-350 ℃, and the time range of the annealing treatment is 5-15 min; and
and the pixel electrode is formed on the passivation layer and is connected with the drain electrode through the through hole, and the pixel electrode comprises indium tin oxide.
10. The thin film transistor array substrate of claim 9, wherein the gate electrode comprises a copper molybdenum composite.
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CN107527956A (en) * 2017-08-17 2017-12-29 京东方科技集团股份有限公司 Thin film transistor (TFT) and the method for preparing thin film transistor (TFT)

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