CN109952634A - 在漏极指尖与源极之间具有导电势垒的hemt - Google Patents

在漏极指尖与源极之间具有导电势垒的hemt Download PDF

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CN109952634A
CN109952634A CN201780070648.8A CN201780070648A CN109952634A CN 109952634 A CN109952634 A CN 109952634A CN 201780070648 A CN201780070648 A CN 201780070648A CN 109952634 A CN109952634 A CN 109952634A
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drain
barrier layer
hemt
source electrode
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J·乔
N·蒂皮尔内尼
C·S·舒
S·彭德哈卡
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Texas Instruments Inc
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Abstract

在所描述实例中，高电子迁移率晶体管HEMT(340)包含在衬底(102)上的有源层(104)及在所述有源层(104)上的IIIA‑N族势垒层(106)。隔离区域(110)穿过所述势垒层(106)以提供在所述有源层(104)上包含所述势垒层(106)的至少一个经隔离有源区(106/104)。栅极(114)在所述势垒层(106)上方。漏极包含至少一个漏极指状件(120a)，所述至少一个漏极指状件包含具有延伸到所述势垒层(106)中以与所述有源层(104)接触的漏极触点(120b)的指尖(120a1)，且源极(122)具有延伸到所述势垒层(106)中以与所述有源层(104)接触的源极触点(122a)。所述源极(122)形成包围所述漏极的环圈。所述隔离区域(110)包含定位于所述源极(122)与漏极触点(120b)之间的一部分(110”)，因此导电势垒在长度方向上位于所述指尖(120a1)的所述漏极触点(120b)与所述源极(122)之间。

Description

在漏极指尖与源极之间具有导电势垒的HEMT
技术领域
本发明涉及IIIA-N族(例如，氮化镓)高电子迁移率场效晶体管(HEMT)。
背景技术
氮化镓(GaN)为常用于电子装置的IIIA-N族材料，其中例如Ga(以及硼、铝、铟及铊)的IIIA族元素有时还称为13族元素。GaN为具有纤锌矿晶体结构的二元IIIA/V直接带隙半导体。针对在光电子学以及高功率及高频率电子装置中的各种应用，在室温下为3.4eV的其相对较宽带隙(对比在室温下硅的1.1eV)给其提供特殊性质。
基于GaN的HEMT以在具有不同带隙的两种材料之间存在结以形成异质结或异质结构为特征。所述HEMT结构基于描述为二维电子气(2DEG)的非常高的电子迁移率，所述二维电子气由于压电效应及自然极化效应而就在大体内在有源层(其通常包括GaN)上的势垒层(其通常包括AlGaN)之间的异质结构界面下面形成。功率FET装置具有栅极、源极电极及漏极电极，其中所述源极电极及漏极电极各自包含延伸穿过顶部势垒层以在有源层的表面中形成与下伏2DEG的欧姆接触的触点。一个IIIA-N族HEMT布局为漏极居中布局，其中高电压漏极区完全被栅极且被源极封围。此布局具有包含关于装置隔离、边缘端接及泄漏电流控制的优点。
发明内容
在所描述实例中，对于漏极居中的IIIA-N族HEMT，在装置操作期间在漏极指状件的指尖的漏极触点附近，一般来说，高浓度的“热”载流子尤其在高功率切换条件下可使装置降级且损坏装置(例如，使装置熔融)。通过在漏极指状件的漏极触点指尖周围提供穿过势垒层的隔离区域，使得所得导电势垒设置于漏极指状件的长度方向上位于指尖的漏极触点与源极之间，导电势垒抑制热载流子注入问题，因此改进装置稳健性及可靠性。
隔离区域可通过图案化势垒层以形成具有邻近导电势垒的有源区台面结构而形成，或可在不需要蚀刻势垒层的情况下包括经植入隔离区域。在具有邻近导电势垒的有源区台面的情形中，可通过使用灰度掩模来将台面边界修圆以抑制可以其它方式沿着台面边缘发生的泄漏或击穿。
附图说明
图1A到C提供根据实例性实施例的与用于形成IIIA-N族HEMT的实例性方法中的步骤对应的连续顶部透视横截面视图，所述IIIA-N族HEMT具有包含定位于源极与漏极触点之间的一部分的隔离区域，因此导电势垒在漏极指状件的长度方向上位于漏极触点指尖与源极之间。图1C中的视图从图1A及1B中所展示的视图旋转180度，且仅展示图1A及1B中所展示的有源区的一部分。
图2是根据实例性实施例的具有在隔离区域上的漏极指尖的IIIA-N族HEMT的俯视图。
图3A是具有漏极居中布局的常规IIIA-N族HEMT的一部分的放大俯视图。
图3B是具有漏极居中布局的第一实例性IIIA-N族HEMT的一部分的放大俯视图，所述第一实例性IIIA-N族HEMT具有包含定位于源极与漏极触点之间的一部分的隔离区域，因此导电势垒在漏极指状件的长度方向上位于指尖的漏极触点与源极之间。
图3C是具有漏极居中布局的第二实例性IIIA-N族HEMT的一部分的放大俯视图，所述第二实例性IIIA-N族HEMT具有包含定位于源极与漏极触点之间的一部分的隔离区域，因此导电势垒在漏极指状件的长度方向上位于指尖的漏极触点与源极之间。
图3D是具有漏极居中布局的另一IIIA-N族HEMT的一部分的放大俯视图，所述另一IIIA-N族HEMT具有包含定位于源极与漏极触点之间的隔离区域部分的隔离区域，因此导电势垒在漏极指状件的长度方向上位于指尖的漏极触点与源极之间。HEMT以其漏极触点在漏极指状件的长度方向上延伸超过源极触点以进一步抑制电流拥挤效应为特征。
图4展示将来自具有常规漏极居中布局的IIIA-N族HEMT的结果与来自具有以下漏极居中布局的所描述IIIA-N族HEMT的结果进行比较的实际600V硬切换合格率数据，所述所描述IIIA-N族HEMT在包含定位于源极与漏极触点之间的一部分的隔离区域上具有漏极触点，因此导电势垒在漏极指状件的长度方向上位于漏极触点指尖与源极之间。
具体实施方式
图式未必按比例绘制。在图式中，相似参考编号指定类似或等效元件。动作或事件的所图解说明排序不应被视为限制性的，因为一些动作或事件可以不同次序发生及/或与其它动作或事件同时发生。此外，一些所图解说明的动作或事件可为实施根据本说明的方法论任选的。
如本文中在不具有进一步限定条件的情况下所使用，术语“耦合到”或“与……耦合”(及类似术语)描述间接或直接电连接。因此，如果第一装置“耦合”到第二装置，那么所述连接可通过其中在路径中仅存在寄生现象的直接电连接或通过经由包含其它装置及连接的介入物项的间接电连接。对于间接耦合，介入物项一般不修改信号的信息但可调整其电流电平、电压电平及/或功率电平。
图1A到C提供根据实例性实施例的与用于形成所描述IIIA-N族HEMT的实例性方法中的步骤对应的连续顶部透视横截面视图，所述所描述IIIA-N族HEMT具有包含定位于源极与漏极触点之间的一部分的隔离区域，因此导电势垒在漏极触点指尖的漏极触点及源极的长度方向上。如上文中所描述，图1C中的视图从图1A及1B中所展示的视图旋转180度，且仅展示图1A及1B中所展示的有源区的一部分。
工艺中HEMT在图1A中展示为包括衬底102、在衬底102上的至少一个IIIA-N族缓冲层103、在缓冲层103上的IIIA-N族有源层104及在有源层104上的IIIA-N族势垒层106。在有源层104中在其异质结附近贯穿其与势垒层106的界面形成2DEG。势垒层106、有源层104及缓冲层103一般全部为衬底102上的外延层。用于界定隔离区域110(其界定有源区)的经图案化掩蔽材料108(例如，光致抗蚀剂)展示为在势垒层106上。举例来说，仅展示T形图案形状。
衬底102可包括蓝宝石、硅、碳化硅(SiC)或GaN。IIIA-N族缓冲层103一般存在于衬底102上，但当使用氮化镓(GaN)衬底时不需要IIIA-N族缓冲层103。举例来说，有源层104可包括25到1,000纳米的GaN。可形成有源层104以便最少化可对电子迁移率具有不利效应的晶体缺陷。有源层104通常为未经掺杂的(例如，未经掺杂GaN)。
举例来说，势垒层106可包括8到30纳米的AlxGa1-xN或InxAlyGa1-x-yN。而且，举例来说，势垒层106中的IIIA族元素的组合物可为24到28原子重量％氮化铝及72到76原子重量％氮化镓。在有源层104上形成势垒层106会在有源层104中贯穿其与势垒层106的界面就在势垒层106下面(例如)以1×1012到2×1013cm-2的电子密度产生2DEG。势垒层106可在势垒层106的顶部表面上包含任选覆盖层，例如包括GaN。
用作隔离掩模的经图案化掩蔽材料108用于从势垒层106及有源层104形成至少界定经隔离有源区的隔离区域110，其中图1B中所展示的结果展示两个有源区106/104。图1B展示环绕经隔离有源区106/104的缺乏势垒层106的隔离区域110，从而在有源层104上具有势垒层106以提供2DEG。举例来说，使用经图案化掩蔽材料108的隔离掩模可包含通过光学光刻工艺形成的200纳米到2微米的光致抗蚀剂。形成隔离区域110可包括台面蚀刻工艺。举例来说，可使用灰度掩模来图案化毯式势垒层106，后续接着用以提供修圆边缘的蚀刻。如图1B中所展示，除蚀刻穿过势垒层106以外，此台面蚀刻工艺还移除有源层104的一部分。
使用灰度掩模使得微型光刻机能够使用借助包括亚分辨率像素的自定义衰减掩模进行的单次曝光来将抗蚀剂塑形。使用经图案化掩蔽材料108的隔离工艺还可为将掺杂剂选择性地植入到势垒层106中及有源层104中以形成经重掺杂隔离势垒的一种(若干种)隔离植入。在任一情形中，隔离区域110用作减少或消除2DEG中的横越穿过其的电流的导电势垒。
栅极114、漏极触点120b及具有源极触点122a的源极122形成于有源区106/104内，其中图1C中所展示的结果为有源区106/104的一部分包含漏极触点120b(其中其漏极指状件120a包含漏极指尖120a1)的一部分及所展示的源极122及源极触点122a的一部分。如上文中所描述，图1C中的视图从图1A及1B中所展示的视图旋转180度，且每一有源区106/104仅为图1A及1B中所展示内容的一部分。栅极114展示为形成于势垒层106上方。源极触点及漏极触点一般通过经掩蔽蚀刻工艺来形成，所述经掩蔽蚀刻工艺选择性地蚀刻势垒层106的厚度的一部分以延伸到势垒层106中，从而提供与在有源层104中在势垒层106与有源层104之间的界面附近的2DEG的良好(低电阻)接触。
尽管未在所提供的视图中展示，但源极122形成包围漏极的完整环圈(参见图2，源极122提供对漏极120的包围)。图1C展示实例性有源区边界141及常规有源区边界147的位置。有源区边界141的位置致使指尖120a1在包含定位于源极122与漏极触点120b之间的隔离区域部分的隔离区域110上方，因此导电势垒在漏极指状件120a中的漏极触点120b的长度方向上位于指尖120a1的漏极触点与源极122之间。相比之下，常规有源区边界147的位置致使指尖120a1在有源区106/104上方，因此在漏极指状件120a中的漏极触点120b的长度方向上位于指尖120a1的漏极触点与源极122之间没有导电势垒，这在如上文中所描述的装置操作期间不合意地致使热载流子在源极122与指尖120a中的漏极触点120b之间流动。
栅极114、包含漏极触点120b的漏极及包含源极触点122a的源极一般都包括金属，例如在一个特定实施例中包括TiW合金。可通过溅镀金属堆叠(例如在另一特定实施例中为Ti/Al/TiN)而形成相应电极。尽管未在图1C中展示，但源极及漏极金属层一般在电介质层的顶部上，所述电介质层在势垒层106的顶部上且在栅极上方以阻止与栅极的短路。
图2是根据实例性实施例的包含2指IIIA-N族HEMT 200的集成电路(IC)250的俯视图，2指IIIA-N族HEMT 200具有包含定位于源极122与漏极120的漏极触点120b之间的隔离部分的隔离区域110，因此导电势垒在漏极指状件120a中的漏极触点120b的长度方向上位于其指尖120a1与源极122之间。IC 250还包含在另一有源区106/104上展示为块240及245的其它电路，例如以用于实现DC/DC功率转换器IC。尽管未在图2(或图3A到3D)中明确展示，但提供栅极114及源极122的金属之间存在电隔离。在一个实施例中，电介质层在栅极114的金属上方，其中源极122的金属在栅极金属上的电介质层的顶部上以形成场板。在另一实施例中，源极122及栅极114的金属之间存在间隔，使得不需要源极及栅极金属之间的此电介质层。
漏极120的区展示为完全被栅极114及源极122两者封围。有源区106/104经展示以被仅包含有源层104(不包含势垒层106)的隔离区域110封围。在此实施例中，有源区106/104可包括台面(其高度由于有源层104上的未经移除势垒层106而提升)，相比于在台面实施例中至少缺乏势垒层106的隔离区域110。栅极为114。实例性有源区边界141(也在图2中)展示为在漏极触点120b下面。
图3A是具有漏极居中布局的常规IIIA-N族HEMT 300的一部分的放大俯视图。在HEMT 300的操作期间的电子流由在从源极122到漏极指状件120a的指尖120a1中的漏极触点120b的路径中以180度弧延伸的箭头展示。此电子流模式产生高浓度的‘热’载流子，所述‘热’载流子尤其在高电流切换条件下可使HEMT装置降级且破坏HEMT装置(例如，使HEMT装置熔融)。
图3B是具有漏极居中布局的IIIA-N族HEMT 320的一部分的放大俯视图，IIIA-N族HEMT 320具有包含定位于源极122与漏极触点120b之间的隔离区域部分110’的隔离区域110，因此导电势垒在漏极指状件120a的长度方向上位于指尖120a1的漏极触点120b与源极122之间。通过在漏极指状件120a的指尖120a1周围提供穿过势垒层106以至少暴露有源层104的隔离区域部分110’，使得所得导电势垒设置于漏极指状件的长度方向上位于指尖120a1的漏极触点120b与源极122之间，导电势垒抑制热载流子注入问题，因此改进装置稳健性及可靠性。导电势垒110’展示为在从源极122到指尖120a1的漏极触点120b的路径中穿过至少150度弧阻挡导电。
图3C是具有漏极居中布局的IIIA-N族HEMT 340的一部分的放大俯视图，IIIA-N族HEMT 340具有包含定位于源极122与漏极触点120b之间的隔离区域部分110”的隔离区域110，因此导电势垒在漏极指状件120a的长度方向上位于指尖120a1的漏极触点120b与源极122之间。有源区边界141的拉回位置产生隔离切割线且因此隔离区域部分110”与漏极触点120b分开，展示为在漏极触点120b下面。通过在漏极指状件120a的指尖120a1周围提供穿过势垒层106以暴露有源层104的隔离区域部分110’，因此所得导电势垒110”设置于漏极指状件的长度方向上位于指尖120a1的漏极触点120b与源极122之间，抑制热载流子注入问题，因此改进装置稳健性及可靠性。
图3D为具有漏极居中布局的另一IIIA-N族HEMT 370的一部分的放大俯视图，另一IIIA-N族HEMT 370具有包含定位于源极122与漏极触点120b之间的隔离区域部分110”的隔离区域110，因此导电势垒在漏极指状件120a的长度方向上位于指尖120a1中的漏极触点120b与源极122之间。如在图3C中，有源区边界141的拉回位置产生隔离切割线且因此隔离区域部分110”与漏极触点120b分开，展示为在漏极触点120b下面。HEMT 370以其漏极触点120b在漏极指状件120a的长度方向上延伸超过源极触点122a以进一步抑制电流拥挤效应为特征，且以其它方式类似于图3C中所展示的HEMT340。展示为375的漏极触点延伸距离可为从大约1μm到大约100μm。
所描述HEMT适用于增强及耗尽模式装置两者。所描述HEMT可体现为离散装置或在例如功率转换器(例如，DC/DC转换器)及功率开关的IC上。
图4展示将来自具有漏极居中布局的常规IIIA-N族HEMT的结果与来自具有漏极居中布局的所描述IIIA-N族HEMT的结果进行比较的实际600V硬切换合格率数据，所述所描述IIIA-N族HEMT具有包含定位于源极与漏极触点之间的一部分的所描述隔离区域110，因此导电势垒在漏极指状件的长度方向上位于指尖120a1的漏极触点120b与源极122之间。切换合格率针对所描述IIIA-N族HEMT被展示为>99％(与针对常规IIIA-N族HEMT的大致72％相比较)。
可使用所描述实施例来形成半导体裸片，所述半导体裸片可为离散装置或集成到各种装配流程中以形成各种不同装置及相关产品的集成电路的一部分。所述半导体裸片可包含在其中的各种元件及/或在其上的层，包含势垒层、电介质层、装置结构、有源元件及无源元件，包含源极区域、漏极区域、位线、基极、射极、集极、导电线、导电通孔等。此外，半导体裸片可由包含双极、绝缘栅极双极晶体管(IGBT)、CMOS、BiCMOS及MEMS的各种工艺形成。
修改在所描述实施例中是可能的，且其它实施例在权利要求书的范围内也是可能的。

Claims (16)

1.一种形成高电子迁移率晶体管HEMT的方法，其包括：
提供衬底；
在所述衬底上形成IIIA-N族有源层；
在所述有源层上形成IIIA-N族势垒层；
穿过所述势垒层形成至少一个隔离区域，以提供在所述有源层上包括所述势垒层的至少一个经隔离有源区；
在所述势垒层上方形成栅极；
形成漏极，所述漏极包括至少一个漏极指状件，所述至少一个漏极指状件包含具有延伸到所述势垒层中以提供与所述有源层的接触的漏极触点的指尖，及
形成源极，所述源极具有延伸到所述势垒层中以提供与所述有源层的接触的源极触点，其中所述源极形成包围所述漏极的环圈，
其中所述隔离区域包含定位于所述源极与所述漏极触点之间的一部分，因此导电势垒在所述漏极指状件的长度方向上位于所述指尖(漏极触点指尖)的所述漏极触点与所述源极之间。
2.根据权利要求1所述的方法，其中所述指尖为弯曲区域，且所述导电势垒在从所述源极到所述漏极触点指尖的路径中穿过至少150度弧阻挡导电。
3.根据权利要求1所述的方法，其中所述形成所述隔离区域包括蚀刻穿过所述势垒层的台面蚀刻工艺。
4.根据权利要求3所述的方法，其中所述形成所述隔离区域包括使用灰度掩模进行图案化，使得所述台面蚀刻工艺为所述经隔离有源区的边缘提供修圆边缘。
5.根据权利要求1所述的方法，其中所述形成所述隔离区域包括经掩蔽离子植入工艺。
6.根据权利要求1所述的方法，其包括在形成所述IIIA-N族有源层之前在所述衬底上形成至少一个缓冲层，其中所述衬底包括硅，其中所述IIIA-N族有源层包括未经掺杂GaN，且所述势垒层包括AlGaN。
7.根据权利要求1所述的方法，其中所述漏极触点延伸超过所述源极触点以进一步抑制电流拥挤效应。
8.根据权利要求1所述的方法，其中所述HEMT为形成于所述衬底中且形成于所述衬底上的集成电路IC的一部分。
9.一种高电子迁移率晶体管HEMT，其包括：
衬底；
有源层，其在所述衬底上；
IIIA-N族势垒层，其在所述有源层上；
至少一个隔离区域，其穿过所述势垒层以提供在所述有源层上包括所述势垒层的至少一个经隔离有源区；
栅极，其在所述势垒层上方；
漏极，其包括至少一个漏极指状件，所述至少一个漏极指状件包含具有延伸到所述势垒层中以提供与所述有源层的接触的漏极触点的指尖，及
源极，其包含延伸到所述势垒层中以提供与所述有源层的接触的源极触点，其中所述源极形成包围所述漏极的环圈；
其中所述隔离区域包含定位于所述源极与所述漏极触点之间的一部分，因此导电势垒在所述漏极指状件的长度方向上位于所述指尖(漏极触点指尖)的所述漏极触点与所述源极之间。
10.根据权利要求9所述的HEMT，其中所述衬底包括蓝宝石、硅或碳化硅SiC。
11.根据权利要求9所述的HEMT，其中所述有源区包括台面。
12.根据权利要求9所述的HEMT，其中所述漏极触点延伸超过所述源极触点以进一步抑制电流拥挤效应。
13.根据权利要求9所述的HEMT，其中所述隔离区域的所述有源区包括经掺杂区域。
14.根据权利要求9所述的HEMT，其中所述HEMT为形成于所述衬底中且形成于所述衬底上的集成电路IC的一部分。
15.根据权利要求9所述的HEMT，其包括在所述衬底上的至少一个缓冲层，其中所述衬底包括硅，其中所述有源层包括未经掺杂GaN，且所述势垒层包括AlGaN。
16.根据权利要求9所述的HEMT，其中所述指尖为弯曲区域，且所述导电势垒在从所述源极到所述漏极触点指尖的路径中穿过至少150度弧阻挡导电。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Publication number Priority date Publication date Assignee Title
US9882041B1 (en) * 2016-11-17 2018-01-30 Texas Instruments Incorporated HEMT having conduction barrier between drain fingertip and source
US11791388B2 (en) * 2020-02-27 2023-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Source leakage current suppression by source surrounding gate structure
US11742390B2 (en) 2020-10-30 2023-08-29 Texas Instruments Incorporated Electronic device with gallium nitride transistors and method of making same
US11664431B2 (en) * 2021-01-08 2023-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Ring transistor structure

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313083A (en) * 1988-12-16 1994-05-17 Raytheon Company R.F. switching circuits
EP2339635A2 (en) * 2009-12-23 2011-06-29 Thales High electron mobility transistor
US20120280280A1 (en) * 2009-09-07 2012-11-08 Naiqian Zhang Semiconductor device and fabrication method thereof
US20130062625A1 (en) * 2011-09-08 2013-03-14 Kabushiki Kaisha Toshiba Semiconductor device
US20130299878A1 (en) * 2012-02-17 2013-11-14 International Rectifier Corporation Transistor Having Elevated Drain Finger Termination
CN105229792A (zh) * 2013-05-03 2016-01-06 德克萨斯仪器股份有限公司 Iii族氮化物晶体管布局
CN105264650A (zh) * 2013-06-13 2016-01-20 夏普株式会社 异质结场效应晶体管

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5105160B2 (ja) 2006-11-13 2012-12-19 クリー インコーポレイテッド トランジスタ
JP5776143B2 (ja) * 2010-07-06 2015-09-09 サンケン電気株式会社 半導体装置
JP2013182992A (ja) * 2012-03-01 2013-09-12 Toshiba Corp 半導体装置
US9337023B1 (en) 2014-12-15 2016-05-10 Texas Instruments Incorporated Buffer stack for group IIIA-N devices
JP6660631B2 (ja) * 2015-08-10 2020-03-11 ローム株式会社 窒化物半導体デバイス
US9882041B1 (en) * 2016-11-17 2018-01-30 Texas Instruments Incorporated HEMT having conduction barrier between drain fingertip and source

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5313083A (en) * 1988-12-16 1994-05-17 Raytheon Company R.F. switching circuits
US20120280280A1 (en) * 2009-09-07 2012-11-08 Naiqian Zhang Semiconductor device and fabrication method thereof
EP2339635A2 (en) * 2009-12-23 2011-06-29 Thales High electron mobility transistor
US20130062625A1 (en) * 2011-09-08 2013-03-14 Kabushiki Kaisha Toshiba Semiconductor device
US20130299878A1 (en) * 2012-02-17 2013-11-14 International Rectifier Corporation Transistor Having Elevated Drain Finger Termination
CN105229792A (zh) * 2013-05-03 2016-01-06 德克萨斯仪器股份有限公司 Iii族氮化物晶体管布局
CN105264650A (zh) * 2013-06-13 2016-01-20 夏普株式会社 异质结场效应晶体管

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113272970A (zh) * 2021-04-12 2021-08-17 英诺赛科(苏州)科技有限公司 半导体器件及其制造方法
CN113272970B (zh) * 2021-04-12 2022-06-14 英诺赛科(苏州)科技有限公司 半导体器件及其制造方法

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