CN109904222A - 薄膜晶体管及其制备方法、阵列基板、显示面板及装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示面板及装置 Download PDF

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CN109904222A
CN109904222A CN201910207115.0A CN201910207115A CN109904222A CN 109904222 A CN109904222 A CN 109904222A CN 201910207115 A CN201910207115 A CN 201910207115A CN 109904222 A CN109904222 A CN 109904222A
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tft
thin film
film transistor
lightly doped
electrode connecting
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郭志轩
王凤国
方业周
武新国
刘弘
李凯
田亮
张诗雨
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
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Priority to CN201910207115.0A priority Critical patent/CN109904222A/zh
Publication of CN109904222A publication Critical patent/CN109904222A/zh
Priority to US16/601,991 priority patent/US11342460B2/en
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Abstract

本发明涉及显示技术领域，公开一种薄膜晶体管及其制备方法、阵列基板、显示面板及装置。其中，薄膜晶体管，包括基板和位于所述基板上的有源层；所述有源层包括多晶硅层，所述有源层具有沟道区域和分别位于所述沟道区域两侧的两个电极连接区域；其中，所述沟道区域包括沿一个所述电极连接区域至另一个所述电极连接区域方向间隔设置的多段轻掺杂区、以及位于所述多段轻掺杂区之间的沟道。上述薄膜晶体管(Poly‑Si TFT)可以有效抑制漏电流的产生，产生的漏电流较小，良率较高。

Description

薄膜晶体管及其制备方法、阵列基板、显示面板及装置
技术领域
本发明涉及显示技术领域，特别涉及一种薄膜晶体管及其制备方法、阵列基板、显示面板及装置。
背景技术
低温多晶硅薄膜晶体管(LTPS TFT)，最大的缺点在于漏电流(Leakage Current)或称关态电流(Off-state Current)无法有效抑制，一般来说LTPS TFT漏电流为非晶硅的十至百倍，且约有17％的LTPS TFT良率下降来自于漏电流。并且，目前新产品的发展趋势为低功耗，这就要求更低的刷新频率和更小的漏电流；因此，如何有效的抑制漏电流的产生是LTPS TFT的重要研究方向之一。
发明内容
本发明公开了一种薄膜晶体管及其制备方法、阵列基板、显示面板及装置，目的是改善LTPS TFT的性能，提高良率。
为达到上述目的，本发明提供以下技术方案：
一种薄膜晶体管，包括基板和位于所述基板上的有源层；所述有源层包括多晶硅层，所述有源层具有沟道区域和分别位于所述沟道区域两侧的两个电极连接区域；其中，所述沟道区域包括沿一个所述电极连接区域至另一个所述电极连接区域方向间隔设置的多段轻掺杂区、以及位于所述多段轻掺杂区之间的沟道。
上述薄膜晶体管(Poly-Si TFT)中，由于在沟道区域内形成了多段轻掺杂区，等效在TFT开关内串联了多个电阻，从而可以使水平方向电场减小，进而降低电场加速引起的碰撞电离所产生的热载流子几率，因此可以一定程度上抑制漏电流的产生；并且，通过设置多段轻掺杂区，可以形成多段电势势垒，进而形成电势缓冲，以进一步减小由于电场加速引起的碰撞电离所产生的热载流子几率，进而，可以进一步抑制漏电流的产生；因此，综上所述，上述TFT的漏电流较小，良率较高。
可选的，所述两个电极连接区域为重掺杂区域。
可选的，所述沟道区域与所述两个电极连接区域相连的两端分别为两段所述轻掺杂区。
可选的，所述沟道区域中，两端的两段轻掺杂区的宽度大于中间的各段轻掺杂区的宽度。
可选的，所述中间的各段轻掺杂区的宽度相等。
可选的，所述沟道区域包括四段所述轻掺杂区。
可选的，各段所述沟道的宽度相等。
可选的，所述沟道区域中，所述轻掺杂区的宽度与所述沟道的宽度的比例小于1。
可选的，所述薄膜晶体管，还包括位于所述有源层上的栅极，所述栅极的两端边沿在基板上的正投影与所述沟道区域中连接两个电极连接区域的两端边沿在基板上的正投影分别对齐。
一种阵列基板，包括上述任一技术方案所述的薄膜晶体管。
一种显示面板，包括上述技术方案中所述的阵列基板。
一种显示装置，包括上述技术方案中所述的显示面板。
一种如上述任一技术方案所述的薄膜晶体管的制备方法，包括以下步骤：
在基板上制备多晶硅层，采用第一次构图工艺形成有源层的图形；
采用掩膜板对所述多晶硅层进行轻掺杂、以形成间隔设置的多段轻掺杂区。
可选的，所述形成间隔设置的多段轻掺杂区之后，还包括：
在所述多晶硅层上形成金属层，通过第二次构图工艺形成栅极的图形；所述栅极的两端边沿在基板上的正投影，与所述沟道区域中连接两个电极连接区域的两端边沿在基板上的正投影分别对齐；
采用栅极或者第二次构图工艺中留下的光刻胶作为掩膜，对所述多晶硅层进行重掺杂、以使所述两个电极连接区域变成重掺杂区域。
附图说明
图1为本发明实施例提供的一种薄膜晶体管的结构示意图；
图2为本发明实施例提供的一种薄膜晶体管在制备过程中形成多晶硅层后的结构示意图；
图3为本发明实施例提供的一种薄膜晶体管在多晶硅层上设置掩膜板后的结构示意图；
图4为本发明实施例提供的一种薄膜晶体管在多晶硅层中形成轻掺杂区后的结构示意图；
图5为本发明实施例提供的一种薄膜晶体管在多晶硅层上形成栅极后的结构示意图；
图6为本发明实施例提供的一种薄膜晶体管在多晶硅层中形成重掺杂区后的结构示意图；
图7为本发明实施例提供的一种薄膜晶体管在剥离了栅极上的PR胶后的结构示意图；
图8为本发明实施例提供的一种薄膜晶体管的制备方法流程图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
第一方面，如图1和图7所示，本发明实施例提供了一种薄膜晶体管(TFT)，该薄膜晶体管包括基板1和位于所述基板1上的有源层2；所述有源层2包括多晶硅层，具有沟道区域21和分别位于所述沟道区域21两侧的两个电极连接区域22；其中，所述沟道区域21包括沿一个所述电极连接区域22至另一个所述电极连接区域22方向间隔设置的多段轻掺杂区(LDD)211、以及位于多段轻掺杂区之间的沟道212。
上述薄膜晶体管(Poly-Si TFT)中，由于在沟道区域21内形成了多段LDD211，等效在TFT开关内串联了多个电阻，从而可以使水平方向电场减小，进而降低电场加速引起的碰撞电离所产生的热载流子几率，因此可以一定程度上抑制漏电流的产生；并且，通过设置为多段LDD211，可以形成多段电势势垒，进而形成电势缓冲，以进一步减小由于电场加速引起的碰撞电离所产生的热载流子几率，进而，可以进一步抑制漏电流的产生；因此，综上所述，上述TFT的漏电流较小，良率较高。
具体的，如图1所示，沟道区域21中，多段沟道212与多段轻掺杂区211交替设置，即，沟道区域21包络间隔设置的多段沟道212。
如图1和图7所示，一种具体的实施例中，所述两个电极连接区域22为重掺杂区域。
进一步的，所述沟道区域21与所述两个电极连接区域22相连的两端分别为两段所述轻掺杂区211；进而，从一个所述电极连接区域22至另一个所述电极连接区域22方向，有源层2中各区域依次为：重掺杂区-轻掺杂区211-沟道212-···轻掺杂区211···-沟道212-轻掺杂区211-重掺杂区；此时，沟道区域21两端的两段轻掺杂区211，可以分别作为两个重掺杂区与沟道212之间的过渡区。
示例性的，所述沟道区域21可以包括四段所述轻掺杂区211，此时，从一个所述电极连接区域22至另一个所述电极连接区域22方向，有源层2中各区域依次为：重掺杂区-轻掺杂区211-沟道212-轻掺杂区211-沟道212-轻掺杂区211-沟道212-轻掺杂区211-重掺杂区。
示例性的，所述沟道区域21中，两端的两段轻掺杂区211的宽度可以大于中间的各段轻掺杂区211的宽度，即作为过渡区的两段轻掺杂区211宽度较大，从而可以有效减小重掺杂与沟道212之间的电场，进而有效抑制漏电流的产生。具体的，本发明中所述的‘宽度’，均是指从一个所述电极连接区域22至另一个所述电极连接区域22方向的尺寸。
示例性的，所述沟道区域21中间的各段轻掺杂区211的宽度可以相等。进一步的，相邻轻掺杂区211之间的间隔可以一致，换句话说，即各段沟道212的宽度也相等。此时，可以形成多段势垒相等的电势差，进而产生的电势缓冲效果较好，从而对漏电流的抑制效果较好。
示例性的，所述沟道区域21中，轻掺杂区211的宽度与相邻轻掺杂区211之间的间隔宽度的比例小于1，换句话说，即轻掺杂区211宽度与沟道212宽度的比例小于1，亦或是，每段沟道212的宽度大于每段轻掺杂区211的宽度。
如图1和图7所示，一种具体的实施例中，本发明提供的TFT还可以包括位于所述有源层2上的栅极(Gate)3，所述栅极3的两端边沿在基板1上的正投影与所述沟道区域21的所述两端边沿在基板1上的正投影分别对齐。
此时，可以通过Gate3或者在Gate3在构图过程中保留的光刻胶(PR胶)作为保护沟道区域21的掩膜，进而可以直接对有源层2中的两个电极连接区域22进行重掺杂工艺。
进一步的，如图1所示，本发明提供的TFT还可以包括：位于基板1和有源层2之间的缓冲层4、位于有源层2和栅极3之间的栅极绝缘层(GI)5，以及，依次层叠于所述栅极3上的介电层(ILD)6和源漏电极(SD)7；具体的，所述介电层6中设有过孔61，所述源漏电极7通过所述过孔61分别与所述两个电极连接区域22电连接。
当然，本发明提供的TFT中，栅极3也可以设置在有源层2的下方、以形成底栅型TFT结构。
第二方面，本发明实施例还提供一种阵列基板，该阵列基板包括上述任一实施例中的薄膜晶体管。
第三方面，本发明实施例还提供一种显示面板，该显示面板包括上述实施例中的阵列基板，或者上述任一实施例中的薄膜晶体管。
具体的，该显示面板可以为电致发光显示面板(AMOLED)，也可以为液晶显示面板(LCD)。
第四方面，本发明实施例还提供一种显示装置，该显示装置包括上述实施例中的显示面板。
由于本发明提供的Poly-Si TFT，能够抑制漏电流产生、有效降低漏电流；从而，可以有效提高LTPS TFT的良率，进而提升阵列基板、显示面板和显示装置的良率；并且，由于TFT漏电流较小，因此，本发明提供的阵列基板、显示面板和显示装置，可以更好的适应目前新产品的低功耗发展趋势，具有较大的竞争优势。
第五方面，基于上述实施例中所述的薄膜晶体管，本发明实施例还提供一种薄膜晶体管的制备方法，如图8所示，该方法包括以下步骤：
步骤101，如图1所示，在基板1上制备多晶硅层20，采用第一次构图工艺形成有源层的图形；
步骤102，如图2和图3所示，采用掩膜板8对所述多晶硅层20进行轻掺杂、以形成间隔设置的多段轻掺杂区211。此时，随着多段轻掺杂区211的形成，多段沟道212也随之确定。
一种具体的实施例中，在步骤102之后，即形成间隔设置的多段轻掺杂区211之后；还可以包括以下步骤：
步骤103，如图4所示，在所述多晶硅层20上形成金属层，通过第二次构图工艺形成栅极3的图形；所述栅极3的两端边沿在基板1上的正投影，与所述沟道区域21中连接两个电极连接区域22的两端边沿在基板1上的正投影分别对齐；
步骤104，如图6所示，采用栅极3作为掩膜，对所述多晶硅层20进行重掺杂、以使所述两个电极连接区域22变为重掺杂区域；或者，如图5所示，也可以采用第二次构图工艺中保留下的PR胶9作为掩膜，对所述多晶硅层20进行重掺杂、以使所述两个电极连接区22域变为重掺杂区域，在重掺杂工艺之后再去除PR胶9。
示例性的，步骤101中，还可以包括对整个多晶硅层20进行一次掺杂处理的过程，以用于调整TFT的阈值电压(Vth)。
示例性的，本发明实施例提供的薄膜晶体管的制备方法，还可以包括以下步骤，如图1所示：
在步骤101之前，制备遮光层(LS)、缓冲层4；
在步骤102和步骤103之间，制备栅极绝缘层(GI)5；
在步骤104之后，制备介电层6和源漏电极(SD)7。
示例性的，当需要制备阵列基板时，在TFT阵列上，还可以依次制备平坦层(PLN)、公共电极(C-ITO)、绝缘层、像素电极(P-ITO)等结构。
本发明提供的Poly-Si TFT制备方法，通过一张轻掺杂掩膜板(LDD DopingMask)，在TFT的沟道区域内形成多个轻掺杂区，进而可以使制备完成的Poly-Si TFT，具有抑制漏电流产生的效果；从而，一方面，可以有效提高LTPS TFT的良率，进而提升阵列基板、显示面板、显示装置的良率；另一方面，可以更好的适应目前新产品的低功耗发展趋势，具有较大的竞争优势。
显然，本领域的技术人员可以对本发明实施例进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (14)

1.一种薄膜晶体管，其特征在于，包括基板和位于所述基板上的有源层；所述有源层包括多晶硅层，所述有源层具有沟道区域和分别位于所述沟道区域两侧的两个电极连接区域；其中，所述沟道区域包括沿一个所述电极连接区域至另一个所述电极连接区域方向间隔设置的多段轻掺杂区、以及位于所述多段轻掺杂区之间的沟道。
2.如权利要求1所述的薄膜晶体管，其特征在于，所述两个电极连接区域为重掺杂区域。
3.如权利要求2所述的薄膜晶体管，其特征在于，所述沟道区域与所述两个电极连接区域相连的两端分别为两段所述轻掺杂区。
4.如权利要求3所述的薄膜晶体管，其特征在于，所述沟道区域中，两端的两段轻掺杂区的宽度大于中间的各段轻掺杂区的宽度。
5.如权利要求4所述的薄膜晶体管，其特征在于，所述中间的各段轻掺杂区的宽度相等。
6.如权利要求3所述的薄膜晶体管，其特征在于，所述沟道区域包括四段所述轻掺杂区。
7.如权利要求1所述的薄膜晶体管，其特征在于，各段所述沟道的宽度相等。
8.如权利要求7所述的薄膜晶体管，其特征在于，所述沟道区域中，所述轻掺杂区的宽度与所述沟道的宽度的比例小于1。
9.如权利要求1-8任一项所述的薄膜晶体管，其特征在于，还包括位于所述有源层上的栅极，所述栅极的两端边沿在基板上的正投影与所述沟道区域中连接两个电极连接区域的两端边沿在基板上的正投影分别对齐。
10.一种阵列基板，其特征在于，包括权利要求1-9任一项所述的薄膜晶体管。
11.一种显示面板，其特征在于，包括权利要求10所述的阵列基板。
12.一种显示装置，其特征在于，包括权利要求11所述的显示面板。
13.一种如权利要求1-9任一项所述的薄膜晶体管的制备方法，其特征在于，包括以下步骤：
在基板上制备多晶硅层，采用第一次构图工艺形成有源层的图形；
采用掩膜板对所述多晶硅层进行轻掺杂、以形成间隔设置的多段轻掺杂区。
14.如权利要求13所述的制备方法，其特征在于，所述形成间隔设置的多段轻掺杂区之后，还包括：
在所述多晶硅层上形成金属层，通过第二次构图工艺形成栅极的图形；所述栅极的两端边沿在基板上的正投影，与所述沟道区域中连接两个电极连接区域的两端边沿在基板上的正投影分别对齐；
采用栅极或者第二次构图工艺中留下的光刻胶作为掩膜，对所述多晶硅层进行重掺杂、以使所述两个电极连接区域变成重掺杂区域。
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