CN109873063B - Light emitting diode epitaxial wafer and growth method thereof - Google Patents
Light emitting diode epitaxial wafer and growth method thereof Download PDFInfo
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- CN109873063B CN109873063B CN201910045276.4A CN201910045276A CN109873063B CN 109873063 B CN109873063 B CN 109873063B CN 201910045276 A CN201910045276 A CN 201910045276A CN 109873063 B CN109873063 B CN 109873063B
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Abstract
The invention discloses a light emitting diode epitaxial wafer and a growth method thereof, and belongs to the technical field of semiconductors. The epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the stress release layer, the active layer and the P-type semiconductor layer are sequentially stacked on the substrate; the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated; the first sublayer is made of gallium nitride doped with silicon and indium, the second sublayer is made of gallium nitride doped with silicon, and the third sublayer is made of gallium nitride doped with indium; in the same composite structure, the doping concentration of silicon in the second sublayer is smaller than that of silicon in the first sublayer, and the doping concentration of indium in the third sublayer is larger than that of indium in the first sublayer. The invention can improve the luminous efficiency of the LED.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light emitting diode epitaxial wafer and a growth method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor Diode that can convert electrical energy into Light energy. As a novel efficient, environment-friendly and green solid-state illumination light source, LEDs are being rapidly and widely applied in the fields of traffic signal lights, automobile interior and exterior lights, urban landscape lighting, mobile phone backlight sources and the like. The core component of the LED is a chip, and improving the light emitting efficiency of the chip is a goal continuously pursued in the application process of the LED.
The chip comprises an epitaxial wafer and an electrode arranged on the epitaxial wafer. The conventional LED epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate. The substrate is used for providing an epitaxial growth surface, the buffer layer is used for providing a nucleation center of epitaxial growth, the N-type semiconductor layer is used for providing electrons of composite luminescence, the P-type semiconductor layer is used for providing holes of the composite luminescence, and the active layer is used for carrying out the composite luminescence of the electrons and the holes.
Generally, the substrate is made of sapphire, the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are made of gallium nitride-based materials, a large lattice mismatch exists between the gallium nitride-based materials and the sapphire, and stress generated by the lattice mismatch extends into the active layer along the direction of epitaxial growth to influence the compound luminescence of electrons and holes. In order to relieve the stress caused by the lattice mismatch, a stress relieving layer is generally provided between the N-type semiconductor layer and the active layer. The stress release layer adopts a superlattice structure formed by alternately laminating a plurality of undoped indium gallium nitride (InGaN) layers and a plurality of undoped gallium nitride (GaN) layers.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
if the stress release layer is thin, the stress release effect is poor, and the stress generated by lattice mismatch can influence the compound luminescence of electrons and holes in the active layer, so that the luminous efficiency of the LED is reduced; if the stress release layer is thick, electron injection into the active layer provided by the N-type semiconductor layer may be affected, and the light emitting efficiency of the LED may also be reduced.
Disclosure of Invention
The embodiment of the invention provides a light-emitting diode epitaxial wafer and a growth method thereof, which can solve the problem that the light-emitting efficiency of an LED cannot be effectively improved by a stress release layer in the prior art. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides an led epitaxial wafer, where the led epitaxial wafer includes a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, an active layer, and a P-type semiconductor layer, where the buffer layer, the N-type semiconductor layer, the stress release layer, the active layer, and the P-type semiconductor layer are sequentially stacked on the substrate; the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated; the first sublayer is made of silicon-and-indium-doped gallium nitride, the second sublayer is made of silicon-doped gallium nitride, and the third sublayer is made of indium-doped gallium nitride; in the same composite structure, the doping concentration of silicon in the second sublayer is less than that of silicon in the first sublayer, and the doping concentration of indium in the third sublayer is greater than that of indium in the first sublayer.
Optionally, in the same composite structure, the doping concentration of silicon in the first sublayer is 2 to 5 times that of silicon in the second sublayer.
Furthermore, the N-type semiconductor layer is made of gallium nitride doped with silicon, and the doping concentration of the silicon in the first sub-layer is 1/200-1/20 of the doping concentration of the silicon in the N-type semiconductor layer.
Optionally, the doping concentration of silicon in the first sub-layer of the plurality of composite structures gradually decreases along the stacking direction of the plurality of composite structures, and the doping concentration of silicon in the second sub-layer of the plurality of composite structures gradually decreases along the stacking direction of the plurality of composite structures.
Further, in two adjacent composite structures, the doping concentration of silicon in the first sublayer of the composite structure stacked first is 2-3 times that of silicon in the first sublayer of the composite structure stacked later, and the doping concentration of silicon in the second sublayer of the composite structure stacked first is 2-3 times that of silicon in the second sublayer of the composite structure stacked later.
Optionally, in the same composite structure, the doping concentration of indium in the third sub-layer is 2 to 6 times that of indium in the first sub-layer.
Further, the active layer comprises a plurality of quantum wells and a plurality of quantum barriers which are alternately stacked, the material of the quantum wells adopts gallium nitride doped with indium, and the doping concentration of the indium in the third sub-layer is 1/5-1/2 of the doping concentration of the indium in the quantum wells.
Optionally, in the same composite structure, the thickness of the first sub-layer is greater than the thickness of the third sub-layer, and the thickness of the third sub-layer is greater than the thickness of the second sub-layer.
In another aspect, an embodiment of the present invention provides a growth method of a light emitting diode epitaxial wafer, where the growth method includes:
providing a substrate;
sequentially growing a buffer layer, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer on the substrate;
the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated; the first sublayer is made of silicon-and-indium-doped gallium nitride, the second sublayer is made of silicon-doped gallium nitride, and the third sublayer is made of indium-doped gallium nitride; in the same composite structure, the doping concentration of silicon in the second sublayer is less than that of silicon in the first sublayer, and the doping concentration of indium in the third sublayer is greater than that of indium in the first sublayer.
Optionally, the growth temperature of the stress release layer is lower than that of the N-type semiconductor layer, and the growth temperature of the stress release layer is higher than that of the active layer.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
the stress release layer is formed by adopting a plurality of composite structures consisting of the first sublayer, the second sublayer and the third sublayer, and the stress release layer is of a superlattice structure and can play a role in releasing stress. The material of the first sub-layer is gallium nitride doped with silicon and indium, the material of the second sub-layer is gallium nitride doped with silicon, the material of the third sub-layer is gallium nitride doped with indium, and a carrier transport channel can be formed in the first sub-layer and the second sub-layer to promote electrons provided by the N-type semiconductor layer to be injected into the active layer; in the same composite structure, the doping concentration of silicon in the second sublayer is higher than that of silicon in the first sublayer, the overall doping concentration of silicon is from many to few, the silicon is more matched with lattices of the N-type semiconductor layer and the active layer, and the influence of stress on the active layer is reduced; in addition, in the same composite structure, the doping concentration of indium in the third sub-layer is greater than that of indium in the first sub-layer, so that the third sub-layer is better in lattice matching with the active layer, the lattice matching in the stress release layer can be adjusted, the stress extending to the active layer is reduced as far as possible, and the luminous efficiency of the LED is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a stress relieving layer provided in an embodiment of the present invention;
fig. 3 is a flowchart of a method for growing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides a light-emitting diode epitaxial wafer. Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention. Referring to fig. 1, the light emitting diode epitaxial wafer includes a substrate 1, a buffer layer 2, an N-type semiconductor layer 3, a stress relief layer 4, an active layer 5, and a P-type semiconductor layer 6, and the buffer layer 2, the N-type semiconductor layer 3, the stress relief layer 4, the active layer 5, and the P-type semiconductor layer 6 are sequentially stacked on the substrate 1.
Fig. 2 is a schematic structural diagram of a stress release layer according to an embodiment of the present invention. Referring to fig. 2, in the present embodiment, the stress relieving layer 4 includes a plurality of composite structures 40 sequentially laminated, each including a first sublayer 41, a second sublayer 42, and a third sublayer 43 sequentially laminated. The material of the first sub-layer 41 is silicon and indium-doped gallium nitride, the material of the second sub-layer 42 is silicon-doped gallium nitride, and the material of the third sub-layer 43 is indium-doped gallium nitride. In the same composite structure 40, the doping concentration of silicon in the second sub-layer 42 is less than that of silicon in the first sub-layer 41, and the doping concentration of indium in the third sub-layer 43 is greater than that of indium in the first sub-layer 41.
According to the embodiment of the invention, the stress release layer is formed by adopting a plurality of composite structures consisting of the first sublayer, the second sublayer and the third sublayer, the stress release layer is of a superlattice structure, so that the stress release layer can play a role in releasing stress, and compared with a single composite structure, the stress release effect is particularly obvious. The material of the first sub-layer is gallium nitride doped with silicon and indium, the material of the second sub-layer is gallium nitride doped with silicon, the material of the third sub-layer is gallium nitride doped with indium, and a carrier transport channel can be formed in the first sub-layer and the second sub-layer to promote electrons provided by the N-type semiconductor layer to be injected into the active layer; in the same composite structure, the doping concentration of silicon in the second sublayer is higher than that of silicon in the first sublayer, the overall doping concentration of silicon is from many to few, the silicon is more matched with lattices of the N-type semiconductor layer and the active layer, and the influence of stress on the active layer is reduced; in addition, in the same composite structure, the doping concentration of indium in the third sub-layer is greater than that of indium in the first sub-layer, so that the third sub-layer is better in lattice matching with the active layer, the lattice matching in the stress release layer can be adjusted, the stress extending to the active layer is reduced as far as possible, and the luminous efficiency of the LED is effectively improved.
Optionally, in the same composite structure 40, the doping concentration of silicon in the first sub-layer 41 may be 2 times to 5 times that of silicon in the second sub-layer 42, so that adverse effects on the epitaxial wafer crystal quality are avoided as much as possible under the condition that a carrier transport channel is formed to effectively promote current spreading.
Further, the material of the N-type semiconductor layer may adopt silicon-doped gallium nitride; the doping concentration of silicon in the first sub-layer 41 can be 1/200-1/20 of the doping concentration of silicon in the N-type semiconductor layer 3, and matching of the N-type semiconductor layer and the active layer is facilitated.
Exemplarily, the doping concentration of silicon in the first sub-layer 41 may be 5 × 1017/cm3～5*1018/cm3The doping concentration of silicon in the second sub-layer 42 may be 1 x 1017/cm3～6*1017/cm3The doping concentration of silicon in the N-type semiconductor layer 3 may be 1 x 1019/cm3～1*1020/cm3。
Further, the doping concentration of silicon in the first sub-layer 41 may be 6 × 1017/cm3～4*1018/cm3E.g. 1 x 1018/cm3(ii) a The doping concentration of silicon in the second sub-layer 42 may be 1 x 1017/cm3～6*1017/cm3E.g. 3 x 1017/cm3。
Alternatively, the doping concentration of silicon in the first sub-layer 41 of the plurality of composite structures 40 may gradually decrease along the stacking direction of the plurality of composite structures 40, and the doping concentration of silicon in the second sub-layer 42 of the plurality of composite structures 40 may gradually decrease along the stacking direction of the plurality of composite structures 40, which is beneficial for matching the N-type semiconductor layer and the active layer.
Further, in two adjacent composite structures 40, the doping concentration of silicon in the first sublayer 41 of the composite structure 40 stacked first may be 2 times to 3 times that of silicon in the first sublayer 41 of the composite structure 40 stacked later, and the doping concentration of silicon in the second sublayer 42 of the composite structure 40 stacked first may be 2 times to 3 times that of silicon in the second sublayer 42 of the composite structure 40 stacked later, so that the implementation effect is good.
Optionally, in the same composite structure 40, the doping concentration of indium in the third sub-layer 43 may be 2 to 6 times that of indium in the first sub-layer 41, which not only can give consideration to lattice matching in the epitaxial wafer, but also can avoid polarization effect enhancement.
Illustratively, in the same composite structure 40, the doping concentration of indium in the third sub-layer 43 may be 2 times to 5 times that of indium in the first sub-layer 41, so that the implementation effect is good.
Further, the active layer 50 may include a plurality of quantum wells and a plurality of quantum barriers alternately stacked, and the material of the quantum wells may be indium-doped gallium nitride; the doping concentration of indium in the third sub-layer 43 can be 1/5-1/3 of the doping concentration of indium in the quantum well, so that lattice matching of the stress release layer and the active layer is promoted, and the integrity of the lattice of the stress release layer can be guaranteed.
Illustratively, the doping concentration of indium in the third sub-layer 43 can be 1/5-1/2 of the doping concentration of indium in the quantum well, and the implementation effect is good.
For example, the doping concentration of indium in the first sub-layer 41 may be 4 × 1018/cm3～1*1019/cm3The doping concentration of indium in the third sub-layer 43 may be 1 x 1019/cm3～8*1019/cm3The doping concentration of indium in the quantum well can be 2 x 1019/cm3～5*1020/cm3。
Further, the doping concentration of indium in the first sub-layer 41 may be 4 × 1018/cm3～1*1019/cm3E.g. 7 x 1018/cm3(ii) a The doping concentration of indium in the third sub-layer 43 may be 1 x 1019/cm3～8*1019/cm3E.g. 4 x 1019/cm3。
Alternatively, the doping concentration of indium in the first sub-layer 41 of the plurality of composite structures 40 may gradually increase along the stacking direction of the plurality of composite structures 40, and the doping concentration of indium in the third sub-layer 43 of the plurality of composite structures 40 may gradually increase along the stacking direction of the plurality of composite structures 40, which is beneficial for lattice matching in the epitaxial wafer.
Further, in two adjacent composite structures 40, the doping concentration of indium in the first sub-layer 41 of the composite structure 40 stacked later may be 1.1 to 1.2 times that of indium in the first sub-layer 41 of the composite structure 40 stacked earlier, and the doping concentration of indium in the third sub-layer 43 of the composite structure 40 stacked later may be 1.1 to 1.2 times that of indium in the third sub-layer 43 of the composite structure 40 stacked earlier, so that the effect is good.
Alternatively, in the same composite structure 40, the thickness of the first sub-layer 41 may be greater than the thickness of the third sub-layer 43, and the thickness of the third sub-layer 43 may be greater than the thickness of the second sub-layer 42. On one hand, the effect of releasing stress and expanding current can be effectively achieved, on the other hand, the internal lattice matching is better, and the negative influence can be avoided.
Further, the thickness of the first sub-layer 41 may be 2 to 15 times that of the third sub-layer 43, and the thickness of the third sub-layer 43 may be 2 to 16 times that of the second sub-layer 42, which is not only beneficial to stress release and current spreading, but also can ensure crystal quality and avoid polarization effect enhancement.
Illustratively, the thickness of the first sub-layer 41 may be 3 to 12 times the thickness of the third sub-layer 43, and the thickness of the third sub-layer 43 may be 2 to 12 times the thickness of the second sub-layer 42, which is good for implementation.
Illustratively, the thickness of the first sub-layer 41 may be 15nm to 30nm, the thickness of the second sub-layer 42 may be 2nm to 8nm, and the thickness of the third sub-layer 43 may be 0.5nm to 4 nm.
Further, the thickness of the first sub-layer 41 may be 15nm to 25nm, such as 20 nm; the thickness of the second sub-layer 42 may be 2nm to 6nm, such as 4 nm; the thickness of the third sub-layer 43 may be in the range of 0.5nm to 2nm, such as 1 nm.
Alternatively, the number of the plurality of composite structures 40 may be 3 to 20, which can not only effectively release the stress generated and extended by the lattice mismatch by using the superlattice structure, but also avoid the growth time being too long to reduce the crystal quality of the epitaxial wafer.
Illustratively, the number of the plurality of composite structures 40 may be 3 to 15, such as 9, which is effective in achieving a stable stress relief effect and a stable crystal quality.
In practical applications, the stress release layer 4 may further include a first cladding layer disposed between the N-type semiconductor layer and the plurality of composite structures, and a second cladding layer disposed between the plurality of composite structures and the active layer; the first cladding layer and the second cladding layer are made of silicon-doped gallium nitride, and the doping concentration of silicon in the first cladding layer and the second cladding layer is the same as that of silicon in the second sub-layer, so that electrons can be injected into the active layer. Furthermore, the thicknesses of the first cladding layer and the second cladding layer are the same as the thickness of the second sublayer, and the thicknesses are thinner, so that adverse effects on the crystal quality are avoided.
Alternatively, the material of the substrate 1 may be sapphire (alumina is a main material), such as sapphire having a crystal orientation of [0001 ]. The buffer layer 2 may be made of undoped gallium nitride or aluminum nitride. The material of the quantum barrier can adopt gallium nitride. The P-type semiconductor layer 6 may be made of P-type doped (e.g., mg) gan.
Further, the thickness of the buffer layer 2 may be 15nm to 30nm, preferably 25 nm. The thickness of the N-type semiconductor layer 3 may be 2 μm to 3 μm, and preferably 2.5 μm. The thickness of the quantum well can be 2 nm-3 nm, preferably 2.5 nm; the thickness of the quantum barrier can be 8nm to 11nm, preferably 9.5 nm; the number of the quantum wells is the same as that of the quantum barriers, and the number of the quantum barriers can be 11-13, preferably 12; the thickness of the active layer 5 may be 130nm to 160nm, preferably 145 nm. The thickness of the P-type semiconductor layer 6 may be 50nm to 80nm, preferably 65 nm. The doping concentration of the P-type dopant in the P-type semiconductor layer 6 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an undoped gallium nitride layer 7, where the undoped gallium nitride layer 7 is disposed between the buffer layer 2 and the N-type semiconductor layer 3 to relieve stress and defects caused by lattice mismatch between the substrate material and the gallium nitride, and provide a growth surface with good crystal quality for the epitaxial wafer main body structure.
In a specific implementation, buffer layer 2 is a thin layer of gallium nitride that is first grown at low temperature on a patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer 7 in this embodiment.
Further, the thickness of the undoped gallium nitride layer 7 may be 2 μm to 3.5 μm, preferably 2.75 μm.
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include an electron blocking layer 81, and the electron blocking layer 81 is disposed between the active layer 5 and the P-type semiconductor layer 6 to prevent electrons from jumping into the P-type semiconductor layer to combine with holes in a non-radiative manner, thereby reducing the light emitting efficiency of the LED.
Specifically, the electron blocking layer 81 may be made of P-type doped aluminum gallium nitride (AlGaN) such as AlyGa1-yN，0.15＜y＜0.25。
Further, the thickness of the electron blocking layer 81 may be 30nm to 50nm, preferably 40 nm.
Preferably, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a low temperature P-type layer 82, and the low temperature P-type layer 82 is disposed between the active layer 4 and the electron blocking layer 81, so as to prevent indium atoms in the active layer from being precipitated due to a high growth temperature of the electron blocking layer, which affects the light emitting efficiency of the light emitting diode.
Specifically, the material of the low-temperature P-type layer 82 may be the same as that of the P-type semiconductor layer 6. In the present embodiment, the material of the low temperature P-type layer 82 may be P-type doped gan.
Further, the thickness of the low-temperature P-type layer 82 may be 10nm to 50nm, preferably 30 nm; the doping concentration of the P-type dopant in the low temperature P-type layer 82 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the light emitting diode epitaxial wafer may further include a contact layer 9, and the contact layer 9 is disposed on the P-type semiconductor layer 6 to form an ohmic contact with an electrode or a transparent conductive film formed in a chip manufacturing process.
Specifically, the contact layer 9 may be made of P-type doped indium gallium nitride or gallium nitride.
Further, the thickness of the contact layer 9 may be 5nm to 300nm, preferably 100 nm; the doping concentration of the P-type dopant in the contact layer 9 may be 1021/cm3～1022/cm3Preferably 5 x 1021/cm3。
The embodiment of the invention provides a method for growing a light-emitting diode epitaxial wafer, which is suitable for growing the light-emitting diode epitaxial wafer shown in figure 1. Fig. 3 is a flowchart of a method for growing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention. Referring to fig. 3, the growing method includes:
step 201: a substrate is provided.
Optionally, the step 201 may include:
the substrate is annealed at a temperature of 1000 to 1100 deg.C (preferably 1050 deg.C) and a pressure of 200to 500torr (preferably 350torr) in a hydrogen atmosphere for 5 to 6 minutes (preferably 5.5 minutes).
The surface of the substrate is cleaned through the steps, impurities are prevented from being doped into the epitaxial wafer, and the growth quality of the epitaxial wafer is improved.
Step 202: a buffer layer, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
In this embodiment, the stress release layer includes a plurality of composite structures stacked in sequence, and each composite structure includes a first sublayer, a second sublayer, and a third sublayer stacked in sequence. The first sublayer is made of silicon and indium-doped gallium nitride, the second sublayer is made of silicon-doped gallium nitride, and the third sublayer is made of indium-doped gallium nitride. In the same composite structure, the doping concentration of silicon in the second sublayer is smaller than that of silicon in the first sublayer, and the doping concentration of indium in the third sublayer is larger than that of indium in the first sublayer.
Alternatively, the growth temperature of the stress relieving layer may be lower than that of the N-type semiconductor layer, and the growth temperature of the stress relieving layer may be higher than that of the active layer. The growth temperature of the stress release layer is between the growth temperature of the N-type semiconductor layer and the growth temperature of the active layer, so that the stress caused by the high-temperature growth of the N-type semiconductor layer can be effectively released, the stress extending to the active layer is reduced, the luminous efficiency of the LED is improved, and the damage of the high-temperature growth to the active layer can be avoided.
Furthermore, the growth temperature of the stress release layer can be 150-300 ℃ lower than that of the N-type semiconductor layer, so that on one hand, the damage to the active layer caused by higher growth temperature is avoided, and on the other hand, the influence on the crystal quality of the epitaxial wafer caused by lower growth temperature is avoided.
Illustratively, the growth temperature of the stress release layer can be 200-300 ℃ lower than that of the N-type semiconductor layer, such as 250 ℃, so that the effect is good, and the crystal quality of the stress release layer and the crystal quality of the active layer can be ensured at the same time.
Illustratively, the growth temperature of the stress relieving layer may be 700 ℃ to 950 ℃.
Further, the growth temperature of the stress release layer may be 800 ℃ to 900 ℃, such as 850 ℃.
Optionally, this step 202 may include:
firstly, controlling the temperature to be 530-560 ℃ (preferably 545 ℃) and the pressure to be 200-500 torr (preferably 350torr), and growing a buffer layer on a substrate;
secondly, controlling the temperature to be 1000-1100 ℃ (preferably 1050 ℃), and the pressure to be 100-500 torr (preferably 300torr), and growing an N-type semiconductor layer on the buffer layer;
thirdly, controlling the temperature to be 700-950 ℃ (preferably 800 ℃) and the pressure to be 100-500 torr (preferably 300torr), and growing a stress release layer on the N-type semiconductor layer;
fourthly, growing an active layer on the stress release layer; wherein, the growth temperature of the quantum well is 760 ℃ to 780 ℃ (preferably 770 ℃), and the pressure is 200 torr; the growth temperature of the quantum barrier is 860 ℃ -890 ℃ (preferably 875 ℃), and the pressure is 200 torr;
and fifthly, controlling the temperature to be 940-980 ℃ (preferably 960 ℃) and the pressure to be 200-600 torr (preferably 400torr), and growing the P-type semiconductor layer on the active layer.
Optionally, before the third step, the growing method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
Specifically, growing an undoped gallium nitride layer on the buffer layer may include:
an undoped gallium nitride layer is grown on the buffer layer at a temperature of 1000 ℃ to 1100 ℃ (preferably 1050 ℃) and a pressure of 200torr to 600torr (preferably 400 torr).
Optionally, before the fifth step, the growing method may further include:
an electron blocking layer is grown on the active layer.
Accordingly, a P-type semiconductor layer is grown on the electron blocking layer.
Specifically, growing an electron blocking layer on the active layer may include:
the electron blocking layer is grown on the active layer at a controlled temperature of 930 deg.C to 970 deg.C (preferably 950 deg.C) and a pressure of 100 torr.
Preferably, before growing the electron blocking layer on the active layer, the growth method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Specifically, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 600 ℃ to 850 ℃ (preferably 750 ℃) and the pressure is controlled to be 100torr to 600torr (preferably 300torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after the fifth step, the growing method may further include:
and growing a contact layer on the P-type semiconductor layer.
Specifically, growing a contact layer on the P-type semiconductor layer may include:
the contact layer is grown on the P-type semiconductor layer at a temperature of 850 to 1050 deg.C (preferably 950 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
After the completion of the epitaxial growth, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.
The control of the temperature and the pressure both refer to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically refer to the reaction chamber of a Metal-organic Chemical Vapor Deposition (MOCVD) device, such as Veeco K465i MOCVD or Veeco C4 MOCVD. During implementation, hydrogen or nitrogen or a mixed gas of hydrogen and nitrogen is used as a carrier gas, trimethyl gallium or triethyl gallium is used as a gallium source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, silane is used as a silicon source, and magnesium diclocide is used as a magnesium source.
Various samples of the light emitting diode epitaxial wafer are formed by changing individual parameters of the stress release layer (such as the doping concentration of silicon in the first sub-layer and the second sub-layer), ensuring other parameters of the stress release layer (such as the doping concentration of indium in the first sub-layer and the third sub-layer, the thicknesses of the first sub-layer, the second sub-layer and the third sub-layer, the number of composite structures and the like), and all parameters of other layers (such as the thickness of a buffer layer, the thickness of an N-type semiconductor layer, the doping concentration of silicon in the N-type semiconductor layer and the like). The samples and the light emitting diode epitaxial wafer adopting the existing stress release layer are manufactured into chips for testing, and the test results are shown in the following table:
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The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (9)
1. The light-emitting diode epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the stress release layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate; the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated; the first sublayer is made of silicon-and-indium-doped gallium nitride, the second sublayer is made of silicon-doped gallium nitride, and the third sublayer is made of indium-doped gallium nitride; in the same composite structure, the doping concentration of silicon in the second sublayer is less than that of silicon in the first sublayer, and the doping concentration of indium in the third sublayer is greater than that of indium in the first sublayer; in the same composite structure, the thickness of the first sublayer is greater than that of the third sublayer, and the thickness of the third sublayer is greater than that of the second sublayer.
2. The light-emitting diode epitaxial wafer according to claim 1, wherein in the same composite structure, the doping concentration of silicon in the first sub-layer is 2 times to 5 times that of silicon in the second sub-layer.
3. The light-emitting diode epitaxial wafer as claimed in claim 2, wherein the material of the N-type semiconductor layer is GaN doped with silicon, and the doping concentration of the silicon in the first sub-layer is 1/200-1/20 of the doping concentration of the silicon in the N-type semiconductor layer.
4. The light-emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein the doping concentration of silicon in the first sub-layer of the plurality of composite structures is gradually reduced along the stacking direction of the plurality of composite structures, and the doping concentration of silicon in the second sub-layer of the plurality of composite structures is gradually reduced along the stacking direction of the plurality of composite structures.
5. The light-emitting diode epitaxial wafer according to claim 4, wherein in two adjacent composite structures, the doping concentration of silicon in the first sub-layer of the composite structure stacked first is 2-3 times that of silicon in the first sub-layer of the composite structure stacked later, and the doping concentration of silicon in the second sub-layer of the composite structure stacked first is 2-3 times that of silicon in the second sub-layer of the composite structure stacked later.
6. The light-emitting diode epitaxial wafer according to any one of claims 1 to 3, wherein in the same composite structure, the doping concentration of indium in the third sub-layer is 2 times to 6 times that of indium in the first sub-layer.
7. The light-emitting diode epitaxial wafer as claimed in claim 6, wherein the active layer comprises a plurality of quantum wells and a plurality of quantum barriers which are alternately stacked, the material of the quantum wells adopts gallium nitride doped with indium, and the doping concentration of indium in the third sub-layer is 1/5-1/2 of the doping concentration of indium in the quantum wells.
8. A growth method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
sequentially growing a buffer layer, an N-type semiconductor layer, a stress release layer, an active layer and a P-type semiconductor layer on the substrate;
the stress release layer comprises a plurality of composite structures which are sequentially laminated, and each composite structure comprises a first sublayer, a second sublayer and a third sublayer which are sequentially laminated; the first sublayer is made of silicon-and-indium-doped gallium nitride, the second sublayer is made of silicon-doped gallium nitride, and the third sublayer is made of indium-doped gallium nitride; in the same composite structure, the doping concentration of silicon in the second sublayer is less than that of silicon in the first sublayer, and the doping concentration of indium in the third sublayer is greater than that of indium in the first sublayer; in the same composite structure, the thickness of the first sublayer is greater than that of the third sublayer, and the thickness of the third sublayer is greater than that of the second sublayer.
9. The growth method according to claim 8, wherein the growth temperature of the stress relieving layer is lower than that of the N-type semiconductor layer, and the growth temperature of the stress relieving layer is higher than that of the active layer.
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| CN103346223A (en) * | 2013-06-06 | 2013-10-09 | 华灿光电股份有限公司 | Epitaxial wafer of light emitting diode |
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