CN109860117A - 用于减小晶体管间隔的切割金属栅极工艺 - Google Patents
用于减小晶体管间隔的切割金属栅极工艺 Download PDFInfo
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- CN109860117A CN109860117A CN201810385047.2A CN201810385047A CN109860117A CN 109860117 A CN109860117 A CN 109860117A CN 201810385047 A CN201810385047 A CN 201810385047A CN 109860117 A CN109860117 A CN 109860117A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
- H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
该方法包括提供具有衬底以及第一鳍和第二鳍的结构,第一鳍和第二鳍位于衬底上方并且通常沿着第一方向纵向定向;在第一鳍和第二鳍上方外延生长半导体源极/漏极(S/D)部件,其中,位于第一鳍上方的第一半导体S/D部件与位于第二鳍上方的第二半导体S/D部件合并;以及对第一鳍和第二鳍之间的区实施第一蚀刻工艺,其中,第一蚀刻工艺将第一半导体S/D部件和第二半导体S/D部件分隔开。本发明的实施例还涉及用于减小晶体管间隔的切割金属栅极工艺。
Description
技术领域
本发明的实施例涉及用于减小晶体管间隔的切割金属栅极工艺。
背景技术
半导体集成电路(IC)工业已经经历了指数增长。IC材料和设计中的技术进步已经产生了多代IC,其中,每一代都比上一代具有更小和更复杂的电路。在IC演化过程中,功能密度(即,每芯片面积的互连器件的数量)已经普遍增大,而几何尺寸(即,可以使用制造工艺产生的最小组件(或线))已经减小。这种按比例缩小工艺通常通过提高生产效率和降低相关成本来提供益处。这种按比例缩小已经增加了处理和制造IC的复杂性。
例如,当设计和制造具有上拉(PU)器件、下拉(PD)器件和传输门(PG)器件的SRAM(静态随机存取存储器)单元时,通常在一个器件区域中(例如,在n阱中)形成PU器件(例如,PMOS),并且在另一器件区域中(例如,在p阱中)形成PD和PG器件。然而,至少对于PU器件,存在它们之间的间隔需要足够大,使得PU器件的外延源极/漏极(S/D)部件不会合并而导致短路缺陷的担心。一方面,为了减小S/D接触电阻,通常期望具有较大的外延S/D部件。另一方面,具有较大的外延S/D部件也增加了PU器件之间的间隔要求,从而不期望地减小了器件集成度。本发明的目的是寻求解决这个问题等。
发明内容
本发明的实施例提供了一种制造半导体结构的方法,包括:提供具有衬底以及第一鳍和第二鳍的结构,所述第一鳍和所述第二鳍位于所述衬底上方并且沿着第一方向纵向定向;在所述第一鳍和所述第二鳍上方外延生长半导体源极/漏极(S/D)部件,其中,位于所述第一鳍上方的第一半导体源极/漏极部件与位于所述第二鳍上方的第二半导体源极/漏极部件合并;以及对所述第一鳍和所述第二鳍之间的区实施第一蚀刻工艺,其中,所述第一蚀刻工艺将所述第一半导体源极/漏极部件和所述第二半导体源极/漏极部件分隔开。
本发明的另一实施例提供了一种制造半导体结构的方法,包括:提供结构,所述结构具有:衬底;第一鳍、第二鳍和第三鳍,位于所述衬底上方并且沿着第一方向纵向定向;栅极结构,位于所述第一鳍、所述第二鳍和所述第三鳍上方并且沿着垂直于所述第一方向的第二方向纵向定向;第一外延半导体源极/漏极(S/D)部件和第二外延半导体源极/漏极(S/D)部件,分别位于所述第一鳍和所述第二鳍上方,其中,所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件沿着所述第二方向合并;和第一介电层,位于所述衬底、所述第一鳍、所述第二鳍和所述第三鳍以及所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件上方,并且填充所述栅极结构之间的间隔;对所述第一鳍和所述第二鳍之间的第一区以及所述第二鳍和所述第三鳍之间的第二区实施第一蚀刻工艺,其中,所述第一蚀刻工艺调整为选择性地蚀刻所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件以及所述第一介电层,而不蚀刻所述栅极结构;以及对所述第二区实施第二蚀刻工艺,其中,所述第二蚀刻工艺调整为选择性地蚀刻所述栅极结构。
本发明的又一实施例提供了一种半导体结构,包括:衬底;第一鳍和第二鳍,位于所述衬底上方并且沿着第一方向纵向定向;第一外延半导体源极/漏极(S/D)部件和第二外延半导体源极/漏极(S/D)部件,分别位于所述第一鳍和所述第二鳍上方;以及第一介电层,设置在所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件之间并且与所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件物理接触,在所述第一介电层和所述第一外延半导体源极/漏极部件之间产生第一界面,并且在所述第一介电层和所述第二外延半导体源极/漏极部件之间产生第二界面,其中,所述第一界面和所述第二界面从顶部至底部朝向彼此倾斜。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该强调,根据工业中的标准实践,各个部件未按比例绘制并且仅用于说明的目的。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1A示出了根据本发明的方面的用切割金属栅极工艺实现的半导体结构的俯视图。
图1B、图1C和图1D示出了根据一些实施例的图1A中的结构的截面图。
图2A、图2B和图2C示出了根据本发明的方面的用于形成图1A至图1D所示的结构的方法的流程图。
图3A、图3B、图4A、图4B、图5A、图5B、图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10、图11、图12A、图12B、图13、图14A、图14B、图15、图16、图17和图18示出了根据一些实施例的根据图2A至图2C的方法的制造工艺期间的半导体结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
本发明通常涉及半导体器件和制造方法,并且更具体地,涉及使用切割金属栅极工艺制造FinFET半导体器件,切割金属栅极工艺有利地减少了邻近鳍(诸如用于形成p型FinFET的鳍)之间的间隔要求。切割金属栅极(CMG)工艺是指在金属栅极(例如,高k金属栅极或HK MG)替换伪栅极结构(例如,多晶硅栅极)之后,切割金属栅极(例如,通过蚀刻工艺)以将金属栅极分成两个或更多部分的制造工艺。每部分均用作单个晶体管的金属栅极。随后将隔离材料填充至金属栅极的邻近部分之间的沟槽。在本发明中,这些沟槽称为切割金属栅极沟槽或CMG沟槽。根据本发明,CMG工艺包括两个曝光步骤和两个蚀刻步骤(所谓的2P2E)。第一曝光步骤和第一蚀刻步骤设计为用于蚀刻介电层以及需要分隔开的那些合并的外延S/D部件,而不蚀刻金属栅极。第二曝光步骤和第二蚀刻步骤设计为用于蚀刻金属栅极。通过利用这种2P2E工艺,与传统器件相比,半导体鳍可以更靠近布置,并且外延S/D部件可以生长地更大。这同时具有两个目的:通过减小半导体鳍之间的间隔来增加器件集成度,以及生长较大的外延S/D部件以用于减小S/D接触电阻。
图1A示出了半导体器件(或半导体结构)100的俯视图。图1B示出了沿着图1A的B-B线的器件100的截面图。图1C示出了沿着图1A的C-C线的器件100的截面图。图1D示出了沿着图1A的D-D线的器件100的截面图。
参照图1A至图1B,器件100包括衬底102、突出于衬底102的多个鳍104(包括第一器件区域103a中的鳍104a、第二器件区域103b中的鳍104b)、位于衬底102上方和鳍104之间的隔离结构106以及设置在鳍104和隔离结构106上方的多个栅极结构112。
鳍104沿着X方向纵向定向并且沿着垂直于X方向的Y方向彼此间隔开。在本实施例中,鳍104a设计为用于形成p型FinFET;并且鳍104b设计为用于形成n型FinFET。鳍104a沿着Y方向具有边缘至边缘的间隔P1。在实施例中,P1在从20至30nm的范围,这比单独形成(未合并)的邻近的外延S/D部件的传统鳍配置更小。在具体实施例中,P1设计为比光刻曝光工具的分辨率大几纳米,诸如在实施例中分辨率为约13.3nm的极紫外(EUV)曝光工具。较小的间隔P1有利地增加了器件集成度。鳍104b的一些彼此靠近放置,以形成用于提高器件性能的多鳍晶体管。在图1A所示的实施例中,存在两组双鳍104b。在实施例中,鳍104a和附近的鳍104b之间的间隔为P2,P2在从40至50nm的范围。在实施例中,两组鳍104b之间的间隔为P3,P3在从40至50nm的范围。在各个实施例中,一组鳍104b可以包括用于形成多鳍晶体管的两个(如图所示)、三个或多个鳍。
栅极结构112沿着Y方向纵向定向并且沿着X方向彼此间隔开。栅极结构112在其相应的沟道区域中接合鳍104a和104b,从而形成FinFET。在本实施例中,栅极结构112接合鳍104a以形成p型FinFET,其可用于SRAM单元中的上拉(PU)器件;并且栅极结构112接合鳍104b以形成n型FinFET,其可以用于SRAM单元中的下拉(PD)器件或传输门(PG)器件。由于间隔P1减小,配置为具有本发明的PU、PD和PG器件的SRAM单元具有比传统SRAM单元更小的面积。
仍参照图1A至图1B,器件100还包括S/D部件162,S/D部件162包括分别设置在鳍104a和104b上方的S/D部件162a和162b。应该注意,为了简单起见,不是所有的S/D部件162都在图1A中示出。通常,S/D部件162设置在其相应的S/D区域中的每个鳍104上。在实施例中,S/D部件162a包括p型掺杂的硅锗,而S/D部件162b包括n型掺杂的硅。
器件100还包括介电层114,介电层114包括介电部件114a、114b和114c。具体地,介电部件114a设置在器件区域103a中的两行鳍104a之间,并且介电部件114b和114c设置在器件区域103b中的两组鳍104b之间,以及设置在器件区域103a和103b之间。介电层114填充CMG沟槽,并且因此称为CMG介电层114。CMG介电层114沿着X方向纵向布置,并且将一些栅极结构112分为至少两部分。在本实施例中,由虚线框113a和113b表示的区通过一个曝光和蚀刻工艺处理,而由虚线框113c表示的区通过另一曝光和蚀刻工艺处理。该方面将在之后详细讨论。介电部件114a设置在虚线框113a内,并且沿着X方向从栅极结构112的一个边缘扩展到栅极结构112的邻近边缘。介电部件114b设置在虚线框113b内,并且沿着X方向从栅极结构112的一个边缘扩展到栅极结构112的邻近边缘。介电部件114c设置在虚线框113c内,并且沿着X方向从栅极结构112的一个边缘扩展到栅极结构112的邻近边缘。在本实施例中,介电部件114b沿着Y方向比介电部件114c更宽。在本实施例中,介电部件114a、114b和114c包括相同的介电材料。在实施例中,介电部件114a沿着Y方向的宽度W1小于P1,并且在从16至18nm的范围。在实施例中,宽度W1设计为与光刻曝光工具的分辨率相同或略大于光刻曝光工具的分辨率,诸如分辨率为约13.3nm的EUV曝光工具。
参照图1B,CMG介电部件114a设置在两个S/D部件162a之间并与S/D部件162a物理接触。在实施例中,CMG介电部件114a和两个S/D部件162a之间的界面115在该截面图中为两条大致直线,其直线度取决于形成CMG介电部件114a的蚀刻和沉积工艺,将在之后讨论。在实施例中,每个界面115均与衬底102的顶面的法线(Z方向)形成在从0至5度的范围的角度。在实施例中,不同高度(沿着Z方向)处的两个界面115之间的水平(沿着Y方向)距离约相同或从顶部至底部线性单调递减。在另一实施例中,两个界面115从顶部至底部朝向彼此倾斜,无论它们是否为大致直线。界面115与S/D部件162a的其它小平面不同。其它小平面通过外延生长工艺形成并且通常遵循S/D部件162a的半导体材料的晶向,而界面115通过蚀刻S/D部件162a形成,而不管下面的晶向。
参照图1C,每个栅极结构112均包括高k介电层108和位于高k介电层108上方的导电层110。导电层110包括一个或多个金属材料层。因此,每个栅极结构112也称为高k金属栅极(或HK MG)112。栅极结构112还可以包括位于高k介电层108下方的界面层(未示出)。CMG介电部件114c将栅极结构112分成左侧部分和右侧部分。左侧部分接合鳍104a以形成晶体管,并且右侧部分接合两个鳍104b以形成另一晶体管。
参照图1D,在该截面图中,CMG介电部件114a与仅一个S/D部件162a物理接触。S/D部件162a、界面115和CMG介电部件114a的以上讨论也适用于图1D。
器件100还包括一个或多个介电层,诸如设置在S/D部件162a和隔离结构106上方的接触蚀刻停止层(CESL)164以及设置在隔离结构106、鳍104、栅极结构112和CESL 164上方的层间介电(ILD)层166。以下进一步描述器件100的组件。
在本实施例中,衬底102是硅衬底。可选地,衬底102可以包括另一元素半导体,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括硅锗、磷化镓砷、磷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、磷砷化镓铟;或它们的组合。
鳍104可以包括一种或多种半导体材料,诸如硅、锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、锑化铟、硅锗、磷砷化镓、磷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟和磷砷化镓铟。在实施例中,鳍104可以包括两种不同的半导体材料的交替堆叠层,诸如硅和硅锗交替堆叠的层。另外,鳍104可以额外地包括用于提高器件100的性能的掺杂剂。例如,鳍104可以包括诸如磷或砷的n型掺杂剂,或诸如硼或铟的p型掺杂剂。
隔离结构106可以包括氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其它合适的绝缘材料。隔离结构106可以是浅沟槽隔离(STI)部件。诸如场氧化物、硅的局部氧化(LOCOS)和/或其它合适的结构的其它隔离结构是可能的。隔离结构106可以包括多层结构,例如具有邻近于鳍104的一个或多个热氧化物衬垫层。
高k介电层108可以包括一种或多种高k介电材料(或一个或多个高k介电材料层),诸如氧化硅铪(HfSiO)、氧化铪(HfO2)、氧化铝(Al2O3)、氧化锆(ZrO2)、氧化镧(La2O3)、氧化钛(TiO2)、氧化钇(Y2O3)、钛酸锶(SrTiO3)或它们的组合。
导电层110包括一个或多个金属层,诸如功函金属层、导电阻挡层和金属填充层。功函金属层可以是p型或n型功函层,这取决于器件的类型(PFET或NFET)。p型功函层包含选自但不限于氮化钛(TiN)、氮化钽(TaN)、钌(Ru)、钼(Mo)、钨(W)、铂(Pt)或它们的组合的组的金属。n型功函层包括选自但不限于钛(Ti)、铝(Al)、碳化钽(TaC)、碳氮化钽(TaCN)、氮化钽硅(TaSiN)、氮化钛硅(TiSiN)或它们的组合的组的金属。金属填充层可以包括铝(Al)、钨(W)、钴(Co)和/或其它合适的材料。
CMG介电层114可以包括一种或多种介电材料,诸如氮化硅、氧化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其它合适的绝缘材料;并且可以通过CVD(化学汽相沉积)、PVD(物理汽相沉积)、ALD(原子层沉积)或其它合适的方法形成。
CESL 164可以包括氮化硅、氮氧化硅、具有氧(O)或碳(C)元素的氮化硅和/或其它材料;并且可以通过CVD、PVD、ALD或其它合适的方法形成。ILD层166可以包括正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其它合适的介电材料。可以通过PECVD(等离子体增强CVD)、FCVD(可流动CVD)或其它合适的方法形成ILD层166。
图2A、图2B和图2C示出了根据实施例的用于形成半导体器件100的方法200的流程图。方法200仅仅是实例,并且除了权利要求中的明确表述之外,方法200不旨在限制本发明。可以在方法200之前、期间和之后提供额外的操作,并且对于方法的额外实施例,可以替换、消除或移动所描述的一些操作。下面结合图3A至图18描述方法200,图3A至图18示出了根据方法200的制造步骤期间的半导体器件100的各个截面图。
在操作202中,方法200(图2A)提供或提供有器件结构100,器件结构100具有衬底102、突出于衬底102的鳍104(包括鳍104a和104b)以及位于衬底102上方和鳍104之间的隔离结构106,诸如图3A和图3B所示。具体地,图3A和图3B分别示出了沿着图1A的B-B线和C-C线的器件结构100的截面图。以上参照图1A至图1D已经讨论了用于衬底102、鳍104和隔离结构106的各种材料。
在实施例中,衬底102可以是晶圆,诸如硅晶圆。可以通过在衬底102的整个区上方外延生长一个或多个半导体层,并且之后图案化一个或多个半导体层以形成单独的鳍104来形成鳍104。可以通过任何合适的方法图案化鳍104。例如,可以使用包括双重图案化或多重图案化工艺的一种或多种光刻工艺图案化鳍104。通常,双重图案化或多重图案化工艺结合光刻和自对准工艺,允许创建具有例如比使用单个直接光刻工艺另外获得的间距更小的间距的图案。例如,在一个实施例中,在衬底上方形成牺牲层并且使用光刻工艺图案化牺牲层。使用自对准工艺在图案化的牺牲层旁边形成间隔件。之后去除牺牲层,并且之后可以使用剩余的间隔件或芯轴以通过蚀刻初始外延半导体层来图案化鳍104。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或其它合适的工艺。例如,干蚀刻工艺可以采用含氧气体、含氟气体(例如,CF4、SF6、CH2F2、CHF3和/或C2F6)、含氯气体(例如,Cl2、CHCl3、CCl4和/或BCl3)、含溴气体(例如,HBr和/或CHBR3)、含碘气体、其它合适的气体和/或等离子体和/或它们的组合。例如,湿蚀刻工艺可以包括以下中的蚀刻:稀释的氢氟酸(DHF);氢氧化钾(KOH)溶液;氨;包含氢氟酸(HF)、硝酸(HNO3)和/或醋酸(CH3COOH)的溶液;或其它合适的湿蚀刻剂。
隔离结构106可以通过一种或多种沉积和蚀刻方法形成。沉积方法可以包括热氧化、化学氧化和诸如可流动CVD(FCVD)的化学汽相沉积(CVD)。蚀刻方法可以包括干蚀刻、湿蚀刻和化学机械平坦化(CMP)。
在操作204中,方法200(图2A)形成接合鳍104的栅极结构112。在实施例中,操作204包括沉积包括栅极介电层108和导电层110的栅极结构112的各个层,并且图案化各个层以形成如图1A和图1C所示的栅极结构112。在具体实施例中,操作204使用替换栅极工艺,替换栅极工艺首先形成临时(或伪)栅极结构并且之后,用栅极结构112替换临时栅极结构。包括操作204a、204b和204c的图2B中示出了替换栅极工艺的实施例,将在以下进一步描述。
在操作204a中,方法200(图2B)形成接合鳍104的临时栅极结构149,诸如图4A和图4B所示,图4A和图4B分别示出了沿着图1A的A-A线和C-C线切割的器件100的截面图。参照图4A和图4B,每个临时栅极结构149均包括界面层150、电极层152和两个硬掩模层154和156。操作204a进一步在临时栅极结构149的侧壁上形成了栅极间隔件160。
介电层150可以包括诸如氧化硅层(例如,SiO2)或氮氧化硅(例如,SiON)的介电材料,并且可以通过化学氧化、热氧化、原子层沉积(ALD)、CVD和/或其它合适的方法形成。栅电极152可以包括多晶硅(poly-Si),并且可以通过诸如低压化学汽相沉积(LPCVD)和等离子体增强CVD(PECVD)的合适的沉积工艺形成。硬掩模层154和156的每个均可以包括诸如氧化硅和/或氮化硅的介电材料的一层或多层,并且可以通过CVD或其它合适的方法形成。可以通过光刻和蚀刻工艺来图案化各个层150、152、154和156。栅极间隔件160可以包括诸如氧化硅、氮化硅、氮氧化硅、碳化硅、其它介电材料或它们的组合的介电材料,并且可以包括一个或多个材料层。可以通过在隔离结构106,鳍104和临时栅极结构149上方沉积作为毯式层的间隔件材料来形成栅极间隔件160。之后,通过各向异性蚀刻工艺蚀刻间隔件材料以暴露隔离结构106、硬掩模层156和鳍104的顶面。位于临时栅极结构149的侧壁上的间隔件材料的部分变成栅极间隔件160。邻近的栅极间隔件160提供沟槽158,沟槽158暴露器件100的S/D区域中的鳍104。
在操作206中,方法200(图2A和图2B)形成源极/漏极(或S/D)部件162,诸如图5A和图5B所示,图5A和图5B分别是沿着图1A的A-A线和B-B线的器件100的截面图。例如,操作206可以蚀刻至暴露在沟槽158中的鳍104内的沟槽,并且在凹槽中外延生长半导体材料。如图5A和图5B示出的,半导体材料可以凸出于鳍104的顶面之上。操作206可以形成分别用于NFET和PFET器件的S/D部件162。例如,操作206可以形成用于NFET器件的具有n型掺杂硅的S/D部件162b,并且形成用于PFET器件的具有p型掺杂的硅锗的S/D部件162a。在本实施例中,一些S/D部件162合并在一起,例如图5B所示。具体地,设计为用于两个单独的PFET的两个S/D部件162a合并,并且设计为用于多鳍NFET的两个S/D部件162b也合并。通常,设计为用于两个单独的晶体管(而不是多鳍晶体管)的两个S/D部件不允许合并在一起。为了避免合并,两个鳍104a之间的间隔通常设计为大于S/D部件162a的横向尺寸。这通常需要两个单独的晶体管的更大的间隔(更多的区)或者更小的外延S/D部件。都不是理想的,因为前者会减小器件集成度,而后者会增加S/D接触电阻。本发明通过初始生长足够大的S/D部件162a以合并,并且之后蚀刻合并的S/D部件将它们分隔开来对一般方法进行改进,这将在之后详细的讨论。
在操作208中,方法200(图2A和图2B)形成各个部件,包括位于S/D部件162上方的接触蚀刻停止层(CESL)164,以及位于CESL 164上方的层间介电(ILD)层166,诸如图6A和图6B所示,图6A和图6B分别是沿着图1A的A-A线和B-B线的器件100的截面图。CESL 164可以包括氮化硅、氮氧化硅、具有氧(O)或碳(C)元素的氮化硅和/或其它材料;并且可以通过CVD、PVD(物理汽相沉积)、ALD或其它合适的方法形成。ILD层166可以包括正硅酸乙酯(TEOS)氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))和/或其它合适的介电材料。可以通过PECVD、FCVD或其它合适的方法形成ILD层166。操作208可以实施一个或多个CMP工艺以平坦化器件100的顶面,去除硬掩模层154和156并且暴露电极层152。
在操作204b中,方法200(图2B)去除临时栅极结构149以形成栅极沟槽169,诸如图7A和图7B所示,图7A和图7B分别是沿着图1A的A-A线和C-C线的器件100的截面图。栅极沟槽169暴露鳍104的表面和栅极间隔件160的侧壁表面。操作204b可以包括对电极层152和界面层150的材料具有选择性的一个或多个蚀刻工艺。蚀刻工艺可以包括干蚀刻、湿蚀刻、反应离子蚀刻或其它合适的蚀刻方法。
在操作204c中,方法200(图2B)在栅极沟槽169中沉积栅极结构(例如,高k金属栅极)112,诸如图8A和图8B所示,图8A和图8B分别是沿着图1A的A-A线和C-C线的器件100的截面图。栅极结构112包括高k介电层108和导电层110。栅极结构112还可以包括位于高k介电层108和鳍104之间的界面层(例如,SiO2)(未示出)。可以使用化学氧化、热氧化、ALD、CVD和/或其它合适的方法来形成界面层。以上参照图A至图1D讨论了高k介电层108和导电层110的材料。高k介电层108可以包括一个或多个高k介电材料层,并且可以使用CVD、ALD和/或其它合适的方法来沉积。导电层110可以包括一个或多个功函金属层和金属填充层,并且可以使用诸如CVD、PVD、镀和/或其它合适的工艺来沉积。
在操作210中,方法200(图2A和图2B)在器件100上方形成一个或多个图案化的硬掩模层,诸如图9A和图9B所示,图9A和图9B分别是沿着图1A的B-B线和C-C线的器件100的截面图。在该实例中示出了一个硬掩模层170。硬掩模层170可以包括氮化钛、氮化硅、非晶硅、硅酸钇(YSiOx)或其它合适的硬掩模材料。在实施例中,操作210使用CVD、PVD、ALD或其它合适的方法来沉积硬掩模层170,并且随后图案化硬掩模层170以形成开口171。开口171对应于图1A的虚线框113a和113b。开口171暴露导电层110和ILD层166。在实例中,操作210可以通过光刻胶涂覆、曝光、曝光后烘烤和显影在硬掩模层170上方形成图案化的光刻胶。图案化的光刻胶提供对应于图1A的框113a和113b的开口。在具体实施例中,操作210使用单个曝光工艺(例如,使用EUV曝光)来曝光光刻胶层以具有包括虚线框113a和113b的潜像,并且之后显影光刻胶层以提供开口。之后,操作210使用图案化的光刻胶作为蚀刻掩模蚀刻硬掩模层170以形成开口171。蚀刻工艺可以包括湿蚀刻、干蚀刻、反应离子蚀刻或其它合适的蚀刻方法。之后,例如通过光刻胶剥离去除图案化的光刻胶。
在操作212中,方法200(图2A)通过开口171蚀刻器件100。图案化的硬掩模层170保护器件100的剩余部分免受蚀刻工艺的影响。在本实施例中,操作212使用蚀刻工艺,蚀刻工艺调整为选择性地蚀刻ILD层166和S/D部件162a,而不(或不显著地)蚀刻栅极结构(例如,HK MG)112。例如,操作212可以使用氟化氢(HF)和氨的干蚀刻工艺,并且可以使用氩气作为载气。这些蚀刻剂对氧化物(在ILD层166中)和硅或硅锗(在S/D部件162中)具有选择性,并且不能较好地蚀刻栅极结构112中的导电层110。参照图10,图10是沿图1A的B-B线的器件100的截面图,操作212将开口171向下延伸并穿过ILD层166和S/D部件162a,并且可以将开口171延伸至隔离结构106内。在沿着图1A的C-C线的器件100的截面图中,器件100保持与图9B所示大致相同,因为蚀刻工艺调整为不蚀刻导电层110。
在操作214中,方法200(图2A)用一种或多种介电材料填充沟槽171以形成包括介电部件114a和114b的介电层114,并且实施化学机械抛光(CMP)工艺以去除图案化的硬掩模170并且平坦化器件100的顶面。产生的器件100在图11中示出。由于栅极结构112的侧壁包含金属材料,因此至少介电层114的外部(与栅极结构112的侧壁直接接触)不含诸如氧的活性化学组分。例如,介电层114的外部可以包括氮化硅并且不含氧或氧化物。在一些实施例中,介电层114可以在其内部包括一些氧化物。可选地,介电层114可以包括一个均匀的氮化硅层并且不含氧化物。可以使用CVD、PVD、ALD或其它合适的方法沉积介电层114。在本实施例中,使用ALD沉积介电层114以确保其完全地填充沟槽171。
在操作216中,方法200(图2C)在器件100上方形成另一图案化的掩模172。图案化的掩模172提供开口173,诸如图12A和图12B所示,图12A和图12B分别是沿着图1A的B-B线和C-C线的器件100的截面图。开口173对应于图1A的虚线框113c。具体地,开口173暴露栅极结构112的将要切割的部分。可以通过单个图案化工艺或多个图案化工艺形成开口173。硬掩模层172可以包括氮化钛、氮化硅、非晶硅、硅酸钇(YSiOx)或其它合适的硬掩模材料;并且可以使用CVD、PVD、ALD或其它合适的方法沉积。在实例中,操作216可以通过光刻胶涂覆、曝光、曝光后烘烤和显影在硬掩模层172上方形成图案化的光刻胶。之后,操作216使用图案化的光刻胶作为蚀刻掩模蚀刻硬掩模层172以形成开口173。蚀刻工艺可以包括湿蚀刻、干蚀刻、反应离子蚀刻或其它合适的蚀刻方法。之后,例如通过光刻胶剥离去除图案化的光刻胶。
在操作218中,方法200(图2C)通过开口173蚀刻栅极结构112。参照图13,在实施例中,操作218将开口173向下延伸并穿过栅极结构112,并且也可以将开口173延伸至隔离结构106内。蚀刻工艺可以使用蚀刻栅极结构112中的各个层的一种或多种蚀刻剂或蚀刻剂的混合物。在示例性实施例中,导电层110包括TiSiN、TaN、TiN、W或它们的组合。为了蚀刻这种导电层和高k介电层108,操作218可以利用具有氯、氟、溴、氧、氢、碳或它们的组合的原子的蚀刻剂来施加干蚀刻工艺。例如,蚀刻剂可以具有Cl2、O2、含碳和氟的气体、含溴和氟的气体以及含碳氢和氟的气体的气体混合物。在一个实例中,蚀刻剂包括Cl2、O2、CF4、BCl3和CHF3的气体混合物。在一些实施例中,为了确保栅极结构112的剩余部分之间的隔离,操作218实施一些过蚀刻以将开口173延伸至隔离结构106内。小心地控制这种过蚀刻以不暴露衬底102。
在操作220中,方法200(图2C)用一种或多种介电材料填充沟槽173以形成介电部件114c,并且实施化学机械抛光(CMP)工艺以去除图案化的硬掩模层172并且平坦化器件100的顶面。
产生的结构在图14A和图14B中示出,图14A和图14B分别是沿着图1A的B-B线和C-C线的器件100的截面图。具体地,沟槽171中的一种或多种介电材料形成介电部件114a和114b,并且沟槽173中的一种或多种介电材料形成介电部件114c。由于栅极结构112的侧壁包含金属材料,因此至少介电层114的外部(与栅极结构112的侧壁直接接触)不含诸如氧的活性化学组分。例如,介电层114的外部可以包括氮化硅并且不含氧或氧化物。在一些实施例中,介电层114可以在其内部包括一些氧化物。可选地,介电层114可以包括一个均匀的氮化硅层并且不含氧化物。可以使用CVD、PVD、ALD或其它合适的方法沉积介电层114。在本实施例中,使用ALD沉积介电层114以确保其完全地填充沟槽171和173。
在操作222中,方法200(图2C)在器件100上方沉积介电层180,诸如图15所示,图15是沿着图1A的B-B线的器件的截面图。在实施例中,介电层180是另一ILD层并且可以包括TEOS氧化物、未掺杂的硅酸盐玻璃或掺杂的氧化硅(诸如BPSG、FSG、PSG、BSG)和/或其它合适的介电材料。可以通过PECVD、FCVD或其它合适的方法形成ILD层180。
在操作224中,方法200(图2C)在器件100内蚀刻接触孔182,包括暴露S/D部件162a的接触孔182a和暴露S/D部件162b的接触孔162b,诸如图16所示,图16是沿着图1A的B-B线的器件的截面图。在实施例中,操作224包括在器件100上方涂覆光刻胶层,曝光和显影光刻胶层以形成开口,并且通过开口蚀刻各个层180、166和164以形成接触孔182。具体地,蚀刻工艺调整为选择性地蚀刻层180、166和164,而不蚀刻S/D部件162和介电层144。在实施例中,蚀刻工艺是干蚀刻。
在操作226中,方法200(图2C)将一种或多种导电材料184沉积至接触孔182内,诸如图17所示,图17是沿着图1A的B-B线的器件的截面图。在实施例中,方法200可以在沉积导电材料184之前,在S/D部件162的暴露表面上方形成硅化物部件。在实施例中,导电材料184包括诸如TaN或TiN的阻挡层和诸如Al、Cu或W的金属填充层。可以使用CVD、PVD、镀或其它合适的方法沉积导电材料184。
在操作228中,方法200(图2C)实施CMP工艺以去除过量的材料184并且暴露介电层114,诸如图18所示,图18是沿着图1A的B-B线的器件的截面图。参照图18,在本实施例中,操作228的CMP工艺将位于两个S/D部件162a之上的导电材料184分隔开,从而形成由介电部件114a隔离的两个S/D接触件。由于S/D部件162a的较大的表面积,因此两个S/D接触件的每个均与下面的S/D部件162a具有足够大的界面,以用于减小S/D接触电阻。
在操作230中,方法200(图2C)实施进一步步骤以完成器件100的制造。例如,方法200可以形成电连接各个晶体管的源极、漏极、栅极端子的金属互连件以形成完整的IC。
虽然不旨在限制,但是本发明的一个或多个实施例为半导体器件及其形成提供许多益处。例如,本发明的实施例提供了两步切割金属栅极工艺,其中,第一步蚀刻介电层而不蚀刻金属栅极,并且第二步蚀刻金属栅极。之后,本发明的实施例利用第一蚀刻步骤将设计为用于单独的晶体管的先前合并的S/D部件分隔开。在本发明的实施例中,与传统器件相比,这允许用于单独的晶体管的半导体鳍更靠近布置,并且与传统器件相比,S/D部件生长地更大。这不仅增加了器件集成度,并且也减小了S/D接触电阻。
在一个示例性方面,本发明涉及方法。该方法包括提供具有衬底以及第一和第二鳍的结构,第一和第二鳍位于衬底上方并且通常沿着第一方向纵向定向;在第一和第二鳍上方外延生长半导体源极/漏极(S/D)部件,其中,位于第一鳍上方的第一半导体S/D部件与位于第二鳍上方的第二半导体S/D部件合并;以及对第一和第二鳍之间的区实施第一蚀刻工艺,其中,第一蚀刻工艺将第一半导体S/D部件和第二半导体S/D部件分隔开。
在实施例中,该方法还包括,在实施第一蚀刻工艺之前,在衬底以及第一和第二鳍上方形成栅极结构,其中,栅极结构通常沿着垂直于第一方向的第二方向纵向定向,其中,第一蚀刻工艺调整为选择性地蚀刻第一和第二半导体S/D部件,而不蚀刻栅极结构。在进一步实施例中,其中,栅极结构的形成包括在衬底以及第一和第二鳍上方形成临时栅极结构;在临时栅极结构和半导体S/D部件上方沉积介电层;去除临时栅极结构,在介电层中产生栅极沟槽;以及在栅极沟槽中沉积栅极结构。在进一步实施例中,第一蚀刻工艺也调整为蚀刻介电层。在实施第一蚀刻工艺在第一和第二鳍之间的区中的介电层中产生沟槽的进一步实施例中,该方法还包括在沟槽中沉积一种或多种介电材料。在进一步实施例中,该方法还包括蚀刻暴露第一和第二半导体S/D部件的接触孔;在接触孔中沉积导电材料;以及实施化学机械抛光(CMP)工艺以将导电材料分成第一部分和第二部分,其中,第一部分和第二部分分别电连接至第一半导体S/D部件和第二半导体S/D部件,并且彼此通过一种或多种介电材料隔离。
在另一实施例中,该结构还包括位于衬底上方并且通常沿着第一方向纵向定向的第三鳍;也在第三鳍上方形成栅极结构;以及对第二和第三鳍之间的区实施第一蚀刻工艺。在进一步实施例中,该方法还包括对第二和第三鳍之间的区实施第二蚀刻工艺,其中,第二蚀刻工艺调整为蚀刻栅极结构。
在方法的实施例中,第一和第二半导体S/D部件均包括p型掺杂的硅锗。在实施第一蚀刻工艺在第一和第二半导体S/D部件之间产生沟槽的另一实施例中,该方法还包括在沟槽中沉积一种或多种介电材料。
在另一示例性方面,本发明针对方法。该方法包括提供结构,该结构具有:衬底;第一、第二和第三鳍,位于衬底上方并且通常沿着第一方向纵向定向;栅极结构,位于第一、第二和第三鳍上方并且通常沿着垂直于第一方向的第二方向纵向定向;第一和第二外延半导体源极/漏极(S/D)部件,分别位于第一和第二鳍上方,其中,第一和第二外延半导体源极/漏极(S/D)部件沿着第二方向合并;以及第一介电层,位于衬底、第一、第二和第三鳍以及第一和第二外延半导体S/D部件上方并且填充栅极结构之间的间隔。该方法还包括对第一和第二鳍之间的第一区以及第二和第三鳍之间的第二区实施第一蚀刻工艺,其中,第一蚀刻工艺调整为选择性地蚀刻第一和第二外延半导体S/D部件和第一介电层,而不蚀刻栅极结构。该方法还包括对第二区实施第二蚀刻工艺,其中,第二蚀刻工艺调整为选择性地蚀刻栅极结构。
在方法的实施例中,第一蚀刻工艺将第一和第二外延半导体S/D部件分隔开。在第一蚀刻工艺在第一和第二外延半导体S/D部件之间产生第一沟槽的另一实施例中,该方法还包括在第一沟槽中沉积一种或多种介电材料。在进一步实施例中,第一和第二蚀刻工艺共同形成第二和第三鳍之间的第二沟槽,并且也在第二沟槽中沉积一种或多种介电材料。
在方法的实施例中,第一蚀刻工艺包括具有氟化氢和氨的蚀刻剂的干蚀刻。在方法的另一实施例中,第二蚀刻工艺使用含氯蚀刻剂。
在又另一示例性方面,本发明针对半导体结构。半导体结构包括衬底;第一和第二鳍,位于衬底上方并且通常沿着第一方向纵向定向;第一和第二外延半导体源极/漏极(S/D)部件,分别位于第一和第二鳍上方;以及第一介电层,设置在第一和第二外延半导体S/D部件之间并且与第一和第二外延半导体S/D部件物理接触,在第一介电层和第一外延半导体S/D部件之间产生第一界面,并且在第一介电层和第二外延半导体S/D部件之间产生第二界面,其中,第一和第二界面从顶部至底部朝向彼此倾斜。
在实施例中,半导体结构还包括栅极结构,位于第一和第二鳍上方并且通常沿着第二方向纵向定向;以及第二介电层,位于衬底、第一和第二鳍以及第一和第二外延半导体S/D部件上方并且填充栅极结构之间的间隔,其中,第一和第二介电层包括不同的介电材料。在进一步实施例中,半导体结构还包括第二介电层与第一和第二外延半导体S/D部件之间的接触蚀刻停止层。
在另一实施例中,半导体结构还包括第一导电部件,位于第一外延半导体S/D部件上方;以及第二导电部件,位于第二外延半导体S/D部件上方,其中,第一介电层设置在第一和第二导电部件之间。
在半导体结构的实施例中,第一和第二界面在沿着垂直于第一方向的第二方向切割的截面图中为两条大致直线。在进一步实施例中,两条大致直线的每个均与衬底的顶面的法线形成在从0至5度的范围的角度。
在半导体结构的另一实施例中,第一和第二外延半导体S/D部件的每个均包括p型掺杂的硅锗。
在又另一实施例中,半导体结构还包括第三鳍,位于衬底上方并且通常沿着第一方向纵向定向;以及第三外延半导体S/D部件,位于第三鳍上方,其中,第一介电层也设置在第二和第三外延半导体S/D部件之间。在进一步实施例中,第一介电层没有与第三外延半导体S/D部件直接接触。在另一进一步实施例中,第一和第二外延半导体S/D部件的每个均包括p型掺杂的硅锗;并且第三外延半导体S/D部件包括n型掺杂的硅。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (10)
1.一种制造半导体结构的方法,包括:
提供具有衬底以及第一鳍和第二鳍的结构,所述第一鳍和所述第二鳍位于所述衬底上方并且沿着第一方向纵向定向;
在所述第一鳍和所述第二鳍上方外延生长半导体源极/漏极(S/D)部件,其中,位于所述第一鳍上方的第一半导体源极/漏极部件与位于所述第二鳍上方的第二半导体源极/漏极部件合并;以及
对所述第一鳍和所述第二鳍之间的区实施第一蚀刻工艺,其中,所述第一蚀刻工艺将所述第一半导体源极/漏极部件和所述第二半导体源极/漏极部件分隔开。
2.根据权利要求1所述的方法,还包括,在实施所述第一蚀刻工艺之前:
在所述衬底以及所述第一鳍和所述第二鳍上方形成栅极结构,其中,所述栅极结构沿着垂直于所述第一方向的第二方向纵向定向,
其中,所述第一蚀刻工艺调整为选择性地蚀刻所述第一半导体源极/漏极部件和所述第二半导体源极/漏极部件,而不蚀刻所述栅极结构。
3.根据权利要求2所述的方法,其中,所述栅极结构的形成包括:
在所述衬底以及所述第一鳍和所述第二鳍上方形成临时栅极结构;
在所述临时栅极结构和所述半导体源极/漏极部件上方沉积介电层;
去除所述临时栅极结构,在所述介电层中产生栅极沟槽;以及
在所述栅极沟槽中沉积所述栅极结构。
4.根据权利要求3所述的方法,其中,所述第一蚀刻工艺也调整为蚀刻所述介电层。
5.根据权利要求4所述的方法,其中,实施所述第一蚀刻工艺在所述第一鳍和所述第二鳍之间的区中的所述介电层中产生沟槽包括:
在所述沟槽中沉积一种或多种介电材料。
6.根据权利要求5所述的方法,还包括:
蚀刻暴露所述第一半导体源极/漏极部件和所述第二半导体源极/漏极部件的接触孔;
在所述接触孔中沉积导电材料;以及
实施化学机械抛光(CMP)工艺以将所述导电材料分成第一部分和第二部分,其中,所述第一部分和所述第二部分分别电连接至所述第一半导体源极/漏极部件和所述第二半导体源极/漏极部件,并且通过所述一种或多种介电材料彼此隔离。
7.根据权利要求2所述的方法,其中:
所述结构还包括位于所述衬底上方并且沿着所述第一方向纵向定向的第三鳍;
所述栅极结构也形成在所述第三鳍上方;以及
也对所述第二鳍和所述第三鳍之间的区实施所述第一蚀刻工艺。
8.根据权利要求7所述的方法,还包括:
对所述第二鳍和所述第三鳍之间的区实施第二蚀刻工艺,其中,所述第二蚀刻工艺调整为蚀刻所述栅极结构。
9.一种制造半导体结构的方法,包括:
提供结构,所述结构具有:
衬底;
第一鳍、第二鳍和第三鳍,位于所述衬底上方并且沿着第一方向纵向定向;
栅极结构,位于所述第一鳍、所述第二鳍和所述第三鳍上方并且沿着垂直于所述第一方向的第二方向纵向定向;
第一外延半导体源极/漏极(S/D)部件和第二外延半导体源极/漏极(S/D)部件,分别位于所述第一鳍和所述第二鳍上方,其中,所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件沿着所述第二方向合并;和
第一介电层,位于所述衬底、所述第一鳍、所述第二鳍和所述第三鳍以及所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件上方,并且填充所述栅极结构之间的间隔;
对所述第一鳍和所述第二鳍之间的第一区以及所述第二鳍和所述第三鳍之间的第二区实施第一蚀刻工艺,其中,所述第一蚀刻工艺调整为选择性地蚀刻所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件以及所述第一介电层,而不蚀刻所述栅极结构;以及
对所述第二区实施第二蚀刻工艺,其中,所述第二蚀刻工艺调整为选择性地蚀刻所述栅极结构。
10.一种半导体结构,包括:
衬底;
第一鳍和第二鳍,位于所述衬底上方并且沿着第一方向纵向定向;
第一外延半导体源极/漏极(S/D)部件和第二外延半导体源极/漏极(S/D)部件,分别位于所述第一鳍和所述第二鳍上方;以及
第一介电层,设置在所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件之间并且与所述第一外延半导体源极/漏极部件和所述第二外延半导体源极/漏极部件物理接触,在所述第一介电层和所述第一外延半导体源极/漏极部件之间产生第一界面,并且在所述第一介电层和所述第二外延半导体源极/漏极部件之间产生第二界面,其中,所述第一界面和所述第二界面从顶部至底部朝向彼此倾斜。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113284849A (zh) * | 2020-02-19 | 2021-08-20 | 台湾积体电路制造股份有限公司 | 半导体器件和形成半导体器件的方法 |
CN113284848A (zh) * | 2020-02-19 | 2021-08-20 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN113764346A (zh) * | 2020-08-14 | 2021-12-07 | 台湾积体电路制造股份有限公司 | 半导体结构及其形成方法 |
CN114641856A (zh) * | 2019-11-13 | 2022-06-17 | 高通股份有限公司 | 采用替代n型fet源极/漏极(s/d)以避免或防止短路缺陷的鳍式场效应晶体管(fet)电路以及相关制造方法 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10373879B2 (en) * | 2017-04-26 | 2019-08-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with contracted isolation feature and formation method thereof |
US10510875B2 (en) * | 2017-07-31 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Source and drain structure with reduced contact resistance and enhanced mobility |
US10461078B2 (en) * | 2018-02-26 | 2019-10-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Creating devices with multiple threshold voltage by cut-metal-gate process |
KR102476142B1 (ko) * | 2018-03-14 | 2022-12-09 | 삼성전자주식회사 | 반도체 장치 |
US11398474B2 (en) * | 2018-09-18 | 2022-07-26 | Intel Corporation | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions |
US11264268B2 (en) | 2018-11-29 | 2022-03-01 | Taiwan Semiconductor Mtaiwananufacturing Co., Ltd. | FinFET circuit devices with well isolation |
US11177181B2 (en) | 2020-01-15 | 2021-11-16 | International Business Machines Corporation | Scalable device for FINFET technology |
DE102020115553A1 (de) * | 2020-02-27 | 2021-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cut-epi-verfahren und strukturen |
US11404570B2 (en) | 2020-02-27 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor devices with embedded ferroelectric field effect transistors |
TW202139270A (zh) | 2020-02-27 | 2021-10-16 | 台灣積體電路製造股份有限公司 | 半導體裝置的形成方法 |
US11515211B2 (en) * | 2020-02-27 | 2022-11-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Cut EPI process and structures |
US11664423B2 (en) * | 2020-08-18 | 2023-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a source/drain of a semiconductor device having an insulating stack in a recess structure |
US11784228B2 (en) | 2021-04-09 | 2023-10-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process and structure for source/drain contacts |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140134814A1 (en) * | 2012-11-12 | 2014-05-15 | GlobalFoundries, Inc. | Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions |
US20160079367A1 (en) * | 2014-09-12 | 2016-03-17 | Jeong-Ho Yoo | Semiconductor device and method for fabricating the same |
CN106057867A (zh) * | 2015-04-14 | 2016-10-26 | 三星电子株式会社 | 半导体器件 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9245805B2 (en) | 2009-09-24 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Germanium FinFETs with metal gates and stressors |
US8816444B2 (en) | 2011-04-29 | 2014-08-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and methods for converting planar design to FinFET design |
US8962400B2 (en) | 2011-07-07 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | In-situ doping of arsenic for source and drain epitaxy |
US8841701B2 (en) | 2011-08-30 | 2014-09-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET device having a channel defined in a diamond-like shape semiconductor structure |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US8847293B2 (en) | 2012-03-02 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structure for semiconductor device |
US8836016B2 (en) | 2012-03-08 | 2014-09-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods with high mobility and high energy bandgap materials |
US8785285B2 (en) | 2012-03-08 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
US8860148B2 (en) | 2012-04-11 | 2014-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for FinFET integrated with capacitor |
US9368388B2 (en) * | 2012-04-13 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus for FinFETs |
US9105490B2 (en) | 2012-09-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8823065B2 (en) | 2012-11-08 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US8772109B2 (en) | 2012-10-24 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for forming semiconductor contacts |
US9236300B2 (en) | 2012-11-30 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact plugs in SRAM cells and the method of forming the same |
US8853025B2 (en) | 2013-02-08 | 2014-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET/tri-gate channel doping for multiple threshold voltage tuning |
US9093514B2 (en) | 2013-03-06 | 2015-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Strained and uniform doping technique for FINFETs |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
KR102310080B1 (ko) * | 2015-03-02 | 2021-10-12 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
KR102413371B1 (ko) * | 2015-11-25 | 2022-06-28 | 삼성전자주식회사 | 반도체 소자 |
KR102587891B1 (ko) * | 2016-12-22 | 2023-10-12 | 삼성전자주식회사 | 반도체 소자 |
US10453935B2 (en) * | 2017-04-20 | 2019-10-22 | International Business Machines Corporation | Thermally stable salicide formation for salicide first contacts |
-
2017
- 2017-11-30 US US15/827,709 patent/US10319581B1/en active Active
-
2018
- 2018-04-26 CN CN201810385047.2A patent/CN109860117B/zh active Active
- 2018-07-05 TW TW107123357A patent/TWI698938B/zh active
-
2019
- 2019-05-24 US US16/421,532 patent/US10651030B2/en active Active
-
2020
- 2020-04-21 US US16/854,627 patent/US11239072B2/en active Active
-
2022
- 2022-01-31 US US17/588,883 patent/US11721544B2/en active Active
-
2023
- 2023-07-28 US US18/361,743 patent/US20230377873A1/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140134814A1 (en) * | 2012-11-12 | 2014-05-15 | GlobalFoundries, Inc. | Methods of manufacturing integrated circuits having finfet structures with epitaxially formed source/drain regions |
US20160079367A1 (en) * | 2014-09-12 | 2016-03-17 | Jeong-Ho Yoo | Semiconductor device and method for fabricating the same |
CN106057867A (zh) * | 2015-04-14 | 2016-10-26 | 三星电子株式会社 | 半导体器件 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114641856A (zh) * | 2019-11-13 | 2022-06-17 | 高通股份有限公司 | 采用替代n型fet源极/漏极(s/d)以避免或防止短路缺陷的鳍式场效应晶体管(fet)电路以及相关制造方法 |
CN113284849A (zh) * | 2020-02-19 | 2021-08-20 | 台湾积体电路制造股份有限公司 | 半导体器件和形成半导体器件的方法 |
CN113284848A (zh) * | 2020-02-19 | 2021-08-20 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
CN113764346A (zh) * | 2020-08-14 | 2021-12-07 | 台湾积体电路制造股份有限公司 | 半导体结构及其形成方法 |
US11984478B2 (en) | 2020-08-14 | 2024-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Forming source and drain features in semiconductor devices |
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US20200251325A1 (en) | 2020-08-06 |
US11721544B2 (en) | 2023-08-08 |
CN109860117B (zh) | 2021-02-26 |
US11239072B2 (en) | 2022-02-01 |
US10319581B1 (en) | 2019-06-11 |
US20220157595A1 (en) | 2022-05-19 |
US10651030B2 (en) | 2020-05-12 |
US20230377873A1 (en) | 2023-11-23 |
TW201926478A (zh) | 2019-07-01 |
TWI698938B (zh) | 2020-07-11 |
US20190318922A1 (en) | 2019-10-17 |
US20190164741A1 (en) | 2019-05-30 |
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