CN109786269A - Reduce the method and semi-finished product structure of package substrate warpage - Google Patents

Reduce the method and semi-finished product structure of package substrate warpage Download PDF

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Publication number
CN109786269A
CN109786269A CN201811026567.0A CN201811026567A CN109786269A CN 109786269 A CN109786269 A CN 109786269A CN 201811026567 A CN201811026567 A CN 201811026567A CN 109786269 A CN109786269 A CN 109786269A
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package substrate
grooving
positioning
package
round orifice
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CN201811026567.0A
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蔡宜兴
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Abstract

The present invention discloses a kind of method and semi-finished product structure for reducing package substrate warpage, wherein the method for reducing package substrate warpage purchases step, an encapsulation step and a laser cutting step comprising one.It is cut with the first grooving in the insulation adhesive layer of package substrate by the laser aid in the laser cutting step, is destroyed the stress of the package substrate, thus reduces the warping phenomenon of the package substrate.

Description

Reduce the method and semi-finished product structure of package substrate warpage
Technical field
The present invention relates to a kind of method and semi-finished product structures, especially with regard to a kind of method for reducing package substrate warpage And semi-finished product structure.
Background technique
Electronic product is towards light and short trend development, and electronic packaging also develops towards same trend, for carrying chip Package substrate it is also more and more thinner, by the thermal expansion coefficient difference of material properties in each semiconductor subassembly, derivative is caused to seal The problem of filling warpage (Warpage) and stress (Stress), these will all will affect the yield of semiconductor packages.In semiconductor package The step of necessarily having heat treatment in dress processing procedure, the package substrate of especially low profile electronic packaging structure thinner thickness is multiple one Body forms in a package substrate item, because rigidity is weaker, is easier to answer in the lower generation that temperature change influences during fabrication Power and cause package substrate buckling deformation, be more likely to cause the operating difficulties of the destruction of electronic building brick and subsequent processing.Into one For step, when being packaged base plate line layout, average wiring density, some regional metal distributing lines usually cannot keep Road is intensive, and then route is very sparse for some places.In encapsulation process, the deviation situation and base of so regional line density Plate and the material of sealing itself have different thermal expansion coefficients, thus after heated (such as baking drying, resin solidification, Gluing fixed chip, routing or sealing injection molding), it will lead to package substrate and easily deform warpage (warpage), cause subsequent Can not be accurately isolated at multiple single packaging structures by dress substrate strip semi-finished product cutting by packing colloid, to cause under yield Drop.Therefore, requirement of the current encapsulation dealer for package substrate that resist warping is also higher and higher.
Therefore, it is necessary to the method and semi-finished product structure of a kind of reduction package substrate warpage of improvement are provided, it is existing to solve There is the problems of technology.
Summary of the invention
The main purpose of the present invention is to provide a kind of methods and semi-finished product structure for reducing package substrate warpage, will be described Insulation adhesive layer on the package substrate of semi-finished product structure is cut with the first grooving, is destroyed the stress of the package substrate, Thus reduce the warping phenomenon of the package substrate.
In order to achieve the above object, the present invention provides a kind of method for reducing package substrate warpage, purchases step, one comprising one Encapsulation step and a laser cutting step;Wherein the step of purchasing is to provide a package substrate, and the package substrate has one Package surface, wherein the package surface is formed with multiple precut roads and multiple crystalline setting areas, the precut road is interlaced with each other Arrangement, the crystalline setting area is located between the precut road;The encapsulation step is that multiple chips are separately positioned on institute Crystalline setting area is stated, and forms a packing colloid and coats the chip, the package surface is made to form an insulation adhesive layer;The laser Cutting step is to cut and cross to the insulation adhesive layer, and be formed at least three the first groovings.
In one embodiment of this invention, purchased in step described, the one first opposite side of the package substrate and One second side is formed with multiple first positioning round orifice, and first grooving respectively corresponds the first positioning round orifice arrangement.
In one embodiment of this invention, it is additionally comprised after the encapsulation step and before the laser cutting step One positioning step, to shoot the position of first positioning round orifice using a video camera and carry out the positioning of the package substrate.
In one embodiment of this invention, it in the positioning step, when the positioning of the package substrate is completed, penetrates One processor loads the location parameter of the chip, to carry out as in the laser cutting step to the insulation adhesive layer The benchmark cut and crossed.
In one embodiment of this invention, one is additionally comprised before the laser cutting step and after the positioning step Substrate screed step makes the encapsulation base to attract the package surface or a lower surface of the package substrate using multiple suction nozzles Plate is maintained at a leveling state.
In one embodiment of this invention, a cleaning is additionally comprised after the laser cutting step, is inhaled using one Dirt device cleans first grooving.
In order to achieve the above object, the present invention provides a kind of semi-finished product structure for reducing package substrate warpage, includes an encapsulation Substrate, multiple first positioning round orifice and an insulation adhesive layer;Wherein the package substrate has a package surface, wherein the envelope Dress surface is formed with multiple precut roads and multiple crystalline setting areas, the precut road arrangement interlaced with each other, the crystalline setting area difference Between the precut road;First positioning round orifice is formed in the one first opposite side and one of the package substrate Two sides, wherein corresponding to each other positioned at the first side of the package substrate and first positioning round orifice of second side;The insulator seal Glue-line is formed in the package surface of the package substrate, wherein the insulator seal glue-line is formed at least three the first groovings, Respectively correspond the first positioning round orifice arrangement.
In one embodiment of this invention, the structure for reducing package substrate warpage additionally comprises multiple second setting circles Hole is formed in an opposite third side and one the 4th side for the package substrate, wherein being located at the third side of the package substrate And the 4th second positioning round orifice of side correspond to each other.
In one embodiment of this invention, the insulation adhesive layer is separately formed at least three the second groovings, respectively corresponds The second positioning round orifice arrangement, and first grooving intersects with second grooving.
In one embodiment of this invention, first grooving and the second grooving row corresponding with the precut road respectively Column.
As described above, the insulation adhesive layer on the package substrate of the semi-finished product structure is cut with first grooving, Be destroyed the package substrate in the stress of the first side and the second side direction, thus reduce the package substrate in the first side and In addition the warping phenomenon of second side direction is cut with second grooving again, make the package substrate in third side and the 4th side The stress in direction is destroyed, thus reduces the package substrate in third side and the warping phenomenon of the 4th side direction.Simultaneously as First grooving and the second grooving of pre-cut form the duct in the corresponding precut road in the insulation adhesive layer, make described Package substrate is thinning in the subsequent thickness for carrying out multiple packing colloid cutting paths, it is thus possible to reduce the semi-finished product structure Clipping time promotes the efficiency of packaging operation.
Detailed description of the invention
Fig. 1 be reduce according to the present invention the semi-finished product structure of package substrate warpage a preferred embodiment it is positive one vertical Body figure.
Fig. 2 is the one vertical of the back side for the preferred embodiment of semi-finished product structure for reducing package substrate warpage according to the present invention Body figure.
Fig. 3 is a cross-sectional view of the III-III cutting line according to the 2nd figure.
Fig. 4 is the flow chart for reducing a preferred embodiment of method for package substrate warpage according to the present invention.
Symbol description
101 semiconductor chip, 102 packing colloid
2 package substrate, 21 package surface
211 precut 212 crystalline setting areas of road
201 first side, 202 second side
203 third side, 3 first positioning round orifice
4 second positioning round orifice 5 insulation adhesive layer
51 first grooving, 52 second grooving
S201 purchases step S202 encapsulation step
S203 positioning step S204 substrate screed step
S205 is cut by laser step S206 cleaning.
Specific embodiment
In order to which above-mentioned and other purposes of the invention, feature, advantage can be clearer and more comprehensible, hereafter by spy lift the present invention compared with Good embodiment, and cooperate institute's accompanying drawings, it is described in detail below.Furthermore the direction term that the present invention is previously mentioned, such as above and below, Top, bottom, front, rear, left and right, inside and outside, side, surrounding, center, level, transverse direction, vertically, longitudinally, axial direction, radial direction, top layer or Lowest level etc. is only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, and It is non-to limit the present invention.
It please refers to shown in the 1st and 2 figures, reduce the semi-finished product structure of package substrate warpage for the present invention one preferably implements Example, wherein the semi-finished product structure is sealing (molding) program by encapsulation procedure and is provided with multiple semiconductor chips 101, and each semiconductor chip 101 is coated with a packing colloid 102 (in order to clearly show that it is wherein single that the 1st figure is only painted 102 part of semiconductor chip 101 and packing colloid that one packaging structure is included).In the present embodiment, the reduction encapsulation The semi-finished product structure of substrate warp includes that a package substrate 2, multiple first positioning round orifice 3, multiple second positioning round orifice 4 and one are exhausted Edge adhesive layer 5.The present invention will be in detail structure, assembled relation and its operation principles that each component is detailed below.
It is continuous that the package substrate 2 is the substrate strip (substrate strip) of a strip referring to shown in the 1st and 2 figures, It has a package surface 21, wherein the package surface 21 is formed with multiple precut roads 211 and multiple crystalline setting areas 212, institute It states precut road 211 to be staggered vertically, the crystalline setting area 212 is located between the precut road 211, described to set Crystalline region 212 is respectively used for setting the semiconductor chip 101, and each semiconductor chip 101 is by corresponding packing colloid 102 It is coated.In the present invention, before completing laser cutting, the precut road 211 all simply means to a reserved strip cutting sky Between, it is not yet actually cut at this time.
Shown in the 1st and 2 figures of continuous reference, first positioning round orifice 3 arranges opposite one for being formed in the package substrate 2 First side 201 and a second side 202, wherein being located at the first side 201 of the package substrate 2 and first positioning of second side 202 Circular hole 3 corresponds to each other.In the present embodiment, first side 201 and second side 202 are respectively formed there are three the first setting circle Hole 3.
Shown in the 1st and 2 figures of continuous reference, second positioning round orifice 4 arranges opposite one for being formed in the package substrate 2 Third side 203 and one the 4th side 204, wherein being located at the second positioning of the third side 203 and the 4th side 204 of the package substrate 2 Circular hole 4 corresponds to each other.In the present embodiment, the third side 203 and the 4th side 204 are respectively formed with seven the second setting circles Hole 4.
It is noted that first positioning round orifice 3 and the second positioning round orifice 4 are for positioning datum point, wherein each envelope The encapsulation type of dress substrate 2 has the relative position corresponding to positioning round orifice.Using location hole and it can match in the present embodiment The mode for closing Mapping figure, to position the position in each precut road 211.
It is continuous referring to shown in the 1st and 2 figures, the insulation adhesive layer 5 be formed in via a dies with epoxy compound plastic injected die described in In the package surface 21 of package substrate 2, wherein the main material of the insulator seal glue-line 5 is heat cured epoxy resin (epoxy), a upper surface of the insulation adhesive layer 5 is formed at least three the first groovings 51 and at least three via laser cutting The second grooving of item 52, first grooving 51 respectively corresponds first positioning round orifice 3, and horizontal cross arranges from left to right, and institute It states the second grooving 52 and respectively corresponds second positioning round orifice 4 vertical longitudinal arrangement from top to bottom.In the present embodiment, described exhausted Edge adhesive layer 5 is for example formed with three the first groovings 51 and seven the second groovings 52, wherein first grooving 51 and described the Two groovings 52 intersect vertically.
Illustrate, the determinant for cutting and crossing item number of first grooving 51 and the second grooving 52, depend on pair In the specification of warpage of packaging assembly (Warpage), such as: if two semiconductor chips in interval can be used in 3mm or less 1mm or more The mode of 101 (5X5mm) draws 3 ordinates, is spaced four semiconductor chips 101 and draws 7 horizontal lines.If it is required that in 1mm hereinafter, vertical To laterally all being crossed using being spaced two semiconductor chips 101, if the requirement of flatness is higher, first grooving 51 and the Two groovings 52 to cut and cross item number more.
In the present invention, the quantity of first grooving 51 usually need to only be set to considerably less than same direction (water It is flat laterally) the corresponding quantity in the precut road 211 of arrangement;The quantity of second grooving 52 also need to only be set to obviously few In the corresponding quantity in the precut road 211 of same direction (vertical longitudinal) arrangement, the envelope can be so reduced Fill the warpage situation of substrate 2.However, in other embodiments, in order to more can reduce the warpage situation of the package substrate 2, The quantity of first grooving 51 and the second grooving 52 can also increase to the precut road 211 of same direction arrangement Corresponding quantity, so make first grooving 51 and the second grooving 52 respectively with the complete corresponding row in the precut road 211 Column.Furthermore by be cut by laser the width of first grooving 51 and the second grooving 52 formed also need to be set to be respectively smaller than and The width in the precut road 211 of its same direction arrangement, to avoid influencing finally to carry out machinery along the precut road 211 (such as grinding wheel) cuts 102 face shaping of packing colloid of isolated post-job single packaging structure.In addition, first grooving 51 And second the depth of grooving 52 only need to be set smaller than the thickness of the insulation adhesive layer 5, and preferably set described first The depth of grooving 51 and the second grooving 52 so drops enough between the 50% to 100% of the thickness of the insulation adhesive layer 5 The warpage situation of the low package substrate 2.
By above-mentioned design, by the insulation adhesive layer 5 on the package substrate 2 of the semi-finished product structure to be cut by laser out First grooving 51 is destroyed the package substrate 2 in the stress in 202 direction of the first side 201 and second side, thus reduces In addition the package substrate 2 is cut with second grooving 52 in the warping phenomenon in 202 direction of the first side 201 and second side again, It is destroyed the package substrate 2 in the stress in 204 direction of third side 203 and the 4th side, thus reduces the package substrate 2 and exist The warping phenomenon in 204 direction of third side 203 and the 4th side.Simultaneously as first grooving 51 and the second grooving 52 of pre-cut The duct in the corresponding precut road 211 is formed in the insulation adhesive layer 5, makes the package substrate 2 between multiple packaging plastics The sealing thickness of cutting path between body 102 is thinning, thus can also reduce the machine cuts cutting of the semi-finished product structure Time promotes the efficiency of packaging operation.
It please refers to Fig. 3 and cooperates shown in Fig. 1 and Fig. 2, one for the method for present invention reduction package substrate warpage is preferably real Example is applied, is and to form the semi-finished product structure of above-mentioned reduction package substrate warpage for replacing general packaging operation, wherein described The method for reducing package substrate warpage purchases step S201, an encapsulation step S202, a positioning step S203, a substrate comprising one Screed step S204, an a laser cutting step S205 and cleaning S206.The present invention will be explained in that steps are as follows.
Continue refering to Fig. 3 and cooperate shown in Fig. 1 and Fig. 2, is purchased in step S201 described, be to provide a package substrate 2, institute Package substrate 2 is stated with a package surface 21, wherein the package surface 21 is formed with multiple precut roads 211 and multiple sets crystalline substance Area 212, the precut road 211 are staggered vertically, the crystalline setting area 212 be located at the precut road 211 it Between, in addition, opposite one first side 201 and a second side 202 of the package substrate 2 is formed with multiple first positioning round orifice 3, And an opposite third side 203 and one the 4th side 204 for the package substrate 2 is formed with multiple second positioning round orifice 4.
Continue refering to Fig. 3 and cooperate shown in Fig. 1 and Fig. 2, in the encapsulation step S202, the encapsulation step is will be multiple Semiconductor chip 101 is separately positioned on the crystalline setting area 212, and forms an insulation adhesive layer via a dies with epoxy compound plastic injected die On the 5 cladding semiconductor chips 101, wherein the insulator seal glue-line 5 is multiple packing colloids 102 and the precut road One assembly of 211 sealing part.Furthermore, it is understood that predefining on the package substrate 2 has multiple crystalline setting areas 212;Then, Each semiconductor chip 101 is fixed on the upper surface of crystalline setting area 212 via glutinous brilliant (die attach) operation, chip and each It is to be formed electrically to connect through bonding wire (wire bond) or the electrical connection module (such as chip-covered boss) of preforming between weld pad It connects;Then, the package substrate 2 is clamped using a pair of upper and lower dies with epoxy compound, it will be in molten condition in the way of plastic injected die 102 raw material of packing colloid (predominantly heat cured epoxy resin) is injected into the die cavity of the mold, to form the insulation The cladding of adhesive layer 5 is located at the semiconductor chip 101 of the package surface 21 of the package substrate 2, to its cooling forming to complete State sealing (molding) program of chip encapsulating manufacturing procedure.
Continue refering to Fig. 3 and cooperate shown in Fig. 1 and Fig. 2, in the positioning step S203, first moves the package substrate 2 It moves to a predetermined position, and the package surface 21 for making the package substrate 2 is upward, shoots followed by a video camera (not being painted) The image of first positioning round orifice 3 and second positioning round orifice 4, and according to first positioning round orifice 3 and described The position of two positioning round orifice 4 carries out the positioning of the package substrate 2, such as orients first positioning round orifice 3 and described The X-axis of two positioning round orifice 4 and the two-dimensional position of Y-axis, then, when the positioning of the package substrate 2 is completed, through a processor (not being painted) loads the location parameter of the semiconductor chip 101, to as in the laser cutting step S205 to described The benchmark that insulation adhesive layer 5 is cut and crossed.
Continue refering to Fig. 3 and cooperate shown in Fig. 1 and Fig. 2, in the substrate screed step S204, to the package substrate 2 Positioning after, the package surface 21 or a lower surface for attracting the package substrate 2 are attached using multiple suction nozzles (not being painted), with The package substrate 2 is set to be maintained at a leveling state.
Continue refering to Fig. 3 and cooperate shown in Fig. 1 and Fig. 2, is to utilize a laser aid in the laser cutting step S205 (not being painted) cuts and crosses the insulation adhesive layer 5 in the package surface 21 for being formed in the package substrate 2, makes institute The surface for stating insulation adhesive layer 5 is formed at least three the first groovings 51 and at least three the second groovings 52.In the present embodiment, The insulation adhesive layer 5 is formed with three the first grooving of horizontal cross 51 and seven from top to bottom vertical longitudinal second from left to right Grooving 52, wherein the width of first grooving 51 and second grooving 52 is set smaller than the precut road 211 Width, and first grooving 51 intersects vertically with second grooving 52.In other embodiments, in order to more can reduce The quantity of the warpage situation of the package substrate 2, first grooving 51 and the second grooving 52 can also increase to it is described pre- The corresponding quantity of Cutting Road 211, and then keep first grooving 51 and the second grooving 52 opposite with the precut road 211 respectively It should arrange.Since first grooving 51 and the second grooving 52 are first groovings 51 and by being cut by laser Clast all is burnt with what the laser burn micro-structure and residual formed after laser cutting was formed in the groove of two groovings 52, is changed One inner surface of the groove of Yan Zhi, first grooving 51 and the second grooving 52 is not substantially flat, but has a roughness The roughness of remaining part of upper surface of the significantly greater than described insulation adhesive layer 5, this is to be cut by laser to form the obvious of groove Feature.
Continue refering to Fig. 3 and cooperate shown in Fig. 1 and Fig. 2, cleaning step is additionally comprised after the laser cutting step S205 Rapid S206, in the cleaning S206, the present invention be using a dust exhaust apparatus (not being painted) to first grooving 51 and Second grooving 52 is cleaned, furthermore, it is understood that rolling the envelope of the package substrate 2 using an idler wheel of the dust exhaust apparatus Fill surface 21, make in first grooving 51 and the second grooving 52 because laser cutting after residual formed burn clast by the rolling Wheel is inhaled glutinous and reaches clean effect.
After the laser cutting step S205 and cleaning S206, the package substrate 2 of the semi-finished product structure can To be further transported to other Working positions, to carry out mechanical (such as grinding wheel) cutting, to be carried out along the precut road 211 Practical cutting, wherein 211 some of precut road is mutually overlapped with the position of first grooving 51 and the second grooving 52. After machine cuts, can cut off the unnecessary package substrate 2 rim charge and the corresponding substrate in the precut road 211 and Adhesive material, thus it is isolated at multiple semiconductor packaging structures (finished product), respectively there is semiconductor chip 101, packing colloid 102 and one fritter be similar to the substrate of 212 size of crystalline setting area.
As described above, the insulation adhesive layer 5 on the package substrate 2 of the semi-finished product structure is cut with first grooving 51, it is destroyed the package substrate 2 in the stress in 202 direction of the first side 201 and second side, thus reduce the package substrate 2 202 direction of the first side 201 and second side warping phenomenon, be in addition cut with second grooving 52 again, make the encapsulation base Stress of the plate 2 in 204 direction of third side 203 and the 4th side is destroyed, thus reduce the package substrate 2 in third side 203 and The warping phenomenon in 204 direction of the 4th side.Simultaneously as first grooving 51 and the second grooving 52 of pre-cut are in the insulator seal Glue-line 5 forms the duct in the corresponding precut road 211, cuts the package substrate 2 in the subsequent multiple packing colloids 102 of progress The thickness for cutting path is thinning, it is thus possible to which the clipping time for reducing the semi-finished product structure promotes the efficiency of packaging operation.
Although the present invention is disclosed with preferred embodiment, so it is not intended to limiting the invention, any the art people Member, without departing from the spirit and scope of the present invention, when can make it is various change and modification, therefore protection scope of the present invention when view Subject to appended claims institute defender.

Claims (10)

1. a kind of method for reducing package substrate warpage, which is characterized in that include step:
One purchases step, provides a package substrate, the package substrate has a package surface, wherein the package surface is formed Have: multiple precut roads, arrangement interlaced with each other;And multiple crystalline setting areas, it is located between the precut road;
Multiple chips are separately positioned on the crystalline setting area, and form a packing colloid and coat the chip by one encapsulation step, are made The package surface forms an insulation adhesive layer;And
One laser cutting step, cuts and crosses the insulation adhesive layer, and is formed at least three the first groovings.
2. the method according to claim 1 for reducing package substrate warpage, which is characterized in that it is purchased in step described, Opposite one first side and a second side of the package substrate is formed with multiple first positioning round orifice, the first grooving difference The corresponding first positioning round orifice arrangement.
3. the method according to claim 2 for reducing package substrate warpage, which is characterized in that after the encapsulation step And a positioning step is additionally comprised before the laser cutting step, to shoot first positioning round orifice using a video camera Position and the positioning for carrying out the package substrate.
4. the method according to claim 2 for reducing package substrate warpage, which is characterized in that in the positioning step, When the positioning of the package substrate is completed, the location parameter of the chip is loaded through a processor, to swash as described The benchmark that the insulation adhesive layer is cut and crossed in light cutting step.
5. the method according to claim 3 for reducing package substrate warpage, which is characterized in that in the laser cutting step A substrate screed step is additionally comprised before and after the positioning step, to attract the envelope of the package substrate using multiple suction nozzles Surface or a lower surface are filled, the package substrate is made to be maintained at a leveling state.
6. the method according to claim 1 for reducing package substrate warpage, which is characterized in that in the laser cutting step A cleaning is additionally comprised later, and first grooving is cleaned using a dust exhaust apparatus.
7. it is a kind of reduce package substrate warpage semi-finished product structure, characterized by comprising:
One package substrate has a package surface, wherein the package surface is formed with: multiple precut roads, row interlaced with each other Column;And multiple crystalline setting areas, it is located between the precut road;
Multiple first positioning round orifice are formed in opposite one first side and a second side of the package substrate, wherein being located at institute First positioning round orifice of the first side and second side of stating package substrate corresponds to each other;And
One insulation adhesive layer, is formed in the package surface of the package substrate, wherein the insulator seal glue-line is formed at least Three the first groovings respectively correspond the first positioning round orifice arrangement.
8. the semi-finished product structure according to claim 7 for reducing package substrate warpage, which is characterized in that the reduction encapsulation The structure of substrate warp additionally comprises multiple second positioning round orifice, is formed in an opposite third side and one for the package substrate Four sides, wherein the second positioning round orifice of the third side and the 4th side that are located at the package substrate corresponds to each other.
9. the semi-finished product structure according to claim 8 for reducing package substrate warpage, which is characterized in that the insulation sealing Layer is separately formed at least three the second groovings, respectively corresponds the second positioning round orifice arrangement, and first grooving and institute State the intersection of the second grooving.
10. the semi-finished product structure according to claim 9 for reducing package substrate warpage, which is characterized in that described first cuts The arrangement corresponding with the precut road respectively of slot and the second grooving.
CN201811026567.0A 2017-11-14 2018-09-04 Reduce the method and semi-finished product structure of package substrate warpage Pending CN109786269A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112743303A (en) * 2020-12-30 2021-05-04 无锡市欧丰电梯配件有限公司 Front-edge panel precision cutting process
CN117352399A (en) * 2023-09-28 2024-01-05 昆山国显光电有限公司 Packaging method, chip packaging structure and electronic equipment

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1162194A (en) * 1996-02-26 1997-10-15 摩托罗拉公司 Method for mfg. electronic element with organic substrate
CN1171299C (en) * 1998-07-31 2004-10-13 精工爱普生株式会社 Semiconductor device and manufacture thereof, substrate, electric circuit board and electronic device for manufacturing same
CN1641849A (en) * 2004-01-09 2005-07-20 威宇科技测试封装有限公司 Method for manufacturing carrying-plate for packaging flat plastic-sealed ball grid array and its carrying plate
CN2785134Y (en) * 2004-12-03 2006-05-31 威宇科技测试封装有限公司 Tooth-shaped basic batten for semiconductor ball grid array package
CN1893127A (en) * 2005-07-04 2007-01-10 株式会社元素电子 Light emitting device
CN101243734A (en) * 2005-06-24 2008-08-13 3M创新有限公司 Printed wiring board manufacturing process
CN101859736A (en) * 2009-04-07 2010-10-13 日月光半导体制造股份有限公司 Semiconductor packaging semi-finished product and semiconductor packaging process
CN102130072A (en) * 2010-01-15 2011-07-20 矽品精密工业股份有限公司 Bearing plate and manufacturing method thereof
CN102194715A (en) * 2010-03-16 2011-09-21 南亚电路板股份有限公司 Packaging substrate module and strip-shaped packaging substrate
CN102244065A (en) * 2010-05-12 2011-11-16 矽品精密工业股份有限公司 Strip package substrate and alignment structure thereof
CN102315202A (en) * 2010-07-02 2012-01-11 欣兴电子股份有限公司 Substrate strip with circuit and making method for substrate strip
CN102456582A (en) * 2010-10-26 2012-05-16 联钢技术国际有限公司 Technology for manufacturing molded lead frame
CN102509722A (en) * 2012-01-06 2012-06-20 日月光半导体制造股份有限公司 Semiconductor encapsulating element and manufacture method thereof
CN202394860U (en) * 2011-12-28 2012-08-22 日月光半导体制造股份有限公司 Packaging base plate strip
CN205029958U (en) * 2015-09-25 2016-02-10 广州兴森快捷电路科技有限公司 V -CUT prevents slow -witted graphic structure
CN107210270A (en) * 2015-01-27 2017-09-26 三菱电机株式会社 Semiconductor module

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7944034B2 (en) * 2007-06-22 2011-05-17 Texas Instruments Incorporated Array molded package-on-package having redistribution lines
TWI539563B (en) * 2012-07-26 2016-06-21 長華電材股份有限公司 Process of encapsulating non-rigid substrate and the substrate
TWI533421B (en) * 2013-06-14 2016-05-11 日月光半導體製造股份有限公司 Semiconductor package structure and semiconductor process
US10153237B2 (en) * 2016-03-21 2018-12-11 Xintec Inc. Chip package and method for forming the same
US9721923B1 (en) * 2016-04-14 2017-08-01 Micron Technology, Inc. Semiconductor package with multiple coplanar interposers

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1162194A (en) * 1996-02-26 1997-10-15 摩托罗拉公司 Method for mfg. electronic element with organic substrate
CN1171299C (en) * 1998-07-31 2004-10-13 精工爱普生株式会社 Semiconductor device and manufacture thereof, substrate, electric circuit board and electronic device for manufacturing same
CN1641849A (en) * 2004-01-09 2005-07-20 威宇科技测试封装有限公司 Method for manufacturing carrying-plate for packaging flat plastic-sealed ball grid array and its carrying plate
CN2785134Y (en) * 2004-12-03 2006-05-31 威宇科技测试封装有限公司 Tooth-shaped basic batten for semiconductor ball grid array package
CN101243734A (en) * 2005-06-24 2008-08-13 3M创新有限公司 Printed wiring board manufacturing process
CN1893127A (en) * 2005-07-04 2007-01-10 株式会社元素电子 Light emitting device
CN101859736A (en) * 2009-04-07 2010-10-13 日月光半导体制造股份有限公司 Semiconductor packaging semi-finished product and semiconductor packaging process
CN102130072A (en) * 2010-01-15 2011-07-20 矽品精密工业股份有限公司 Bearing plate and manufacturing method thereof
CN102194715A (en) * 2010-03-16 2011-09-21 南亚电路板股份有限公司 Packaging substrate module and strip-shaped packaging substrate
CN102244065A (en) * 2010-05-12 2011-11-16 矽品精密工业股份有限公司 Strip package substrate and alignment structure thereof
CN102315202A (en) * 2010-07-02 2012-01-11 欣兴电子股份有限公司 Substrate strip with circuit and making method for substrate strip
CN102456582A (en) * 2010-10-26 2012-05-16 联钢技术国际有限公司 Technology for manufacturing molded lead frame
CN202394860U (en) * 2011-12-28 2012-08-22 日月光半导体制造股份有限公司 Packaging base plate strip
CN102509722A (en) * 2012-01-06 2012-06-20 日月光半导体制造股份有限公司 Semiconductor encapsulating element and manufacture method thereof
CN107210270A (en) * 2015-01-27 2017-09-26 三菱电机株式会社 Semiconductor module
CN205029958U (en) * 2015-09-25 2016-02-10 广州兴森快捷电路科技有限公司 V -CUT prevents slow -witted graphic structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112743303A (en) * 2020-12-30 2021-05-04 无锡市欧丰电梯配件有限公司 Front-edge panel precision cutting process
CN117352399A (en) * 2023-09-28 2024-01-05 昆山国显光电有限公司 Packaging method, chip packaging structure and electronic equipment

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