TWM523189U - Lead frame performing body and lead frame packaging structure - Google Patents

Lead frame performing body and lead frame packaging structure Download PDF

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Publication number
TWM523189U
TWM523189U TW105203479U TW105203479U TWM523189U TW M523189 U TWM523189 U TW M523189U TW 105203479 U TW105203479 U TW 105203479U TW 105203479 U TW105203479 U TW 105203479U TW M523189 U TWM523189 U TW M523189U
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Taiwan
Prior art keywords
lead frame
wafer
leadframe
preform
wafer holder
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TW105203479U
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Chinese (zh)
Inventor
Jia-Neng Huang
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Chang Wah Technology Co Ltd
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Publication date
Application filed by Chang Wah Technology Co Ltd filed Critical Chang Wah Technology Co Ltd
Priority to TW105203479U priority Critical patent/TWM523189U/en
Publication of TWM523189U publication Critical patent/TWM523189U/en
Priority to JP2017001035U priority patent/JP3210520U/en
Priority to US15/456,019 priority patent/US10475730B2/en
Priority to KR2020170001183U priority patent/KR200489287Y1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

導線架預成形體及導線架封裝結構Lead frame preform and lead frame package structure

本新型是有關於一種導線架預成形體，及導線架封裝結構，特別是指一種可用於獨立電性晶片封裝的導線架預成形體，及導線架封裝結構。The present invention relates to a leadframe preform, and a leadframe package structure, and more particularly to a leadframe preform that can be used for an independent electrical chip package, and a leadframe package structure.

四方扁平無外引腳(QFN，quad flat no-lead)封裝結構，因為沒有向外延伸的引腳，因此，可大幅減小封裝尺寸。此外，因為QFN具有較短的訊號傳遞路徑及較快的訊號傳遞速度，因此，也更適用於一般高速及高頻的電子產品。The quad flat no-lead (QFN) package structure greatly reduces the package size because there are no outwardly extending pins. In addition, because QFN has a shorter signal transmission path and faster signal transmission speed, it is also more suitable for general high-speed and high-frequency electronic products.

參閱圖1，圖1是一般習知的QFN封裝結構的其中一個導線架封裝單元。該導線架封裝單元包含界定出一空間的一連接支架11、一位於該空間中的晶片座12、多條自該連接支架11朝向該晶片座12延伸的引腳13、一設置於該晶片座12頂面的晶片14多條分別電連接該晶片14與該等引腳的導線15，及用於支撐該晶片座12的支撐部16。Referring to FIG. 1, FIG. 1 is one of the leadframe package units of a conventional QFN package structure. The lead frame package unit includes a connection bracket 11 defining a space, a wafer holder 12 located in the space, a plurality of pins 13 extending from the connection bracket 11 toward the wafer holder 12, and a chip holder disposed on the wafer holder A plurality of 12 top wafers 14 electrically connect the wafer 14 and the leads 15 of the pins, respectively, and a support portion 16 for supporting the wafer holder 12.

然而，當晶片封裝完成欲進行每個導線架單元的切割分離時，由於需沿著由金屬(銅)構成的該等引腳13進行切割(如圖中假想線所示)，因此，切割的刀具也容易受損。此外，由於一般導線架封裝單元僅具有一個晶片座12，因此，每一個導線架封裝單元僅能封裝單一個(單一種)晶片，當要製備具有不同功能的晶片或是多個晶片時，只能利用不同的導線架封裝單元進行不同晶片的封裝。However, when the wafer package is completed to perform the cutting separation of each lead frame unit, since the cutting is performed along the pins 13 made of metal (copper) (as shown by the imaginary line in the figure), the cut is performed. The tool is also easily damaged. In addition, since the general lead frame package unit has only one wafer holder 12, each lead frame package unit can only package a single (single) wafer. When a wafer having different functions or a plurality of wafers is to be prepared, only Different wafer package units can be used to package different wafers.

因此，本新型之目的，即在提供一種具有多個彼此電性獨立的導線架單元的導線架預成形體。Accordingly, it is an object of the present invention to provide a leadframe preform having a plurality of leadframe units that are electrically independent of one another.

於是，本新型該導線架預成形體，包括多個彼此電性獨立且成陣列排列的導線架單元。該每一個導線架單元包含一成型膠層、至少一晶片座，及多條引腳。Thus, the lead frame preform of the present invention comprises a plurality of lead frame units electrically and independently arranged in an array. Each of the leadframe units includes a molding layer, at least one wafer holder, and a plurality of pins.

該成型膠層由絕緣高分子材料構成，具有一中心區，及一環圍該中心區的切割道。The molding layer is composed of an insulating polymer material, has a central area, and a cutting path surrounding the central area.

該至少一晶片座由金屬材料構成，位於該成型膠層的該中心區內，該晶片座具有彼此反向的一頂面及一底面，且該頂面及底面會分別自該成型膠層反向的兩個表面裸露。The at least one wafer holder is made of a metal material, and is located in the central region of the molding adhesive layer. The wafer holder has a top surface and a bottom surface opposite to each other, and the top surface and the bottom surface are respectively reversed from the molding adhesive layer. The two faces are bare.

該等引腳由與該晶片座相同的金屬材料構成，彼此各自獨立地自該切割道的頂面朝向該等晶片座延伸，並與該晶片座呈一間距。The pins are formed of the same metal material as the wafer holder, independently extending from the top surface of the dicing street toward the wafer holders and spaced apart from the wafer holder.

此外，本新型的另一目的，在於提供一種利用該導線架預成形體封裝而得的導線架封裝結構。In addition, another object of the present invention is to provide a lead frame package structure obtained by using the lead frame preform package.

於是，該導線架封裝結構包括一個如前所述的導線架預成形體、多個晶片，及多條導線。該每一個晶片為設置於該其中一個晶片座上，並藉由至少部分的該等導線與該等引腳電連接，且該等晶片彼此為電性獨立。Thus, the leadframe package structure includes a leadframe preform, a plurality of wafers, and a plurality of conductors as previously described. Each of the wafers is disposed on one of the wafer holders and is electrically connected to the pins by at least a portion of the wires, and the wafers are electrically independent of each other.

本新型之功效在於：利用導線架預成形體的結構設計，因此，得以讓該導線架預成形體的每一個導線架單元之間彼此不須由金屬連接，且為電性獨立，因此，當利用該導線架預成形體形成封裝結構後，不僅切割前即可對每一個晶片獨立進行線上測試，且更易於切割而得到各自獨立的導線架單元。The utility model has the advantages of: utilizing the structural design of the lead frame preform, so that each lead frame unit of the lead frame preform can be connected to each other without metal, and is electrically independent, therefore, when After the leadframe preform is used to form the package structure, each wafer can be independently tested on-line before cutting, and it is easier to cut to obtain separate leadframe units.

參閱圖2、3，圖2是本新型之導線架封裝結構的一實施例的俯視示意圖，圖3是沿圖2中之III-III割面線的剖視圖。2 and 3, FIG. 2 is a top plan view of an embodiment of the lead frame package structure of the present invention, and FIG. 3 is a cross-sectional view taken along line III-III of FIG.

該導線架封裝結構包含一個導線架預成形體200A、多個晶片3，及多條導線4。The leadframe package structure includes a leadframe preform 200A, a plurality of wafers 3, and a plurality of wires 4.

該導線架預成形體200A包括多個彼此電性獨立且成陣列排列的導線架單元2A，且該每一個導線架單元2A包含一成型膠層21、一晶片座22，及多條引腳23。The leadframe preform 200A includes a plurality of leadframe units 2A electrically and independently arranged in an array, and each of the leadframe units 2A includes a molding layer 21, a wafer holder 22, and a plurality of leads 23 .

該成型膠層21由絕緣高分子材料構成，具有一中心區211，及一環圍該中心區211的切割道212。The molding layer 21 is made of an insulating polymer material, and has a central portion 211 and a cutting path 212 surrounding the central portion 211.

該晶片座22由金屬材料構成，位於該成型膠層21的該中心區211內。該晶片座22具有彼此反向的一頂面221及一底面222，且該頂面221及底面222會分別自該成型膠層21反向的兩個表面裸露。The wafer holder 22 is made of a metal material and is located in the central region 211 of the molding layer 21. The wafer holder 22 has a top surface 221 and a bottom surface 222 opposite to each other, and the top surface 221 and the bottom surface 222 are respectively exposed from the opposite surfaces of the molding layer 21.

該等引腳23由與該晶片座22相同的金屬材料構成，彼此各自獨立地自該切割道212的頂面朝向該等晶片座22延伸，並與該晶片座22呈一間距。The pins 23 are formed of the same metal material as the wafer holder 22, and extend independently from the top surface of the dicing street 212 toward the wafer holders 22, and spaced apart from the wafer holder 22.

該等晶片3分別對應形成於該等導線架單元2的該等晶片座22的頂面221，且該每一個晶片3藉由多數導線4與該等引腳23電連接。The wafers 3 correspond to the top surfaces 221 of the wafer holders 22 formed on the lead frame units 2, and each of the wafers 3 is electrically connected to the pins 23 by a plurality of wires 4.

由於該導線架封裝結構的該每一個導線架單元2A彼此均為電性獨立，因此經封裝後的每一個晶片3也可具有各自獨立的電性，而在封裝後切割前即可分別對該等晶片3進行板上(on board)電性測試。此外，由於本新型該導線架預成形體200A已事先將位於切割位置(如圖2虛線所示)的金屬材料蝕刻移除，因此，當要將該導線架封裝結構進行各個導線架單元2A的切割時，僅需要切割高分子材料，而可進一步減少切割刀具的損耗。Since each of the lead frame units 2A of the lead frame package structure is electrically independent from each other, each of the packaged wafers 3 can also have independent electrical properties, and can be separately used before being packaged and cut. The wafer 3 is subjected to an on board electrical test. In addition, since the leadframe preform 200A of the present invention has previously removed the metal material at the cutting position (shown by a broken line in FIG. 2), the leadframe package structure is to be subjected to the respective leadframe unit 2A. When cutting, only the polymer material needs to be cut, and the loss of the cutting tool can be further reduced.

茲將前述該導線架封裝結構的該實施例的製作方法說明如下：The manufacturing method of the embodiment of the lead frame package structure described above is described as follows:

配合參閱圖4、5，詳細的說，前述該導線架預成形體是提供一可導電的材料，例如銅系合金或鐵鎳合金等材料構成的基片100。定義多條縱向及橫向排列且彼此相交的第一、二分隔島101、102，且兩兩相鄰且彼此相交的橫向及縱向排列的第一、二分隔島101、102共同定義出後續經蝕刻移除後預形成之多數空間301。Referring to Figures 4 and 5 in detail, the leadframe preform is a substrate 100 constructed of a conductive material such as a copper alloy or an iron-nickel alloy. Defining a plurality of first and second islands 101, 102 arranged longitudinally and laterally and intersecting each other, and the first and second islands 101, 102 arranged adjacent to each other and intersecting each other in the lateral direction and the longitudinal direction define a subsequent etching Most of the space 301 that is pre-formed after removal.

進行第一次蝕刻，將該基片100不必要的部分蝕刻移除，令該基片100形成一個導線架201A。A first etching is performed to remove unnecessary portions of the substrate 100, so that the substrate 100 forms a lead frame 201A.

該導線架201A包括一具有多條縱向及橫向排列且彼此間隔的連接支架300，及多個導線架單元2A。其中，該等連接支架300即位於該等第一、二分隔島101、102所定義之位置，兩兩相鄰且彼此相交的橫向及縱向排列的連接支架300共同界定出一個空間301，且該等導線架單元2A即分別對應形成於該等空間301。要說明的是，經蝕刻後形成的該等連接支架300的形狀及細部結構為本技術領域者所熟知並視實際需求及設計而有所不同，且非為本新型之結構重點，因此，於圖式中僅是一簡單示意圖，實際結構並不以此為限。The lead frame 201A includes a plurality of connecting brackets 300 arranged longitudinally and laterally and spaced apart from each other, and a plurality of lead frame units 2A. Wherein, the connecting brackets 300 are located at positions defined by the first and second partitioning islands 101, 102, and the laterally and longitudinally arranged connecting brackets 300 adjacent to each other and intersecting each other collectively define a space 301, and The lead frame units 2A are respectively formed corresponding to the spaces 301. It should be noted that the shape and the detailed structure of the connecting brackets 300 formed by etching are well known to those skilled in the art and vary according to actual needs and designs, and are not the structural focus of the present invention. The figure is only a simple schematic diagram, and the actual structure is not limited to this.

該每一個導線架單元2A具有一個位於該空間301的晶片座22、多條自該等連接支架300朝向該晶片座22延伸，並與該晶片座22呈一間距的引腳23，及分別自該晶片座22的4個對角延伸至與相鄰的該等連接支架300連接的支撐部24。Each of the lead frame units 2A has a wafer holder 22 located in the space 301, a plurality of pins 23 extending from the connection brackets 300 toward the wafer holder 22, and spaced apart from the wafer holder 22, and respectively The four diagonals of the wafer holder 22 extend to the support portion 24 that is connected to the adjacent connection brackets 300.

參閱圖5，圖5(a)為圖4所示之該導線架201A沿V-V割面線的剖視示意圖。將前述經由蝕刻方式製得的該導線架201A夾設於一模具(圖未示)中，用模注方式灌入一成形膠，其中，該成形膠為選自一般絕緣封裝材料，如環氧樹脂等，讓該成形膠填滿該等連接支架300的空隙，以及該連接支架300與該等晶片座22之間的空隙，且不會覆蓋該等連接支架300、晶片座22、引腳23，及支撐部24的頂面，並令該成形膠固化形成該成形膠層21，即可得到一如圖5(b)所示的導線架預成形體半成品202A。Referring to FIG. 5, FIG. 5(a) is a cross-sectional view of the lead frame 201A shown in FIG. 4 along the line V-V. The lead frame 201A obtained by the etching method is sandwiched in a mold (not shown), and a molding glue is injected by molding, wherein the forming glue is selected from a general insulating packaging material such as epoxy. Resin or the like, the molding gel fills the gaps of the connecting brackets 300, and the gap between the connecting brackets 300 and the wafer holders 22, and does not cover the connecting brackets 300, the wafer holders 22, and the leads 23 And the top surface of the support portion 24, and the molding glue is solidified to form the molding layer 21, thereby obtaining a lead frame preform semi-finished product 202A as shown in FIG. 5(b).

接著，進行第二次蝕刻，將該導線架預成形體半成品202A的該等連接支架300蝕刻移除至令該等引腳23為各自獨立彼此不連接，並同時將該等支撐部24移除，即可得到一如圖5(c)所示的導線架預成形體200A。Then, a second etching is performed to etch the connection brackets 300 of the lead frame preform blank 202A so that the pins 23 are not connected to each other independently, and at the same time, the support portions 24 are removed. Thus, a lead frame preform 200A as shown in Fig. 5(c) is obtained.

最後，進行晶片封裝，將該等晶片3分別設置於該導線架預成形體200A的該等晶片座22的頂面221，接著利用打線製程，將每一個晶片3與對應的該等引腳23利用導線4電連接，即可得到如圖2所示之該導線架封裝結構。Finally, wafer encapsulation is performed, and the wafers 3 are respectively disposed on the top surface 221 of the wafer holders 22 of the leadframe preform 200A, and then each of the wafers 3 and the corresponding pins 23 are formed by a wire bonding process. By electrically connecting the wires 4, the lead frame package structure as shown in FIG. 2 can be obtained.

由於該導線架預成形體半成品202A已經藉由該成型膠層21固定，因此，可利用第二次蝕刻，將原本位於切割道的金屬(如圖5(a)、(b)虛線所示的連接支架300)及用於連接固定該晶片座22的支撐部24蝕刻移除，預先讓該等引腳23彼此電性獨立不連接。因此，經由第二次蝕刻後所得到的該導線架預成形體200A的該每一個導線架單元2A為各自電性獨立，故，可在封裝後切割前即對每一個晶片3進行板上(on board)電性測試，且切割時僅需要切割高分子材料(如圖5(c)位於引腳23兩側之箭頭所指處)，而可進一步減少切割刀具的損耗。Since the leadframe preform semi-finished product 202A has been fixed by the molding layer 21, the second etching can be used to place the metal originally located in the scribe line (as shown by the dashed lines in FIGS. 5(a) and (b). The connection bracket 300) and the support portion 24 for connecting and fixing the wafer holder 22 are etched and removed, and the pins 23 are electrically connected independently of each other in advance. Therefore, each of the lead frame units 2A of the lead frame preform 200A obtained after the second etching is electrically independent, so that each of the wafers 3 can be plated before the post-package cutting ( On board) electrical test, and only need to cut the polymer material when cutting (as shown by the arrow on both sides of the pin 23 in Figure 5 (c)), and further reduce the loss of the cutting tool.

配合參閱圖6~8，本發明導線架封裝結構的一第二實施例，其結構與該第一實施例大致相同，不同處在於第二實施例形成形成的導線架預成形體200B其中至少部分的導線架單元2B會具有多個各自獨立設置的晶片座22，且相鄰的兩個晶片座22之間具有一自該成型膠層21表面向下形成的溝槽26。圖6中是以該其中一個導線架單元2B具有三個晶片座22，且每一個晶片座22會設置一個晶片3為例。Referring to Figures 6-8, a second embodiment of the leadframe package structure of the present invention has substantially the same structure as the first embodiment, except that the leadframe preform 200B formed in the second embodiment is at least partially formed. The lead frame unit 2B has a plurality of wafer holders 22 which are independently disposed, and adjacent wafer holders 22 have a groove 26 formed downward from the surface of the molding layer 21. In Fig. 6, the one of the lead frame units 2B has three wafer holders 22, and each of the wafer holders 22 is provided with a wafer 3.

由於該等導線架單元2B之間彼此為電性獨立，且該導線架單元2B也可具有多個各自電性獨立的晶片座22，因此，封裝於該導線架單元2B的該等晶片3也可各自獨立地對外電聯接，而進一步實現於單一個該導線架單元2B內施行多晶片封裝的目的。Since the lead frame units 2B are electrically independent from each other, and the lead frame unit 2B can also have a plurality of electrically independent wafer holders 22, the wafers 3 packaged in the lead frame unit 2B are also The external electrical connection can be independently performed, and the purpose of performing multi-chip packaging in a single one of the lead frame units 2B is further realized.

前述該第二實施例的製作方法，大致與該第一實施例雷同，不同處在於該第二實施例於該第一次蝕刻及該第二次蝕刻形成的結構與該第一實施例有部分不同。The manufacturing method of the second embodiment is substantially the same as that of the first embodiment, except that the structure formed by the first etching and the second etching in the second embodiment is partially related to the first embodiment. different.

續參閱圖7，詳細的說，該第二實施例經過第一次蝕刻後形成的導線架201B的至少一個該導電架單元2B會如圖7所示，具有3個晶片座22，任相鄰的兩個晶片座22之間會具有一連接件25，且該等支撐部24是形成於相對遠離的兩個晶片座22的對角。Referring to FIG. 7 in detail, at least one of the conductive frame units 2B of the lead frame 201B formed by the first etching after the first etching will have three wafer holders 22 as shown in FIG. There will be a connector 25 between the wafer holders 22, and the support portions 24 are diagonally formed between the two wafer holders 22 that are relatively distant.

再參閱圖8，圖8(a)是圖7的該導線架單元2B沿VIII-VIII割面線的剖視示意圖，圖8(b)則是將該導線架201B夾設於一模具(圖未示)中，用模注方式形成該成形膠層21，而得到的一導線架預成形體半成品202B；最後將該導線架預成形體半成品202B進行第二次蝕刻，將該等連接支架300、該等支撐部24及該等連接件25移除，而得到一如圖8(c)所示的導線架預成形體200B。要說明的是，由於該等連接件25是於該成型膠層21形成後，才經由第二次蝕刻移除，因此，該成型膠層21於對應該等連接件25的位置即會形成該等溝槽26。最後再將該導線架預成形體200B進行晶片的打線封裝後，即可得到如圖6所示之導線架封裝結構。Referring to FIG. 8, FIG. 8(a) is a cross-sectional view of the lead frame unit 2B of FIG. 7 taken along the line VIII-VIII, and FIG. 8(b) is a view of the lead frame 201B sandwiched between the molds. In the unillustrated, the molding layer 21 is formed by molding, and a lead frame preform semi-finished product 202B is obtained. Finally, the lead frame preform blank 202B is etched a second time, and the connecting brackets 300 are connected. The support portions 24 and the connecting members 25 are removed to obtain a lead frame preform 200B as shown in Fig. 8(c). It is to be noted that since the connecting members 25 are removed after the molding layer 21 is formed, the molding layer 21 is formed at a position corresponding to the connecting member 25. The groove 26 is equal. Finally, after the lead frame preform 200B is subjected to wire bonding of the wafer, a lead frame package structure as shown in FIG. 6 can be obtained.

前述該第二實施例是以相鄰的二個晶片座22之間具有一條直線狀的連接件25為例，然實際實施時該連接件25的數量及形狀可視需求及設計而調整，而不限定為此形狀及數量。The second embodiment is exemplified by a linear connecting member 25 between two adjacent wafer holders 22. However, the number and shape of the connecting members 25 can be adjusted according to requirements and design. Limited to this shape and quantity.

此外，參閱圖9，要再說明的是，前述該第一、二實施例於該第一次蝕刻形成該等引腳23時，還可進一步控制不將該等引腳23鄰近該晶片座22下方的材料移除，讓形成的每一個引腳23均具有一引腳段231及一支撐段232，而可得到如圖9所示之引腳23結構。利用將每一個該引腳23製作成具有該支撐段232的支撐結構，由於該引腳段231有該支撐段232的支撐，而有較佳的支撐性，所以，當將該導線架201A、201B夾設於該模具時，該支撐段232可頂抵於該模具，有效支撐並固定該引腳段231，而避免於灌注成形膠，形成該導線架預成形體半成品202A、202B的過程中，該等引腳32位移或變形塌陷的問題。In addition, referring to FIG. 9 , it is to be noted that, when the first and second embodiments form the pins 23 , the first and second embodiments may further control that the pins 23 are not adjacent to the wafer holder 22 . The underlying material is removed, so that each of the formed pins 23 has a pin segment 231 and a support segment 232, and a pin 23 structure as shown in FIG. 9 can be obtained. By using each of the pins 23 to form a support structure having the support section 232, since the lead segment 231 has the support of the support section 232, and has better support, when the lead frame 201A, When the 201B is sandwiched between the molds, the support section 232 can abut against the mold to effectively support and fix the lead segments 231, and avoid the process of injecting the molding glue to form the lead frame preforms 202A, 202B. The pin 32 displacement or deformation collapse problem.

綜上所述，本新型利用該導線架預成形體200A、200B的結構設計，讓該導線架預成形體200A、200B的每一個導線架單元2A、2B之間彼此為電性獨立，因此，當利用該導線架預成形體200A、200B封裝得到該導線架封裝結構後，不僅切割前即可對位於該每一個導線架單元2A、2B的晶片3獨立進行電性測試，且更易於切割，而可避免切割刀具的耗損。此外，也可進一步於單一個導線架單元2B形成具有多個可用於獨立承載晶片3之晶片座22。因此，當利用該導線架預成形體200B進行晶片封裝時，還可將多個不同功能的晶片封裝在一個該導線架單元2B內各自獨立的晶片座22，之後再利用導線4將該等晶片3各自獨立對外電連接並封裝，而進一步實現於單一個導線架單元2B內施行多晶粒封裝的目的，故確實能達成本新型之目的。In summary, the present invention utilizes the structural design of the leadframe preforms 200A, 200B such that each leadframe unit 2A, 2B of the leadframe preforms 200A, 200B is electrically independent of each other, therefore, After the lead frame package structure is obtained by using the lead frame preforms 200A, 200B, the wafers 3 located on each of the lead frame units 2A, 2B can be electrically tested independently and cut more easily, not only before cutting. The wear of the cutting tool can be avoided. In addition, a plurality of wafer holders 22 that can be used to independently carry the wafer 3 can be further formed in a single leadframe unit 2B. Therefore, when the lead frame preform 200B is used for wafer packaging, a plurality of wafers having different functions can be packaged in a separate wafer holder 22 in the lead frame unit 2B, and then the wafers are processed by the wires 4. 3 Each of the independent external electrical connections and packaging, and further realizes the purpose of performing multi-die encapsulation in a single lead frame unit 2B, so the purpose of the present invention can be achieved.

惟以上所述者，僅為本新型之實施例而已，當不能以此限定本新型實施之範圍，凡是依本新型申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本新型專利涵蓋之範圍內。However, the above is only the embodiment of the present invention, and when it is not possible to limit the scope of the present invention, all the simple equivalent changes and modifications according to the scope of the patent application and the contents of the patent specification are still This new patent covers the scope.

200A、200B‧‧‧導線架預成形體
25‧‧‧連接件
2A、2B‧‧‧導線架單元
26‧‧‧溝槽
21‧‧‧成型膠層
3‧‧‧晶片
211‧‧‧中心區
4‧‧‧導線
212‧‧‧切割道
101‧‧‧第一分隔島
22‧‧‧晶片座
102‧‧‧第二分隔島
221‧‧‧頂面
100‧‧‧基片
222‧‧‧底面
201A、201B‧‧‧導線架
23‧‧‧引腳
202A、202B‧‧‧導線架預成形體半成品
231‧‧‧引腳段
300‧‧‧連接支架
232‧‧‧支撐段
301‧‧‧空間
24‧‧‧支撐部200A, 200B‧‧‧ lead frame preforms
25‧‧‧Connecting parts
2A, 2B‧‧‧ lead frame unit
26‧‧‧ trench
21‧‧‧Forming layer
3‧‧‧ wafer
211‧‧‧ Central District
4‧‧‧ wire
212‧‧‧ cutting road
101‧‧‧First Separation Island
22‧‧‧ Wafer holder
102‧‧‧Second Separation Island
221‧‧‧ top surface
100‧‧‧ substrates
222‧‧‧ bottom
201A, 201B‧‧‧ lead frame
23‧‧‧ Pin
202A, 202B‧‧‧ leadframe preforms semi-finished products
231‧‧‧ pin segment
300‧‧‧Connecting bracket
232‧‧‧Support section
301‧‧‧ Space
24‧‧‧Support

本新型之其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中： 圖1是習知的QFN封裝結構的導線架封裝單元的一示意圖； 圖2是本新型該導線架封裝結構的一第一實施例的一俯視示意圖； 圖3是圖2中沿III-III割面線的剖視示意圖； 圖4是該第一實施例的製作流程示意圖，說明經第一次蝕刻後得到的導線架201A的俯視示意圖； 圖5是圖4中沿V-V割面線的剖視示意圖，接續圖4說明該第一實施例的製作流程； 圖6是說明本新型該導線架封裝結構的一第二實施例的一俯視示意圖； 圖7是說明經第一次蝕刻後得到的該導線架201B的俯視示意圖； 圖8是圖7中沿VIII-VIII割面線的剖視示意圖，說明該第二實施例的製作流程； 圖9是說明本新型該導線架預成形體的引腳還具有支撐部的態樣。Other features and effects of the present invention will be apparent from the following description of the drawings, wherein: FIG. 1 is a schematic view of a lead frame package unit of a conventional QFN package structure; FIG. 2 is a lead frame of the present invention. FIG. 3 is a schematic cross-sectional view along the line III-III of FIG. 2; FIG. 4 is a schematic view showing the manufacturing process of the first embodiment, illustrating the first etching process. FIG. 5 is a cross-sectional view of the lead wire taken along line VV of FIG. 4, and FIG. 4 is a flow chart showing the manufacturing process of the first embodiment; FIG. 6 is a view showing the lead frame package structure of the present invention. A top view of a second embodiment of the present invention; FIG. 7 is a schematic plan view showing the lead frame 201B obtained after the first etching; FIG. 8 is a cross-sectional view taken along line VIII-VIII of FIG. The manufacturing process of the second embodiment; FIG. 9 is a view showing the aspect in which the lead of the lead frame preform of the present invention further has a support portion.

200A‧‧‧導線架預成形體 200A‧‧‧ lead frame preforms

2A‧‧‧導線架單元 2A‧‧‧ lead frame unit

21‧‧‧成型膠層 21‧‧‧Forming layer

211‧‧‧中心區 211‧‧‧ Central District

212‧‧‧切割道 212‧‧‧ cutting road

22‧‧‧晶片座 22‧‧‧ Wafer holder

23‧‧‧引腳 23‧‧‧ Pin

3‧‧‧晶片 3‧‧‧ wafer

4‧‧‧導線 4‧‧‧ wire

Claims (6)

一種導線架預成形體，包括多個彼此電性獨立且成陣列排列的導線架單元，該每一個導線架單元，包含： 一成型膠層，由絕緣高分子材料構成，具有一中心區，及一環圍該中心區的切割道； 至少一晶片座，由金屬材料構成並位於該中心區內，該晶片座具有彼此反向的一頂面及一底面，且該頂面及底面會分別自該成型膠層反向的兩個表面裸露；及 多條引腳，由與該晶片座相同的金屬材料構成，彼此各自獨立地自該切割道的頂面朝向該等晶片座延伸，並與該晶片座呈一間距。A lead frame preform comprising a plurality of lead frame units electrically and independently arranged in an array, each lead frame unit comprising: a molding layer formed of an insulating polymer material having a central region, and a scribe line surrounding the central area; at least one wafer holder, formed of a metal material and located in the central area, the wafer holder having a top surface and a bottom surface opposite to each other, and the top surface and the bottom surface are respectively The opposite surfaces of the molding layer are exposed; and a plurality of pins are formed of the same metal material as the wafer holder, and each independently extends from the top surface of the dicing street toward the wafer holders, and the wafer The seat is at a pitch. 如請求項1所述的導線架預成形體，其中，該每一個導線架單元包含多個彼此不相連接的晶片座。The leadframe preform of claim 1, wherein each of the leadframe units comprises a plurality of wafer holders that are not connected to each other. 如請求項2所述的導線架預成形體，其中，該成型膠層於任相鄰的兩個晶片座之間會具有至少一自該成型膠層表面向下形成的溝槽。The leadframe preform of claim 2, wherein the molding layer has at least one groove formed downward from the surface of the molding layer between any two adjacent wafer holders. 如請求項1所述的導線架預成形體，其中，該每一條引腳包括一自該切割道朝向該晶片座延伸的引腳部，及一自該引腳部鄰近該晶片座的端緣向下延伸的支撐部。The leadframe preform of claim 1, wherein each of the leads includes a lead portion extending from the scribe line toward the wafer holder, and an end from the lead portion adjacent to the wafer holder a support that extends downward. 如請求項4所述的導線架預成形體，其中，該引腳部與該支撐部的垂直高度總和與該晶片座的高度實質相同。The leadframe preform of claim 4, wherein a sum of vertical heights of the lead portions and the support portion is substantially the same as a height of the wafer holder. 一種導線架封裝結構，包括一個如請求項1所述之導線架預成形體、多個晶片，及多條導線，其中，該每一個晶片為設置於該其中一個晶片座上，並藉由至少部分的該等導線與該等引腳電連接，且該等晶片彼此為電性獨立。A lead frame package structure comprising the leadframe preform of claim 1, a plurality of wafers, and a plurality of wires, wherein each of the wafers is disposed on one of the wafer holders, and at least A portion of the wires are electrically connected to the pins and the wafers are electrically independent of each other.
TW105203479U 2016-03-14 2016-03-14 Lead frame performing body and lead frame packaging structure TWM523189U (en)

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