CN109785896A - It is a kind of to power on while reading the circuit for trimming position, method and device - Google Patents
It is a kind of to power on while reading the circuit for trimming position, method and device Download PDFInfo
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- CN109785896A CN109785896A CN201811547434.8A CN201811547434A CN109785896A CN 109785896 A CN109785896 A CN 109785896A CN 201811547434 A CN201811547434 A CN 201811547434A CN 109785896 A CN109785896 A CN 109785896A
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- wordline
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Abstract
It powers on the invention discloses a kind of while reading the circuit for trimming position, method and device, two, the edge wordline of storage array is used for program operation and erase operation, and corresponding bit line is input in comparator, to obtain logical bit 1 or 0, as trimming information, therefore when powering on, output once trims information to each storage array；It is not stored directly in the cell of flash chip due to trimming information, avoids the cell and trimmed the problem of information is lost after erasable, to improve the reliability of circuit.
Description
Technical field
The present invention relates to the technologies that trims of flash memory circuit, especially a kind of to power on while reading the circuit for trimming position, method
And device.
Background technique
The technology of flash chip is grown rapidly, and manufacturing process is smaller and smaller, and flash chip is deposited in process of production
In process deviation, the yield of chip will affect, therefore in the production process of chip or after chip production completion, engineer
Chip parameter is tested, is then trimmed according to key parameter of the test result to chip, and result storage will be trimmed
In flash chip, it is unified in when powering in flash chip and reads this and trim information, but flash chip may be led
Breath loss is write, therefore reliability is high not enough.
Summary of the invention
To solve the above problems, powering on while reading the circuit for trimming position, method and device, benefit the present invention provides a kind of
Information is trimmed with two wordline pre-write and by comparator output, greatly improves reliability.
Technical solution used by the present invention solves the problems, such as it is:
It is a kind of to power on while reading the circuit for trimming position, wordline and the wordline including storage array edge is arranged in
The bit line of connection, the current amplifier of the connection bit line and for export the comparator for trimming position, the wordline includes first
Wordline and the second wordline, the bit line include the first bit line and the second bit line, and the current amplifier includes the first Current amplifier
Device and the second current amplifier, first wordline is corresponding to the first bit line, and first bit line passes through first electric current
Amplifier is connected to the non-inverting input terminal of the comparator, and second wordline is corresponding to the second bit line, second bit line
The inverse output terminal of the comparator is connected to by second current amplifier.
Further, the comparator is based on sense amplifier.
It is a kind of using it is any of the above-described it is a kind of power on while reading trim the circuit of position and power on while reading and trim the side of position
Method, comprising the following steps:
Program operation is carried out to the first wordline and erase operation is carried out to the second wordline, or the first wordline is carried out
Erase is operated and is carried out program operation to the second wordline；
Each storage array is powered on；
The first bit line and the second bit line for being successively read each storage array through what comparator exported trim position, are sent to and repair
Mode transfer block.
Further, program operation is carried out to the first wordline and erase operation is carried out to the second wordline, compared after powering on
Device exports trim information 1, carries out erase operation to the first wordline and carries out program operation to the second wordline, compares after powering on
Device exports trim information 0.
Further, the operation of the first wordline and the second wordline is carried out before storage array dispatches from the factory.
It is a kind of to power on while reading the device for trimming position, comprising:
Wordline operation module, for carrying out program operation to the first wordline and carrying out erase operation to the second wordline,
Or erase operation is carried out to the first wordline and program operation is carried out to the second wordline；
Energization module, for being powered on to each storage array；
Information reading module is trimmed, the first bit line and the second bit line for being successively read each storage array are through comparator
Output trims position, is sent to trimming module.
Further, the wordline operation module exports trim information 1 or trim information 0 after the power-up.
Further, the operation of the wordline operation module carries out before storage array dispatches from the factory.
The beneficial effects of the present invention are: the present invention by two, the edge wordline of storage array be used for program operation and
Erase operation, and corresponding bit line is input in comparator, to obtain logical bit 1 or 0, as information is trimmed, therefore
When powering on, output once trims information to each storage array；Flash chip is not stored directly in due to trimming information
In cell, avoids the cell and trimmed the problem of information is lost after erasable, to improve the reliability of circuit.
Detailed description of the invention
Present invention will be further explained below with reference to the attached drawings and examples.
Fig. 1 is the storage array connection relationship diagram of the embodiment of the present invention；
Fig. 2 is the flow chart of the embodiment of the present invention.
Specific embodiment
Referring to Figures 1 and 2, An embodiment provides it is a kind of power on while reading trim the circuit of position, packet
Include the wordline that storage array edge is set, the bit line connecting with the wordline, the current amplifier and use for connecting the bit line
The comparator of position is trimmed in output, and the wordline includes the first wordline and the second wordline, and the bit line includes the first bit line and the
Two bit lines, the current amplifier include the first current amplifier and the second current amplifier, and first wordline is to first
Line is corresponding, and first bit line is connected to the non-inverting input terminal of the comparator by first current amplifier, described
Second wordline is corresponding to the second bit line, and second bit line is connected to the comparator by second current amplifier
Inverse output terminal.
The circuit structure that output trims position is given in the present embodiment, only relates to two wordline at storage array edge, by
Current amplifier is connected on the corresponding bit line of two wordline, latter two right current amplifier is input in comparator, thus output 1
Or 0, comparator described in the present embodiment is sensitive comparator, the measurement suitable for low current；Two wordline pass through different behaviour
Work can make corresponding bit line export different electric currents, to control the output result of comparator.
It powers on An embodiment provides a kind of while reading the method for trimming position, comprising the following steps:
Program operation is carried out to the first wordline and erase operation is carried out to the second wordline, or the first wordline is carried out
Erase is operated and is carried out program operation to the second wordline；
Each storage array is powered on；
The first bit line and the second bit line for being successively read each storage array through what comparator exported trim position, are sent to and repair
Mode transfer block.
The present embodiment based on it is above-mentioned it is a kind of power on and meanwhile read trim position circuit carry out, two wordline are carried out respectively
Program operation and erase operation, to make corresponding bit line export different electric currents, due to the non-inverting input terminal of comparator
It is had differences with the electric current of inverting input terminal, therefore can control comparator output, that is, control wordline realization trims letter
Breath is write.
Specifically, the operation of the first wordline and the second wordline is carried out before storage array dispatches from the factory, when powering on
It reads for the first time and generation trims information, i.e., program operation is carried out to the first wordline and erase behaviour is carried out to the second wordline
Make, powers on rear comparator output trim information 1, erase operation is carried out to the first wordline and program is carried out to the second wordline
Operation powers on rear comparator output trim information 0.
An embodiment provides it is a kind of power on while reading trim the device of position, comprising:
Wordline operation module, for carrying out program operation to the first wordline and carrying out erase operation to the second wordline,
Or erase operation is carried out to the first wordline and program operation is carried out to the second wordline；
Energization module, for being powered on to each storage array；
Information reading module is trimmed, the first bit line and the second bit line for being successively read each storage array are through comparator
Output trims position, is sent to trimming module.
The operation of the wordline operation module storage array dispatch from the factory before carry out, and after the power-up export trim information 1 or
Person trim information 0.
Above-described embodiment is carried out for the storage array in flash memory, is being dispatched from the factory to two wordline at single storage array edge
Preceding progress program operation and erase operation, when powering on, the bit line of corresponding two wordline exports different electric currents, enters
The comparator, the comparator output 1 or 0 trim information, and all information that trim of multiple storage arrays combine
Information data completely being trimmed to one, more may be used compared to will completely trim the method that information is stored in cell originally
It leans on, will not be caused to trim information loss by erasable because of cell.
The above, only presently preferred embodiments of the present invention, the invention is not limited to above embodiment, as long as
It reaches technical effect of the invention with identical means, all should belong to protection scope of the present invention.
Claims (8)
1. a kind of power on while reading the circuit for trimming position, it is characterised in that: including be arranged in storage array edge wordline, with
The bit line of the wordline connection connects the current amplifier of the bit line and for exporting the comparator for trimming position, the wordline
Including the first wordline and the second wordline, the bit line includes the first bit line and the second bit line, and the current amplifier includes first
Current amplifier and the second current amplifier, first wordline is corresponding to the first bit line, and first bit line passes through described
First current amplifier is connected to the non-inverting input terminal of the comparator, and second wordline is corresponding to the second bit line, described
Second bit line is connected to the inverse output terminal of the comparator by second current amplifier.
It a kind of power on 2. according to claim 1 while reading the circuit for trimming position, it is characterised in that: the comparator base
In sense amplifier.
3. it is a kind of using claim 1-2 it is any it is described it is a kind of power on while reading trim the circuit of position and powering on while reading
The method for trimming position: it is characterized by comprising following steps:
Program operation is carried out to the first wordline and erase operation is carried out to the second wordline, or
Person carries out erase operation to the first wordline and carries out program operation to the second wordline；
Each storage array is powered on；
The first bit line and the second bit line for being successively read each storage array through what comparator exported trim position, are sent to and trim mould
Block.
A kind of power on 4. according to claim 3 while reading the method for trimming position, it is characterised in that: to the first wordline into
Row program operation and erase operation is carried out to the second wordline, powers on rear comparator output trim information 1, to the first wordline into
Row erase is operated and is carried out program operation to the second wordline, powers on rear comparator output trim information 0.
A kind of power on 5. according to claim 3 while reading the method for trimming position, it is characterised in that: to the first wordline and
The operation of second wordline carries out before storage array dispatches from the factory.
6. a kind of power on while reading the device for trimming position, it is characterised in that: include:
Wordline operation module, for carrying out program operation to the first wordline and to the progress erase operation of the second wordline, or
Erase operation is carried out to the first wordline and program operation is carried out to the second wordline；
Energization module, for being powered on to each storage array；
Information reading module is trimmed, the first bit line and the second bit line for being successively read each storage array are exported through comparator
Trim position, be sent to trimming module.
It a kind of power on 7. according to claim 6 while reading the device for trimming position, it is characterised in that: the wordline operation
Module exports trim information 1 or trim information 0 after the power-up.
It a kind of power on 8. according to claim 6 while reading the device for trimming position, it is characterised in that: the wordline operation
The operation of module carries out before storage array dispatches from the factory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811547434.8A CN109785896B (en) | 2018-12-17 | 2018-12-17 | Circuit, method and device for simultaneously reading trimming bit during power-on |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811547434.8A CN109785896B (en) | 2018-12-17 | 2018-12-17 | Circuit, method and device for simultaneously reading trimming bit during power-on |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109785896A true CN109785896A (en) | 2019-05-21 |
| CN109785896B CN109785896B (en) | 2020-12-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811547434.8A Active CN109785896B (en) | 2018-12-17 | 2018-12-17 | Circuit, method and device for simultaneously reading trimming bit during power-on |
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Citations (6)
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|---|---|---|---|---|
| TW200949838A (en) * | 2008-05-30 | 2009-12-01 | Freescale Semiconductor Inc | Method for electrically trimming an NVM reference cell |
| CN102270507A (en) * | 2011-06-28 | 2011-12-07 | 上海宏力半导体制造有限公司 | Flash memory capable of adjusting word line voltage |
| US9436545B2 (en) * | 2013-02-04 | 2016-09-06 | Samsung Electronics Co., Ltd. | Semiconducotr memory device including non-volatile memory cell array |
| WO2017116763A2 (en) * | 2015-12-28 | 2017-07-06 | Headway Technologies, Inc. | Improved adaptive reference scheme for magnetic memory aplications |
| CN107481765A (en) * | 2017-08-22 | 2017-12-15 | 珠海泓芯科技有限公司 | Flash chip trims method of testing and trims test device |
| CN108877866A (en) * | 2017-05-08 | 2018-11-23 | 爱思开海力士有限公司 | Semiconductor devices and its builtin voltage method of adjustment |
-
2018
- 2018-12-17 CN CN201811547434.8A patent/CN109785896B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200949838A (en) * | 2008-05-30 | 2009-12-01 | Freescale Semiconductor Inc | Method for electrically trimming an NVM reference cell |
| CN102270507A (en) * | 2011-06-28 | 2011-12-07 | 上海宏力半导体制造有限公司 | Flash memory capable of adjusting word line voltage |
| US9436545B2 (en) * | 2013-02-04 | 2016-09-06 | Samsung Electronics Co., Ltd. | Semiconducotr memory device including non-volatile memory cell array |
| WO2017116763A2 (en) * | 2015-12-28 | 2017-07-06 | Headway Technologies, Inc. | Improved adaptive reference scheme for magnetic memory aplications |
| CN108877866A (en) * | 2017-05-08 | 2018-11-23 | 爱思开海力士有限公司 | Semiconductor devices and its builtin voltage method of adjustment |
| CN107481765A (en) * | 2017-08-22 | 2017-12-15 | 珠海泓芯科技有限公司 | Flash chip trims method of testing and trims test device |
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| Publication number | Publication date |
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| CN109785896B (en) | 2020-12-15 |
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Address after: 519000 unit a1106-1107, block a, entrepreneurship building, Tsinghua Science Park, 101 University Road, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee after: Zhuhai Boya Technology Co.,Ltd. Address before: Unit a1005-1007, block a, pioneering building, Tsinghua Science Park, 101 University Road, Tangjiawan Town, Zhuhai City, Guangdong Province, 519080 Patentee before: ZHUHAI BOYA TECHNOLOGY Co.,Ltd. |