CN109785896B - Circuit, method and device for simultaneously reading trimming bit during power-on - Google Patents
Circuit, method and device for simultaneously reading trimming bit during power-on Download PDFInfo
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- CN109785896B CN109785896B CN201811547434.8A CN201811547434A CN109785896B CN 109785896 B CN109785896 B CN 109785896B CN 201811547434 A CN201811547434 A CN 201811547434A CN 109785896 B CN109785896 B CN 109785896B
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Abstract
The invention discloses a circuit, a method and a device for reading trimming bits at the same time of electrifying.A, two word lines at the edge of a memory array are used for program operation and erase operation, and corresponding bit lines are input into a comparator, so that a logic bit 1 or 0 is obtained as trimming bit information, and each memory array outputs one-time trimming bit information when being electrified; because the trimming information is not directly stored in the cell of the flash memory chip, the problem that the trimming information is lost after the cell is erased is solved, and the reliability of the circuit is improved.
Description
Technical Field
The present invention relates to trimming technology of flash memory circuits, and more particularly, to a circuit, method and apparatus for reading trimming bits while powering up.
Background
The flash memory chip has a fast development in process technology, the process is smaller and smaller, and the flash memory chip has process deviation in the production process and can affect the yield of the chip, so that an engineer tests chip parameters in the production process of the chip or after the chip is produced, then repairs key parameters of the chip according to the test result, and stores the repair result in the flash memory chip, and the repair information is uniformly read in the flash memory chip when the flash memory chip is powered on, but the flash memory chip can cause information loss, so the reliability is not high enough.
Disclosure of Invention
In order to solve the above problems, the present invention provides a circuit, a method and a device for reading trimming bits at the same time when power is turned on, wherein the reliability is greatly improved by pre-writing two word lines and outputting trimming bit information through a comparator.
The technical scheme adopted by the invention for solving the problems is as follows:
a circuit for simultaneously powering on and reading trimming bits comprises word lines arranged at the edge of a memory array, bit lines connected with the word lines, current amplifiers connected with the bit lines and a comparator for outputting trimming bits, wherein the word lines comprise first word lines and second word lines, the bit lines comprise first bit lines and second bit lines, the current amplifiers comprise first current amplifiers and second current amplifiers, the first word lines correspond to the first bit lines, the first bit lines are connected to the non-inverting input end of the comparator through the first current amplifiers, the second word lines correspond to the second bit lines, and the second bit lines are connected to the inverting input end of the comparator through the second current amplifiers.
Further, the comparator is a sense amplifier.
A method for simultaneously reading trimming bits by applying the power-on and bit-reading circuit comprises the following steps:
performing a program operation on the first word line and performing an erase operation on the second word line, or performing an erase operation on the first word line and performing a program operation on the second word line;
powering up each storage array;
and sequentially reading the trimming bits output by the comparator of the first bit line and the second bit line of each memory array, and sending the trimming bits to the trimming module.
Further, program operation is carried out on the first word line, erase operation is carried out on the second word line, the comparator outputs trim information 1 after power-on, erase operation is carried out on the first word line, program operation is carried out on the second word line, and the comparator outputs trim information 0 after power-on.
Further, the operation on the first word line and the second word line is performed before the memory array is shipped.
An apparatus for powering up while reading trim bits, comprising:
the word line operation module is used for performing program operation on the first word line and performing erase operation on the second word line, or performing erase operation on the first word line and performing program operation on the second word line;
the power-on module is used for powering on each storage array;
and the trimming information reading module is used for sequentially reading the trimming bits output by the comparator of the first bit line and the second bit line of each memory array and sending the trimming bits to the trimming module.
Further, the word line operation module outputs trim information 1 or trim information 0 after being powered on.
Further, the operation of the word line operation module is performed before the memory array is shipped.
The invention has the beneficial effects that: according to the invention, two word lines at the edge of the memory array are used for program operation and erase operation, and corresponding bit lines are input into a comparator, so that a logic bit 1 or 0 is obtained as trimming bit information, and therefore, each memory array outputs trimming bit information once when being electrified; because the trimming information is not directly stored in the cell of the flash memory chip, the problem that the trimming information is lost after the cell is erased is solved, and the reliability of the circuit is improved.
Drawings
The invention is further illustrated by the following figures and examples.
FIG. 1 is a schematic diagram of a storage array connection according to an embodiment of the invention;
fig. 2 is a flow chart of an embodiment of the present invention.
Detailed Description
Referring to fig. 1 and 2, an embodiment of the present invention provides a circuit for powering up while reading a trim bit, including a word line disposed at an edge of a memory array, a bit line connected to the word line, a current amplifier connected to the bit line, and a comparator for outputting a trim bit, the word line including a first word line and a second word line, the bit line including a first bit line and a second bit line, the current amplifier including a first current amplifier and a second current amplifier, the first word line corresponding to the first bit line, the first bit line connected to a non-inverting input terminal of the comparator through the first current amplifier, the second word line corresponding to the second bit line, and the second bit line connected to an inverting input terminal of the comparator through the second current amplifier.
The circuit structure for outputting the trimming bit is provided in the embodiment, only two word lines at the edge of the memory array are involved, a current amplifier is connected to bit lines corresponding to the two word lines, and then the two current amplifiers are input into a comparator, so that 1 or 0 is output; the two word lines can enable the corresponding bit lines to output different currents through different operations, and therefore the output result of the comparator is controlled.
One embodiment of the present invention provides a method for reading trim bits while powering on, comprising the following steps:
performing a program operation on the first word line and performing an erase operation on the second word line, or performing an erase operation on the first word line and performing a program operation on the second word line;
powering up each storage array;
and sequentially reading the trimming bits output by the comparator of the first bit line and the second bit line of each memory array, and sending the trimming bits to the trimming module.
In this embodiment, based on the above circuit for simultaneously reading the trimming bit when powering on, program operation and erase operation are respectively performed on two word lines, so that the corresponding bit lines output different currents.
Specifically, the operation on the first word line and the second word line is performed before the memory array leaves a factory, when the memory array is powered on, the trimming information is read and generated for the first time, namely the program operation is performed on the first word line and the erase operation is performed on the second word line, the comparator outputs trim information 1 after the power on, the erase operation is performed on the first word line and the program operation is performed on the second word line, and the comparator outputs trim information 0 after the power on.
One embodiment of the present invention provides an apparatus for reading trim bits while powering up, including:
the word line operation module is used for performing program operation on the first word line and performing erase operation on the second word line, or performing erase operation on the first word line and performing program operation on the second word line;
the power-on module is used for powering on each storage array;
and the trimming information reading module is used for sequentially reading the trimming bits output by the comparator of the first bit line and the second bit line of each memory array and sending the trimming bits to the trimming module.
The operation of the word line operation module is carried out before the memory array leaves a factory, and trim information 1 or trim information 0 is output after the power is on.
The embodiment is performed for a memory array in a flash memory, program operation and erase operation are performed on two word lines at the edge of a single memory array before leaving a factory, when the flash memory is powered on, different currents are output corresponding to bit lines of the two word lines and enter the comparator, the comparator outputs trimming information of 1 or 0, all trimming information of a plurality of memory arrays are combined to obtain complete trimming information data, and compared with an original method for storing the complete trimming information in a cell, the method is more reliable, and trimming information loss caused by erasing and writing of the cell is avoided.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and the present invention shall fall within the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means.
Claims (8)
1. A circuit for simultaneously reading trimming bits when powering up is characterized in that: the memory array comprises word lines arranged at the edge of a memory array, bit lines connected with the word lines, current amplifiers connected with the bit lines and a comparator used for outputting trimming bits, wherein the word lines comprise first word lines and second word lines, the bit lines comprise first bit lines and second bit lines, the current amplifiers comprise first current amplifiers and second current amplifiers, the first word lines correspond to the first bit lines, the first bit lines are connected to the non-inverting input end of the comparator through the first current amplifiers, the second word lines correspond to the second bit lines, and the second bit lines are connected to the inverting input end of the comparator through the second current amplifiers.
2. A circuit for powering up while reading trim bits according to claim 1, wherein: the comparator is a sensitive amplifier.
3. A method of powering up a simultaneous read trim bit using a circuit as claimed in any one of claims 1 to 2: the method is characterized in that: the method comprises the following steps:
performing a program operation on the first word line and performing an erase operation on the second word line, or performing an erase operation on the first word line and performing a program operation on the second word line;
powering up each storage array;
and sequentially reading the trimming bits output by the comparator of the first bit line and the second bit line of each memory array, and sending the trimming bits to the trimming module.
4. A method of powering up while reading trim bits according to claim 3, wherein: performing program operation on the first word line and erase operation on the second word line, outputting trim information 1 by the comparator after power-on, performing erase operation on the first word line and program operation on the second word line, and outputting trim information 0 by the comparator after power-on.
5. A method of powering up while reading trim bits according to claim 3, wherein: the operation on the first word line and the second word line is performed before the memory array is shipped.
6. The utility model provides a device of debugging bit is read simultaneously to power-on which characterized in that: the method comprises the following steps:
the word line operation module is used for performing program operation on the first word line and performing erase operation on the second word line, or performing erase operation on the first word line and performing program operation on the second word line;
the power-on module is used for powering on each storage array;
and the trimming information reading module is used for sequentially reading the trimming bits output by the comparator of the first bit line and the second bit line of each memory array and sending the trimming bits to the trimming module.
7. The apparatus of claim 6, wherein the apparatus for powering on and reading trim bits comprises: and the word line operation module outputs trim information 1 or trim information 0 after being powered on.
8. The apparatus of claim 6, wherein the apparatus for powering on and reading trim bits comprises: the operation of the word line operation module is carried out before the memory array leaves factory.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811547434.8A CN109785896B (en) | 2018-12-17 | 2018-12-17 | Circuit, method and device for simultaneously reading trimming bit during power-on |
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| CN201811547434.8A CN109785896B (en) | 2018-12-17 | 2018-12-17 | Circuit, method and device for simultaneously reading trimming bit during power-on |
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| CN109785896A CN109785896A (en) | 2019-05-21 |
| CN109785896B true CN109785896B (en) | 2020-12-15 |
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| TW200949838A (en) * | 2008-05-30 | 2009-12-01 | Freescale Semiconductor Inc | Method for electrically trimming an NVM reference cell |
| CN102270507A (en) * | 2011-06-28 | 2011-12-07 | 上海宏力半导体制造有限公司 | Flash memory capable of adjusting word line voltage |
| US9436545B2 (en) * | 2013-02-04 | 2016-09-06 | Samsung Electronics Co., Ltd. | Semiconducotr memory device including non-volatile memory cell array |
| WO2017116763A3 (en) * | 2015-12-28 | 2017-10-19 | Headway Technologies, Inc. | Adaptive reference scheme for magnetic memory |
| CN107481765A (en) * | 2017-08-22 | 2017-12-15 | 珠海泓芯科技有限公司 | Flash chip trims method of testing and trims test device |
| CN108877866A (en) * | 2017-05-08 | 2018-11-23 | 爱思开海力士有限公司 | Semiconductor devices and its builtin voltage method of adjustment |
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2018
- 2018-12-17 CN CN201811547434.8A patent/CN109785896B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200949838A (en) * | 2008-05-30 | 2009-12-01 | Freescale Semiconductor Inc | Method for electrically trimming an NVM reference cell |
| CN102270507A (en) * | 2011-06-28 | 2011-12-07 | 上海宏力半导体制造有限公司 | Flash memory capable of adjusting word line voltage |
| US9436545B2 (en) * | 2013-02-04 | 2016-09-06 | Samsung Electronics Co., Ltd. | Semiconducotr memory device including non-volatile memory cell array |
| WO2017116763A3 (en) * | 2015-12-28 | 2017-10-19 | Headway Technologies, Inc. | Adaptive reference scheme for magnetic memory |
| CN108877866A (en) * | 2017-05-08 | 2018-11-23 | 爱思开海力士有限公司 | Semiconductor devices and its builtin voltage method of adjustment |
| CN107481765A (en) * | 2017-08-22 | 2017-12-15 | 珠海泓芯科技有限公司 | Flash chip trims method of testing and trims test device |
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