CN109755244B - 一种制作动态随机存储器的埋入式字符线的方法 - Google Patents

一种制作动态随机存储器的埋入式字符线的方法 Download PDF

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CN109755244B
CN109755244B CN201711079388.9A CN201711079388A CN109755244B CN 109755244 B CN109755244 B CN 109755244B CN 201711079388 A CN201711079388 A CN 201711079388A CN 109755244 B CN109755244 B CN 109755244B
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random access
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张凯钧
陈意维
郑存闵
吴佳臻
陈品宏
蔡志杰
陈姿洁
黄怡安
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Abstract

本发明公开一种制作动态随机存储器的埋入式字符线的方法，其主要先形成一凹槽于基底内，然后形成一阻障层于凹槽内，进行一浸入式(soak)制作工艺，由此降低阻障层内的氯浓度，之后再形成一导电层并填满凹槽。

Description

一种制作动态随机存储器的埋入式字符线的方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种制作动态随机存储器(Dynamic Random Access Memory,DRAM)元件的埋入式字符线的方法。
背景技术
随着各种电子产品朝小型化发展的趋势，动态随机存储器(DRAM)单元的设计也必须符合高集成度及高密度的要求。对于一具备凹入式栅极结构的DRAM单元而言，由于其可以在相同的半导体基底内获得更长的载流子通道长度，以减少电容结构的漏电情形产生，因此在目前主流发展趋势下，其已逐渐取代仅具备平面栅极结构的DRAM单元。
一般来说，具备凹入式栅极结构的DRAM单元会包含一晶体管元件与一电荷贮存装置，以接收来自于位线及字符线的电压信号。然而，受限于制作工艺技术之故，现有具备凹入式栅极结构的DRAM单元仍存在有许多缺陷，还待进一步改良并有效提升相关存储器元件的效能及可靠度。
发明内容
本发明一实施例公开一种制作动态随机存储器的埋入式字符线的方法，其主要先形成一凹槽于基底内，然后形成一阻障层于凹槽内，进行一浸入式(soak)制作工艺由此降低阻障层内的氯浓度，之后再形成一导电层并填满凹槽。
依据本发明一实施例，形成阻障层的步骤较佳包含将含钛的第一反应物以及一包含氮的第二反应物反应以形成一由氮化钛所构成的阻障层以及一包含Ti(NH2)xCly的副产物，之后再进行浸入式制作工艺去除该副产物，由此提升阻障层以及导电层之间的附着能力(adhesion)并同时降低元件阻值。
附图说明
图1至图6为本发明一实施例制作一动态随机存储器元件的方法示意图。
主要元件符号说明
10 动态随机存储器元件 12 位线
14 字符线 16 基底
18 主动区(有源区) 20 存储器区
22 栅极 24 浅沟绝缘
26 凹槽 28 阻障层
30 副产物 32 氨气
34 导电层 36 栅极结构
38 硬掩模
具体实施方式
请参照图1至图6，图1至图6为本发明一实施例制作一动态随机存储器元件的方法示意图，其中图1为俯视图，图2至图6则显示图1中沿着切线AA’方向制作动态随机存储器元件的埋入式字符线的方法示意图。本实施例是提供一存储器元件，例如是具备凹入式栅极的动态随机存储器元件10，其包含有至少一晶体管元件(图未示)以及至少一电容结构(图未示)，以作为DRAM阵列中的最小组成单元并接收来自于位线12及字符线14的电压信号。
如图1所示，动态随机存储器元件10包含一基底16，例如一由硅所构成的半导体基底，然后于基底16内形成有至少一浅沟绝缘24，以于基底16上定义出多个主动区(activearea,AA)18。此外，基底16上还定义有一存储器区20以及一周边区(图未示)。其中，动态随机存储器元件10的多个字符线(word line,WL)14与多个位线(bit line,BL)12较佳形成于存储器区20的基底16上而其他的主动(有源)元件等(未绘示)则可形成在周边区。需注意的是，为简化说明，本发明的图1仅绘示出位于存储器区20的元件上视图并省略了位于周边区的元件。
在本实施例中，各主动区18例如是相互平行地朝向一第一方向延伸，而字符线14或多条栅极22是形成在基底16内并穿越各主动区18及浅沟绝缘24。具体来说，各栅极22是沿着不同于第一方向的一第二方向，例如Y方向延伸，且第二方向与第一方向相交并小于90度。
另一方面，位线12是相互平行地形成在基底16上沿着一第三方向，例如X方向延伸，并同样横跨各主动区18及浅沟绝缘24。其中，第三方向同样是不同于第一方向并且较佳是与第二方向垂直。也就是说，第一方向、第二方向及第三方向彼此都不同，且第一方向与第二方向及第三方向都不垂直。此外，字符线14两侧的主动区18内较佳设有接触插塞，例如包括位线接触插塞(bit line contact,BLC)(图未示)来电连接至各晶体管元件的源极/漏极区域(图未示)以及存储节点(storage node)接触插塞(图未示)来电连接一电容。
以下针对字符线14(或又称埋入式字符线)的制作进行说明。首先如图2所示，先形成至少一凹槽26于基底16内，然后依序形成一栅极介电层(图未示)以及一阻障层28于凹槽26内以及基底16表面。在本实施例中，形成阻障层28的步骤较佳将含钛的第一反应物以及一含氮的第二反应物反应以形成阻障层28。更具体而言，本实施例较佳将例如四氯化钛(TiCl4)的第一反应物与例如氨气(NH3)的第二反应物反应而形成由氮化钛(TiN)所构成的阻障层28以及氯化氢(HCl)。
值得注意的是，一般形成阻障层28的过程中时常因第一反应物以及第二反应物之间的反应不完成造成含氯元素沉淀进而产生由Ti(NH2)xCly所构成的副产物(byproduct)30。由于此副产物30附着于阻障层28表面后容易降低后续阻障层28以及导电层之间的附着能力(adhesion performance)，本发明较佳在阻障层28形成之后进行一浸入式(soak)制作工艺来去除该副产物30并同时降低阻障层28表面的氯浓度。
在本实施例中，浸入式制作工艺可细部包含以下两道步骤，其主要先进行一现场氨气浸入式制作工艺将氨气与前述副产物反应，然后再进行一氮气清除(N2 purge)制作工艺来去除由副产物30与氨气再次反应而产生的氯化氢。
如图3所示，本实施例可先进行一现场(in-situ)氨气浸入式制作工艺，例如可在同一反应室内通入氨气32，使氨气32与Ti(NH2)xCly所构成的副产物30反应结合后形成氮化钛以及氯化氢。
接着如图4所示，进行一氮气清除制作工艺，例如利用氮气作为媒介沿着箭头方向吹除或带走反应室内的氯化氢，由此降低阻障层28表面的氯浓度并使阻障层28表面不再附着任何副产物30。
需注意的是，前述由图3至图4所进行的两道步骤较佳视为一道浸入式制作工艺循环(soaking cycle)，且依据本发明的一实施例，在图2形成氮化钛所构成的阻障层28之后较佳进行十次或十次以上浸入式制作工艺循环来确保阻障层28表面无任何副产物30残留。换句话说，本发明较佳于图2形成阻障层28后重复进行图3至图4的步骤至少十次或十次以上，如此即可确保后续形成导电层时阻障层28与导电层之间不至因副产物存在而影响两者之间的附着能力。
如图5所示，接着形成一导电层34于阻障层28上，其中导电层34较佳填满凹槽26并设于凹槽外26的阻障层28上方。本实施例中，导电层34较佳包含钨，但不局限于此。
然后如图6所示，利用回蚀刻制作工艺去除部分导电层34、部分阻障层28以及部分栅极介电层以形成一栅极结构36于凹槽26内，其中所形成的栅极结构36即为图1的字符线14。之后再形成一硬掩模38于栅极结构36上并使硬掩模38上表面切齐基底16上表面。在本实施例中，硬掩模38较佳包含氮化硅，但不局限于此。随后可依据制作工艺需求进行一离子注入制作工艺，以于栅极结构36两侧的基底16内形成掺杂区(图未示)，例如轻掺杂漏极或源极/漏极区域。最后进行接触插塞制作工艺，例如可分别于栅极结构36两侧形成位线接触插塞电连接源极/漏极区域与后续所制作的位线，以及形成存储节点接触插塞同时电连接源极/漏极区域与后续所制作的电容。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (6)

1.一种制作动态随机存储器的埋入式字符线的方法，包含：
形成一凹槽于一基底内；
形成一阻障层于该凹槽内；
进行一浸入式(soak)制作工艺由此降低阻障层表面的氯浓度，其中该浸入式制作工艺包含：
a)进行一现场氨气浸入式制作工艺将氨气以及包含Ti(NH2)xCly的副产物反应；以及
b)进行一氮气清除制作工艺；以及
形成一导电层并填满该凹槽。
2.如权利要求1所述的方法，另包含：
将含钛的第一反应物以及一含氮的第二反应物反应以形成该阻障层以及该副产物；以及
进行该浸入式制作工艺去除该副产物。
3.如权利要求2所述的方法，其中该第一反应物包含四氯化钛以及该第二反应物包含氨气。
4.如权利要求1所述的方法，另包含重复进行该步骤a)以及步骤b)十次或十次以上。
5.如权利要求1所述的方法，其中该阻障层包含氮化钛。
6.如权利要求1所述的方法，其中该导电层包含钨。
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