CN109686804B - InGaAs探测器芯片及其制备方法 - Google Patents

InGaAs探测器芯片及其制备方法 Download PDF

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CN109686804B
CN109686804B CN201811607949.2A CN201811607949A CN109686804B CN 109686804 B CN109686804 B CN 109686804B CN 201811607949 A CN201811607949 A CN 201811607949A CN 109686804 B CN109686804 B CN 109686804B
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黄寓洋
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Suzhou Suna Photoelectric Co ltd
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Abstract

本发明公开了一种InGaAs探测器芯片及其制备方法，所述InGaAs探测器芯片依次包括衬底、N型半导体层、吸收层、及P型半导体层，所述N型半导体层为n+掺杂的InP层，P型半导体层为p+掺杂的InP层，吸收层包括p+掺杂的P型InGaAs吸收层和n+掺杂的N型InGaAs吸收层，P型InGaAs吸收层与P型半导体层相邻，N型InGaAs吸收层与N型半导体层相邻，所述P型InGaAs吸收层的厚度小于N型InGaAs吸收层的厚度，P型InGaAs吸收层的掺杂浓度大于N型InGaAs吸收层的掺杂浓度。本发明通过优化吸收层的厚度及掺杂，采用高低掺杂的两层InGaAs吸收层，可以增大PN结的结电容，在不影响芯片响应速度的情况下，大大提高了探测器芯片的抗静电能力，保证了芯片的可靠性。

Description

InGaAs探测器芯片及其制备方法
技术领域
本发明涉及半导体制造技术领域，特别是涉及一种InGaAs探测器芯片及其制备方法。
背景技术
铟镓砷探测器芯片的传统结构为InP/InGaAs/InP结构，其在近红外波段内拥有良好的性能，这使得其在民用、军事和航空航天领域有着广泛的应用价值。
然而，在激光器、探测器等芯片等领域，静电击穿经常导致芯片在使用过程中失效，造成芯片寿命减少，影响客户正常使用，无法保证芯片的抗静电能力和可靠性。
因此，针对上述技术问题，有必要提供一种InGaAs探测器芯片及其制备方法。
发明内容
有鉴于此，本发明的目的在于提供一种InGaAs探测器芯片及其制备方法。
为了实现上述目的，本发明一实施例提供的技术方案如下：
一种InGaAs探测器芯片，所述InGaAs探测器芯片依次包括衬底、N型半导体层、吸收层、及P型半导体层，所述N型半导体层为n+掺杂的InP层，P型半导体层为p+掺杂的InP层，吸收层包括p+掺杂的P型InGaAs吸收层和n+掺杂的N型InGaAs吸收层，P型InGaAs吸收层与P型半导体层相邻，N型InGaAs吸收层与N型半导体层相邻，所述P型InGaAs吸收层的厚度小于N型InGaAs吸收层的厚度，P型InGaAs吸收层的掺杂浓度大于N型InGaAs吸收层的掺杂浓度。
作为本发明的进一步改进，所述P型InGaAs吸收层的掺杂浓度为5E15cm-3～9E16cm-3，N型InGaAs吸收层的掺杂浓度为5E14cm-3～9E15cm-3。
作为本发明的进一步改进，所述P型InGaAs吸收层的掺杂浓度为1E16cm-3，N型InGaAs吸收层的掺杂浓度为1E15cm-3。
作为本发明的进一步改进，所述P型InGaAs吸收层的厚度为50nm～200nm，N型InGaAs吸收层的的厚度为2000nm～4000nm。
作为本发明的进一步改进，所述P型InGaAs吸收层的厚度为100nm，N型InGaAs吸收层的的厚度为2900nm。
作为本发明的进一步改进，所述衬底为InP衬底。
作为本发明的进一步改进，所述P型半导体层上还包括p+掺杂的InGaAs接触层。
本发明另一实施例提供的技术方案如下：
一种InGaAs探测器芯片的制备方法，所述制备方法包括：
提供一衬底；
在衬底上外延生长N型半导体层，N型半导体层为n+掺杂的InP层；
在N型半导体层上外延生长吸收层，所述吸收层包括p+掺杂的P型InGaAs吸收层和n+掺杂的N型InGaAs吸收层，P型InGaAs吸收层位于N型InGaAs吸收层上方，P型InGaAs吸收层的厚度小于N型InGaAs吸收层的厚度，P型InGaAs吸收层的掺杂浓度大于N型InGaAs吸收层的掺杂浓度；
在吸收层上外延生长P型半导体层，P型半导体层为p+掺杂的InP层。
作为本发明的进一步改进，所述P型InGaAs吸收层的掺杂浓度为5E15cm-3～9E16cm-3，N型InGaAs吸收层的掺杂浓度为5E14cm-3～9E15cm-3。
作为本发明的进一步改进，所述P型InGaAs吸收层的厚度为50nm～200nm，N型InGaAs吸收层的的厚度为2000nm～4000nm。
本发明的有益效果是：
本发明通过优化吸收层的厚度及掺杂，采用高低掺杂的两层InGaAs吸收层，可以增大PN结的结电容，在不影响芯片响应速度的情况下，大大提高了探测器芯片的抗静电能力，保证了芯片的可靠性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明中记载的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明一具体实施例中InGaAs探测器芯片的结构示意图；
图2为本发明一具体实施例中InGaAs探测器芯片制备方法的流程示意图；
图3为现有技术中InGaAs探测器芯片的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本发明保护的范围。
参图1所示本发明公开了一种InGaAs探测器芯片，依次包括衬底、N型半导体层、吸收层、及P型半导体层，N型半导体层为n+掺杂的InP层，P型半导体层为p+掺杂的InP层，吸收层包括p+掺杂的P型InGaAs吸收层和n+掺杂的N型InGaAs吸收层，P型InGaAs吸收层与P型半导体层相邻，N型InGaAs吸收层与N型半导体层相邻，P型InGaAs吸收层的厚度小于N型InGaAs吸收层的厚度，P型InGaAs吸收层的掺杂浓度大于N型InGaAs吸收层的掺杂浓度。
参图2所示，本发明还公开了一种InGaAs探测器芯片的制备方法，包括：
提供一衬底；
在衬底上外延生长N型半导体层，N型半导体层为n+掺杂的InP层；
在N型半导体层上外延生长吸收层，吸收层包括p+掺杂的P型InGaAs吸收层和n+掺杂的N型InGaAs吸收层，P型InGaAs吸收层位于N型InGaAs吸收层上方，P型InGaAs吸收层的厚度小于N型InGaAs吸收层的厚度，P型InGaAs吸收层的掺杂浓度大于N型InGaAs吸收层的掺杂浓度；
在吸收层上外延生长P型半导体层，P型半导体层为p+掺杂的InP层。
以下结合具体实施例对本发明进行详细说明。
参图1所示，本发明一具体实施例中的InGaAs探测器芯片，依次包括：
衬底10，衬底为InP衬底；
N型半导体层20，N型半导体层为n+掺杂的InP层；
吸收层30，吸收层30包括p+掺杂的P型InGaAs吸收层31和n+掺杂的N型InGaAs吸收层32，P型InGaAs吸收层31与P型半导体层40相邻，N型InGaAs吸收层32与N型半导体层20相邻，P型InGaAs吸收层31的厚度小于N型InGaAs吸收层32的厚度，P型InGaAs吸收层31的掺杂浓度大于N型InGaAs吸收层32的掺杂浓度；
P型半导体层40，P型半导体层为p+掺杂的InP层；
接触层50，接触层为p+掺杂的InGaAs接触层。
其中，本发明中P型InGaAs吸收层31的掺杂类型为p+，掺杂浓度为5E15cm-3～9E16cm-3，厚度为50nm～200nm；N型InGaAs吸收层32的掺杂类型为n+，掺杂浓度为5E14cm-3～9E15cm-3，厚度为2000nm～4000nm。
优选地，本实施例中P型InGaAs吸收层31的掺杂浓度为1E16cm-3，厚度为100nm；N型InGaAs吸收层32的掺杂浓度为1E15cm-3，厚度为2900nm。
结合图2所示，本实施例中InGaAs探测器芯片的制备方法，包括以下步骤：
提供一衬底；
在衬底上外延生长N型半导体层，N型半导体层为n+掺杂的InP层；
在N型半导体层上外延生长吸收层，吸收层包括p+掺杂的P型InGaAs吸收层和n+掺杂的N型InGaAs吸收层，P型InGaAs吸收层位于N型InGaAs吸收层上方，P型InGaAs吸收层的厚度小于N型InGaAs吸收层的厚度，P型InGaAs吸收层的掺杂浓度大于N型InGaAs吸收层的掺杂浓度；
在吸收层上外延生长P型半导体层，P型半导体层为p+掺杂的InP层。
具体地，本实施例中P型InGaAs吸收层31的掺杂浓度为1E16cm-3，厚度为100nm；N型InGaAs吸收层32的掺杂浓度为1E15cm-3，厚度为2900nm。
参图3所示，现有技术中的InGaAs探测器芯片，依次包括：
衬底10’，衬底为InP衬底；
N型半导体层20’，N型半导体层为n+掺杂的InP层；
本征层30’，本征层30为InGaAs本征层，厚度为3000nm，未掺杂；
P型半导体层40’，P型半导体层为p+掺杂的InP层；
接触层50’，接触层为p+掺杂的InGaAs接触层。
经过测试，采用面积相同的芯片(100μm*100μm)，现有技术中的InGaAs探测器芯片的抗静电能力为1000V，而采用本发明具体实施例中的InGaAs探测器芯片的结电容为4.2pF，抗静电能力能够提升至2000V，且本实施例中的芯片响应速度未降低。
通过改变P型InGaAs吸收层31和N型InGaAs吸收层32的厚度及掺杂浓度进行抗电性能测试，在P型InGaAs吸收层31和N型InGaAs吸收层32掺杂浓度比为10：1、厚度比为1：29的情况下，InGaAs探测器芯片的抗静电性能最佳。
由以上技术方案可以看出，本发明具有如下有益效果：
本发明通过优化吸收层的厚度及掺杂，采用高低掺杂的两层InGaAs吸收层，可以增大PN结的结电容，在不影响芯片响应速度的情况下，大大提高了探测器芯片的抗静电能力，保证了芯片的可靠性。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (6)

1.一种InGaAs探测器芯片，其特征在于，所述InGaAs探测器芯片包括衬底和依次设置在衬底上的N型半导体层、吸收层及P型半导体层，所述N型半导体层为n+掺杂的InP层，所述P型半导体层为p+掺杂的InP层，所述吸收层包括p+掺杂的P型InGaAs吸收层和n+掺杂的N型InGaAs吸收层，所述P型InGaAs吸收层与P型半导体层相邻，所述N型InGaAs吸收层与N型半导体层相邻，所述P型InGaAs吸收层的掺杂浓度为5E15cm-3~9E16cm-3、厚度为50nm~200nm，所述N型InGaAs吸收层的掺杂浓度为5E14cm-3~9E15cm-3、厚度为2000nm~4000nm，并且所述P型InGaAs吸收层的掺杂浓度大于N型InGaAs吸收层的掺杂浓度。
2.根据权利要求1所述的InGaAs探测器芯片，其特征在于，所述P型InGaAs吸收层的掺杂浓度为1E16cm-3，所述N型InGaAs吸收层的掺杂浓度为1E15cm-3。
3.根据权利要求1所述的InGaAs探测器芯片，其特征在于，所述P型InGaAs吸收层的厚度为100nm，N型InGaAs吸收层的的厚度为2900nm。
4.根据权利要求1所述的InGaAs探测器芯片，其特征在于，所述衬底为InP衬底。
5.根据权利要求1所述的InGaAs探测器芯片，其特征在于，所述P型半导体层上还设有p+掺杂的InGaAs接触层。
6.一种InGaAs探测器芯片的制备方法，其特征在于，所述制备方法包括：
提供一衬底；
在所述衬底上外延生长N型半导体层，所述N型半导体层为n+掺杂的InP层；
在所述N型半导体层上外延生长吸收层，所述吸收层包括p+掺杂的P型InGaAs吸收层和n+掺杂的N型InGaAs吸收层，所述P型InGaAs吸收层与P型半导体层相邻，所述N型InGaAs吸收层与N型半导体层相邻，所述P型InGaAs吸收层的掺杂浓度为5E15cm-3~9E16cm-3、厚度为50nm~200nm，所述N型InGaAs吸收层的掺杂浓度为5E14cm-3~9E15cm-3、厚度为2000nm~4000nm，并且所述P型InGaAs吸收层的掺杂浓度大于N型InGaAs吸收层的掺杂浓度；
在所述吸收层上外延生长P型半导体层，所述P型半导体层为p+掺杂的InP层。
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