CN109686666A - A kind of fast recovery chip manufacture method - Google Patents
A kind of fast recovery chip manufacture method Download PDFInfo
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- CN109686666A CN109686666A CN201811605590.5A CN201811605590A CN109686666A CN 109686666 A CN109686666 A CN 109686666A CN 201811605590 A CN201811605590 A CN 201811605590A CN 109686666 A CN109686666 A CN 109686666A
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- 238000011084 recovery Methods 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims abstract description 66
- 238000009792 diffusion process Methods 0.000 claims abstract description 59
- 229910052697 platinum Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000005260 corrosion Methods 0.000 claims abstract description 29
- 230000007797 corrosion Effects 0.000 claims abstract description 29
- 238000004140 cleaning Methods 0.000 claims abstract description 15
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 12
- 238000002161 passivation Methods 0.000 claims abstract description 10
- 238000001465 metallisation Methods 0.000 claims abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 44
- 229910052710 silicon Inorganic materials 0.000 claims description 44
- 239000010703 silicon Substances 0.000 claims description 44
- 239000012535 impurity Substances 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 4
- 238000001035 drying Methods 0.000 claims description 2
- 239000000843 powder Substances 0.000 claims description 2
- 230000001737 promoting effect Effects 0.000 claims 1
- 239000002002 slurry Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 21
- 239000002585 base Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000012805 post-processing Methods 0.000 description 2
- 238000012913 prioritisation Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000004576 sand Substances 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000004506 ultrasonic cleaning Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 125000002091 cationic group Chemical group 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- GVVPGTZRZFNKDS-JXMROGBWSA-N geranyl diphosphate Chemical compound CC(C)=CCC\C(C)=C\CO[P@](O)(=O)OP(O)(O)=O GVVPGTZRZFNKDS-JXMROGBWSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 230000009972 noncorrosive effect Effects 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of fast recovery chip manufacture methods, are related to chip manufacturing technical field.It is deposited magnetron sputtering and makes fast recovery diffusion substrate by way of platinum layer is diffused again, then fast recovery diffusion substrate is precut according to presetting size to form groove, wherein, presetting size includes presetting width and presetting depth, groove is corroded according to preheating setting time again, to form the groove after corrosion, wherein, diffusion substrate is separated into multiple fast recovery chips interconnected by groove, cleaning and passivation protection are carried out to the groove after corrosion again, and each fast surface for restoring chip is set to form Ohmic contact by metallization, the last groove according to after corrosion is cut, to form multiple fast recovery chips.The fast chip manufacture method that restores provided by the invention has the reverse recovery time for the fast recovery chip being cut into short and Relatively centralized, while can achieve the effect that reduce forward voltage drop.
Description
Technical field
The present invention relates to chip manufacturing technical fields, in particular to a kind of fast recovery chip manufacture method.
Background technique
Fast recovery diode (abbreviation FRD) is a kind of semiconductor for having the characteristics that switching characteristic is good, reverse recovery time is short
Diode is mainly used in the electronic circuits such as Switching Power Supply, PWM pulse width modulator, frequency converter, as two pole of high-frequency rectification
Pipe, freewheeling diode or damper diode use.
The country is that forward voltage drop is big with conventionally produced fast recovery chip common problem at present, two after encapsulation
The power consumption of pole pipe is larger, and diode is easily burnt.And the fast recovery diode in high-power circuit is applied, to wherein chip
Forward voltage drop Capability Requirement is especially harsh.
It is the emphasis of those skilled in the art's concern in view of this, how to solve the above problems.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of fast recovery chip manufacture methods, to solve in the prior art
The big problem of the fast forward voltage drop for restoring chip.
To achieve the goals above, technical solution used in the embodiment of the present invention is as follows:
The embodiment of the invention provides a kind of fast recovery chip manufacture method, the fast recovery chip manufacture method includes:
It is deposited magnetron sputtering and makes fast recovery diffusion substrate by way of platinum layer is diffused again；
The fast recovery diffusion substrate is precut according to presetting size to form groove, wherein described default
Fixed size includes presetting width and presetting depth；
The groove is corroded according to preheating setting time, to form the groove after corrosion, wherein the groove is by institute
It states diffusion substrate and is separated into multiple fast recovery chips interconnected；
Cleaning and passivation protection are carried out to the groove after the corrosion, and each fast recovery chip is made by metallization
Surface formed Ohmic contact；
It is cut according to the groove after the corrosion, to form multiple fast recovery chips.
Compared with the prior art, the invention has the following advantages:
The present invention provides a kind of fast recovery chip manufacture methods, wherein deposits platinum layer by magnetron sputtering and is expanded again
Scattered mode makes fast recovery diffusion substrate, is then precut to fast recovery diffusion substrate according to presetting size to be formed
Groove, wherein presetting size includes presetting width and presetting depth, then carries out corruption according to preheating setting time to groove
Erosion, to form the groove after corrosion, wherein diffusion substrate is separated into multiple fast recovery chips interconnected by groove, then right
Groove after corrosion carries out cleaning and passivation protection, and so that each fast surface for restoring chip is formed ohm by metallization and connect
Touching, the last groove according to after corrosion is cut, to form multiple fast recovery chips.Due to fast recovery core provided by the invention
Piece production method is to deposit by way of platinum layer is diffused again to carry out platinum diffusion, the Reverse recovery of chip magnetron sputtering
Time is short and Relatively centralized.It needs first to be precut additionally, due to fast recovery chip manufacture method provided by the invention, then
Corroded, therefore corroded by the groove of presetting size, corrosion depth can be reached within the shorter time, in turn
Smaller for the width of corrosion, the table top for the fast recovery chip being cut into is larger.Due to restore fastly the mesa dimensions of chip with just
Inversely to pressure drop, therefore by way of increasing the fast table top for restoring chip, the effect for reducing forward voltage drop can be reached
Fruit.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, preferred embodiment is cited below particularly, and cooperate
Appended attached drawing, is described in detail below.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 shows the fast flow chart for restoring chip manufacture method provided in an embodiment of the present invention.
Fig. 2 shows the flow charts of the sub-step of step S101 in Fig. 1 provided in an embodiment of the present invention.
Fig. 3 shows the schematic diagram of cutting technique provided in an embodiment of the present invention.
Label: the area 110-N；The area 120-P；130- colloid protective layer；140- blade；150- groove.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings is implemented
The component of example can be arranged and be designed with a variety of different configurations.
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Usually exist
The component of the embodiment of the present invention described and illustrated in attached drawing can be arranged and be designed with a variety of different configurations herein.Cause
This, is not intended to limit claimed invention to the detailed description of the embodiment of the present invention provided in the accompanying drawings below
Range, but it is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.Meanwhile of the invention
In description, it is also necessary to which explanation is unless specifically defined or limited otherwise, term " connected ", " connection " shall be understood in a broad sense,
It for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can be mechanical connection, be also possible to electricity
Connection；It can be directly connected, the connection inside two elements can also be can be indirectly connected through an intermediary.For
For those skilled in the art, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.It ties below
Attached drawing is closed, is elaborated to some embodiments of the present invention.In the absence of conflict, following embodiment and embodiment
In feature can be combined with each other.
Referring to Fig. 1, restore chip manufacture method the embodiment of the invention provides a kind of fast, with obtain forward voltage drop it is low,
Reverse recovery time is short and is distributed the fast recovery chip concentrated.The fast recovery chip manufacture method includes:
Step S101 is deposited magnetron sputtering and is made fast recovery diffusion substrate by way of platinum layer is diffused again.
In the present embodiment, restore diffusion substrate fastly to refer to using the silicon wafer formation area N 110 and the area P 120, and carry out platinum layer
The overall structure of diffusion.
Specifically, referring to Fig. 2, in the present embodiment, step S101 includes:
Sub-step S1011 carries out chemical cleaning to the surface of selected silicon wafer.
Chip is restored fastly for low pressure drop, production target is that acquisition is smaller while obtaining lesser reverse recovery time
Forward voltage drop to reduce turn-on consumption.But there is the relationships of compromise for reverse recovery time and forward voltage drop, therefore will be to core
Piece is reasonably designed, i.e., under conditions of meeting direction turnaround time, reduction Vf as far as possible.For diode chip for backlight unit
Speech, total forward voltage drop is by metal-semiconductor contact pressure drop, the area P 120, the 110 heavily doped layer pressure drop of the area N, knot pressure drop and base area
A few part compositions of pressure drop Vm.In the area P 120, under the conditions of 110 heavily doped layer concentration of the area N is sufficiently high and good Ohmic contact, contact
Pressure drop, heavy doping pressure drop and NN+ knot pressure drop are negligible, and base resistance rate and one timing P+N knot pressure of junction depth drop are also fixed
Value.Forward voltage drop is reduced, is critical to reduce base area pressure drop Vm.By formula(wherein, W is base width,
τ H is carrier lifetime, and DH is ambipolar diffusion coefficient) it is found that base area is wider, Vf is bigger.Meanwhile there are direct ratios with resistivity by Vm
Relationship, therefore from reduce Vm, preferably select lesser base width and lesser resistivity, and to improve reverse breakdown electricity
Pressure then requires biggish base width and biggish resistivity.As it can be seen that requirement of the positive and negative electrical parameter to resistivity, base width
It is conflicting, therefore in terms of design is to take into account two, meanwhile, under the premise of guaranteeing certain breakdown reverse voltage, silicon wafer is answered
It selects as far as possible thin.By experiment, 35~40 Ω cm of final choice resistivity of the present invention, the silicon wafer of thickness T=270 ± 5 μm.
Also, after selected silicon wafer, impurities on surface of silicon chip influences the fast recovery chip being finally made in order to prevent
Effect needs to be chemically treated to achieve the effect that cleaning selected silicon wafer in the present embodiment.For example, by acid,
The modes such as alkali, deionized water ultrasonic cleaning clean selected silicon wafer.
Sub-step S1012 carries out phosphorus diffusion to the one side of selected silicon wafer to form the area N 110.
Specifically, at present during making the area N 110, the mode for generalling use the diffusion of paper source is carried out, however, it is contemplated that
The problem of junction depth consistency difference after to the diffusion of paper source, therefore using the expansion that silicon wafer is placed in 1150 DEG C~1250 DEG C in the present embodiment
The gas for dissipating in furnace, and being passed through carrying liquid phosphorus source carries out the mode of 2.5 hours of pre-deposition and forms the area N 110.Wherein, due to
The gas progress ion implanting for carrying liquid source is passed through in diffusion furnace, obtained material junction depth is stablized, and consistency is preferable, therefore
The area N 110 obtained by this method can make surface square resistance less than 0.1 Ω/mouth.
Meanwhile after forming the area N 110, it is also necessary to the area N 110 be carried out impurity cleaning, interfered with impurity at row.Wherein, originally
Embodiment is carried out using wet type wafer sand ejector to 110 sandblasting of the area N except impurity cleans, of course, in some other embodiments
In, impurity cleaning can also be carried out in other manners, and the present embodiment does not do any restriction to this.
Sub-step S1013 is diffused propulsion in the silicon wafer.
In the present embodiment, it is also necessary to propulsion is diffused to the area N 110 of silicon wafer, after the present embodiment is used to pre-deposited
Silicon wafer in 1200 DEG C~1250 DEG C diffusion furnaces by phosphorus source be diffused propulsion in the way of be doped.
Sub-step S1014 is diffused post-processing to the silicon wafer.
Wherein, during being doped, it is possible that the phenomenon that silicon chip surface generates oxide layer, therefore also need
Post-processing is diffused to silicon wafer.Specifically, by separating silicon wafer with acid soak, deionized water ultrasonic cleaning, to reach
Remove the effect of surface oxide layer.
Sub-step S1015 carries out boron to the another side of the selected silicon wafer and spreads to form the area P 120.
Similar to the production mode in the area N 110, the present embodiment is using by treated, silicon wafer is placed in 1150 DEG C~1250 DEG C
Diffusion furnace in, be passed through and carry the gas of liquid boron source and be diffused the mode to form the area P 120, so that the surface square electricity of boron
Resistance is less than 0.1 Ω/mouth.Meanwhile sandblasting is still carried out using wet type wafer sand ejector and removes impurity treatment.
Sub-step S1016, by magnetron sputtering deposit platinum layer and spread in the way of obtain platinum diffusion layer.
For the performance prioritization scheme of reverse recovery time: platinum expansion is the fast process for restoring most critical in chip manufacturing, platinum
The concentration and uniformity of diffusion directly affect the fast reverse recovery characteristic for restoring chip.Diffusion of the platinum in silicon, it is considered that
It is to decompose diffusion way with clearance-type-displacement to carry out, and the diffusion coefficient of this flooding mechanism is the function of temperature, i.e., it is warm
Degree is higher, and diffusion coefficient is bigger.Solid solubility variation with temperature of the platinum in silicon is more violent simultaneously, as the temperature rises,
Solid solubility significantly increases.It is therefore desirable to which suitable diffusion way is selected to carry out platinum diffusion, traditional technique generally uses coating liquid
The mode of state platinum source or evaporation coating carries out platinum layer coating.Wherein, the diffusion effect after coating liquid platinum source is poor, directly results in
Reverse recovery time distribution is discrete, although and platinum layer uniformity that evaporation coating mode obtains is preferable, the knot of film and substrate
It is poor with joint efforts.
In view of this, in the present embodiment, platinum layer deposition is carried out by the way of magnetron sputtering, which passes through will be high-purity
Platinum target ground connection is used as cathode, and substrate (silicon wafer) has positive potential as anode, under high voltage electric field effect, in vacuum chamber
Argon gas generates highdensity cationic (Ar+) after glow discharge, and Ar+ is strongly attracted to the cathode and high velocity bombardment of target
Platinum target sputters out pt atom, these pt atoms sputtered out have certain kinetic energy, and penetrate along certain direction
To substrate, to realize platinum layer uniform deposition on substrate, being uniformly distributed for platinum layer is then realized by diffusion again, it is final
Diffusion effect it is uniform, reverse recovery time consistency is preferable.In addition, because diffusion temperature has direct shadow to reverse recovery time
It rings, by multiple comparative experiments, suitable diffusion temperature has finally been determined, stablize reverse recovery time in 60~100ns model
In enclosing.
Sub-step S1017 makes annealing treatment the silicon wafer after the formation platinum diffusion layer, and is cleaned by ultrasonic, with
Form the fast recovery diffusion substrate.
In order to enable it is more uniform to diffusion layer distribution, in the present embodiment, pure oxygen need to be also passed through in diffusion furnace to institute
Silicon wafer is stated to be made annealing treatment.Also, after annealing, there may be impurity on silicon wafer, therefore the present embodiment also needs
To treated, silicon wafer is cleaned by ultrasonic.
Sub-step S102 carries out double spread and drying and processing to the fast recovery diffusion substrate.
Control corrosion rate direction in corrosion process in order to control fast recovery diffusion substrate, prevents non-corrosive region to be corroded,
In the present embodiment, the method used carries out double spread for the surface in the area N 110 and the area P 120 simultaneously, and at 125 DEG C
It is toasted 30 minutes in baking oven, to form colloid protective layer 130.
Step S103 precuts to form groove the presetting size in the fast recovery diffusion substrate after gluing
150, wherein the presetting size includes presetting width and presetting depth.
For the ease of being cut into multiple fast recovery chips, needs to corrode multiple grooves 150 out, carried out with along groove 150
Cutting.But the time generally existing by the way of directly etching is long at present, corrosion area is big, the fast recovery core resulted in
The table top of piece is smaller.Meanwhile traditional performance prioritization scheme for forward voltage drop are as follows: due to chip table size and positive pressure
Inversely, therefore in the processing procedure for restoring chip fastly, can be reached by increasing chip table size reduces positive pressure to drop
The purpose of drop.But traditional photoetching process is used, needs to increase mesa dimensions, general fashion is to reduce photoetching lines, due to remaining
Amount is smaller, and the controlled amounts of mesa dimensions are fairly limited.
In view of this, referring to Fig. 3, in the present embodiment, the present invention passes through the work that blade 140 precut+corrodes on a small quantity
Skill replaces photoetching+corrosion traditional handicraft.I.e. in the face silicon wafer P, cutting-up goes out the groove 150 of one fixed width, carries out on this basis short
The chemical attack of time can obtain the channel of depth desired and width.Specific method is first to be cut into groove with blade 140
150, then the silicon wafer of well cutting is subjected to nitration mixture and corrodes certain time, groove 150 after corrosion is deep-controlled at 125~130 μm.
Wherein, presetting width provided in this embodiment is 100~120 μm, and presetting depth is 80~100 μm, preheating setting time 4
~5min.It of course, may be other values for presetting width, depth and time in some other embodiments,
The present embodiment does not do any restriction to this.
It is to be appreciated that two kinds of techniques corrode same depth, the etching time that blade 140 precuts technique at least shortens
50%, due to the reduction of etching time, 150 width of groove is obviously reduced, and the effective area of chip obviously increases.Simultaneously as
Powerful chip has a corresponding requirement to cut lengths, main content of the test be determining suitable cut lengths, depth of cut,
Cutting width and etching time.
Step S104 carries out cleaning and passivation protection to the groove 150 after the corrosion, and makes each institute by metallization
It states the fast surface for restoring chip and forms Ohmic contact.
After corrosion, two-sided gluing will be ineffective, needs to carry out processing of removing photoresist to fast diffusion substrate of restoring at this time, with
Aspect carries out subsequent Passivation Treatment.Further, the present embodiment is removed photoresist processing using carrying out silicon wafer corrode to steep acid, then
The mode for carrying out RCA cleaning carries out cleaning of removing photoresist.
Further, after being corroded, multiple diode P-N junctions out can be corroded, for protection diode P-N junction,
In the present embodiment, protected by the way of glassivation processing.Specifically, corroding diode P-N junction surface painting out
It is covered with glass powder paste, then under conditions of more than 800 degrees Celsius, sinters glass into, and then the passivation for forming diode P-N junction is protected
Sheath.
Also, nickel layer in the present embodiment, is plated on the two sides of silicon wafer using chemical method, so that nickel is formed ohm with silicon and connects
Touching, to prepare metal ohmic contact electrode in the area N 110 and the area P 120.
Step S105 is cut according to the groove 150 after the corrosion, to form multiple fast recovery chips.
The cutting separation of chip is carried out according to the chip size that is formed after corrosion, and then multiple fast recoveries after being cut
Chip.
By above-mentioned manufacture craft, can make maximal integer mass flow electric current IOM 3A~5A, breakdown reverse voltage VBR >=
1200V, forward voltage drop VF≤1.0V, reverse leakage current IR≤1 μ A, reverse recovery time TRR75ns~150ns.
It is to be appreciated that having faster reverse recovery time using GPP chip made from this method, and when Reverse recovery
Between Relatively centralized have more excellent switching characteristic compared with similar products.In addition forward voltage drop is 1000mV, with similar product
1250mV compare, there is smaller forward conduction to be lost, while having stronger anti-positive surge capacity.
In conclusion the present invention provides a kind of fast recovery chip manufacture methods, wherein deposit platinum layer by magnetron sputtering
The mode being diffused again makes fast recovery diffusion substrate, then to fast diffusion substrate of restoring according to presetting size progress pre-cut
Cut to form groove, wherein presetting size includes presetting width and presetting depth, then to groove according to it is presetting when
Between corroded, with formed corrosion after groove, wherein diffusion substrate is separated into multiple fast recovery cores interconnected by groove
Piece, then cleaning and passivation protection are carried out to the groove after corrosion, and form each fast surface for restoring chip by metallization
Ohmic contact, the last groove according to after corrosion is cut, to form multiple fast recovery chips.Due to provided by the invention fast
Restoring chip manufacture method is to deposit by way of platinum layer is diffused again to carry out platinum diffusion magnetron sputtering, chip it is anti-
The short and Relatively centralized to recovery time.It needs first to carry out pre-cut additionally, due to fast recovery chip manufacture method provided by the invention
It cuts, is then corroded, therefore corroded by the groove of presetting size, it is deep that corrosion can be reached within the shorter time
Degree, so it is smaller for the width of corrosion, and the table top for the fast recovery chip being cut into is larger.Due to restoring the table top ruler of chip fastly
Very little and forward voltage drop inversely, therefore by way of increasing the fast table top for restoring chip, can reach reduction forward direction pressure
The effect of drop.It should be noted that, in this document, the relational terms of such as " first " and " second " or the like are used merely to one
A entity or operation with another entity or operate distinguish, without necessarily requiring or implying these entities or operation it
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to
Cover non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or setting
Standby intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in the process, method, article or apparatus that includes the element.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any to repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.It should also be noted that similar label and letter exist
Similar terms are indicated in following attached drawing, therefore, once being defined in a certain Xiang Yi attached drawing, are then not required in subsequent attached drawing
It is further defined and explained.
Claims (8)
1. a kind of fast restore chip manufacture method, which is characterized in that the fast recovery chip manufacture method includes:
It is deposited magnetron sputtering and makes fast recovery diffusion substrate by way of platinum layer is diffused again；
The fast recovery diffusion substrate is precut according to presetting size to form groove, wherein described presetting
Size includes presetting width and presetting depth；
The groove is corroded according to preheating setting time, to form the groove after corrosion, wherein the groove is by the expansion
Scattered substrate is separated into multiple fast recovery chips interconnected；
Cleaning and passivation protection are carried out to the groove after the corrosion, and each fast table for restoring chip is made by metallization
Face forms Ohmic contact；
It is cut according to the groove after the corrosion, to form multiple fast recovery chips.
2. fast recovery chip manufacture method as described in claim 1, which is characterized in that described to deposit platinum layer by magnetron sputtering
The mode being diffused again makes fast the step of restoring diffusion substrate and includes:
Phosphorus diffusion is carried out to form the area N to the one side of selected silicon wafer；
Propulsion is diffused in the silicon wafer；
Boron is carried out to the another side of the selected silicon wafer to spread to form the area P；
By magnetron sputtering deposit platinum layer and spread in the way of obtain platinum diffusion layer；
Silicon wafer after the formation platinum diffusion layer is made annealing treatment, and is cleaned by ultrasonic, is expanded with forming the fast recovery
Dissipate substrate.
3. as claimed in claim 2 fast restore chip manufacture method, which is characterized in that the one side of described pair of selected silicon wafer into
Row phosphorus diffusion includes: the step of the area N to be formed
The silicon wafer is placed in 1150 DEG C~1250 DEG C of diffusion furnace, and is passed through the gas for carrying liquid phosphorus source, described
The one side of silicon wafer forms the area N；
Impurity cleaning is carried out to the one side in the area N of formation.
4. as claimed in claim 2 fast restore chip manufacture method, which is characterized in that described pair of selected silicon wafer it is another
Carry out boron diffusion on one side to be formed includes: the step of the area P
The silicon wafer being diffused after promoting is placed in 1150 DEG C~1250 DEG C of diffusion furnace, and is passed through and carries liquid boron source
Gas, with the another side of the silicon wafer formed the area P；
Impurity cleaning is carried out to the one side in the area P of formation.
5. fast recovery chip manufacture method as claimed in claim 2, which is characterized in that in the one side of described pair of selected silicon wafer
Before carrying out the step of phosphorus diffusion is to form the area N, the fast recovery chip manufacture method further include:
Chemical cleaning is carried out to the surface of selected silicon wafer.
6. fast recovery chip manufacture method as claimed in claim 2, which is characterized in that form the platinum diffusion layer at described pair
Silicon wafer afterwards is made annealing treatment, and is cleaned by ultrasonic, the step of to form the fast recovery diffusion substrate after, it is described fast
Restore chip manufacture method further include:
Double spread and drying and processing are carried out to the fast recovery diffusion substrate.
7. fast recovery chip manufacture method as described in claim 1, which is characterized in that the presetting width is 100~120
μm, the presetting depth is 80~100 μm, and the preheating setting time is 4~5min.
8. as described in claim 1 fast restore chip manufacture method, which is characterized in that the groove to after the corrosion into
Row was cleaned with the step of passivation protection
In the multiple fast P-N junction surface coating glass slurry for restoring chip interconnected, and the glass powder paste is burnt
Form glass, to form passivation protection layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113223944A (en) * | 2021-03-31 | 2021-08-06 | 青岛惠科微电子有限公司 | Manufacturing method and manufacturing equipment of fast recovery chip and fast recovery chip |
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