CN109637997A - 半导体装置封装和其制造方法 - Google Patents

半导体装置封装和其制造方法 Download PDF

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Publication number
CN109637997A
CN109637997A CN201811167799.8A CN201811167799A CN109637997A CN 109637997 A CN109637997 A CN 109637997A CN 201811167799 A CN201811167799 A CN 201811167799A CN 109637997 A CN109637997 A CN 109637997A
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electrical contact
bare die
redistribution layer
rdl
semiconductor device
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CN109637997B (zh
Inventor
方绪南
庄淳钧
叶勇谊
李明锦
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

半导体装置封装包括第一重布层(RDL)、第一裸片、第二裸片、第二RDL和封装体。第一裸片设置在第一RDL上并且电连接到第一RDL。第一裸片具有第一电性触点。第二裸片设置在第一RDL上并且电连接到第一RDL。第二裸片具有第一电性触点。第二RDL被第一RDL包围。第二RDL具有电连接到第一裸片的第一电性触点的第一电性触点和电连接到第二裸片的第一电性触点的第二电性触点。第二RDL的第一电性触点的尺寸大于第二RDL的第二电性触点的尺寸。

Description

半导体装置封装和其制造方法
技术领域
本公开总体涉及半导体装置封装，更具体地，本公开涉及包括内插器的半导体装置封装和其制造方法。
背景技术
在传统的2.5或3维半导体封装中，通常使用硅通孔(TSV)内插器来实现不同芯片之间的细线或细间距连接。然而，TSV结构可能增加制造半导体封装的成本或难度。此外，TSV内插器的导电压焊点之间具有均匀的尺寸或间距，并且可能不支持具有不同尺寸的导电压焊点的芯片之间的连接。
发明内容
在一个方面，根据一些实施例，半导体装置封装包括第一重布层(RDL)、第一裸片、第二裸片、第二RDL和封装体。第一裸片设置在第一RDL上并且电连接到第一RDL。第一裸片具有第一电性触点。第二裸片设置在第一RDL上并且电连接到第一RDL。第二裸片具有第一电性触点。第二RDL被第一RDL包围。第二RDL具有电连接到第一裸片的第一电性触点的第一电性触点和电连接到第二裸片的第一电性触点的第二电性触点。第二RDL的第一电性触点的尺寸大于第二RDL的第二电性触点的尺寸。封装体设置在第一RDL上并覆盖第一裸片和第二裸片。
在另一方面，根据一些实施例，制造半导体装置封装的方法包括：提供载体；在载体上设置互连结构；在载体上形成至少部分地包围互连结构的重布层(RDL)；在RDL和互连结构上设置第一裸片和第二裸片；以及在RDL上形成封装体以覆盖第一裸片和第二裸片。
在又一方面，根据一些实施例，制造半导体装置封装的方法包括：提供载体；在载体上设置第一裸片和第二裸片；形成覆盖第一裸片和第二裸片的封装体；去除载体以暴露第一裸片和第二裸片；在第一裸片和第二裸片上设置互连结构，其中互连结构的第一电性触点电连接到第一裸片，互连结构的第二电性触点电连接到第二裸片；以及形成包围互连结构的第一重布层(RDL)。
附图说明
当结合附图阅读时，从以下详细描述中可以最好地理解本公开的各方面。应注意，各种特征可能未按比例绘制，并且在附图中，为了清楚起见，可任意增加或减小所描绘特征的尺寸。
图1A示出了根据本发明的一些实施例的半导体装置封装的截面图。
图1B示出了根据本公开的一些实施例的半导体装置封装的截面图。
图1C示出了根据本公开的一些实施例的半导体装置封装的截面图。
图1D示出了根据本公开的一些实施例的半导体装置封装的截面图。
图1E示出了根据本公开的一些实施例的半导体装置封装的截面图。
图2A、图2B、图2C、图2D、图2E和图2F是根据本公开的一些实施例的在各个阶段制造的桥内插器的截面图。
图3A、图3B、图3C、图3D、图3E、图3F、图3G、图3H、图3I、图3J和图3K是根据本公开的一些实施例的在各个阶段制造的半导体装置封装的截面图。
图4A、图4B、图4C、图4D、图4E、图4F、图4G、图4H、图4I和图4J是根据本公开的一些实施例的在各个阶段制造的半导体装置封装的截面图。
图5A、图5B、图5C、图5D、图5E、图5F、图5G、图5H、图5I和图5J是根据本公开的一些实施例的在各个阶段制造的半导体装置封装的截面图。
图6A、图6B、图6C、图6D、图6E、图6F、图6G、图6H、图6I、图6J、图6K和图6L是根据本公开的一些实施例的在各个阶段制造的半导体装置封装的截面图。
图7A、图7B、图7C、图7D、图7E、图7F、图7G和图7H是根据本公开的一些实施例的在各个阶段制造的半导体装置封装的截面图。
图8A、图8B、图8C和图8D是根据本公开的一些实施例的在各个阶段制造的半导体装置封装的截面图。
在整个附图和详细描述使用共用的附图标记来指示相同或相似的元件。从以下结合附图的详细描述中将更容易理解本公开。
具体实施方式
根据本公开的一些实施例，通过用硅桥内插器(硅桥内插器具有重布层(RDL)，重布层具有根据不同裸片的布置而分配的不同尺寸的压焊点以用于裸片之间的互连)替换半导体封装中的TSV内插器，半导体封装的制造可以更具成本效益和灵活性。
图1A示出了根据本公开的一些实施例的半导体装置封装1a的截面图。
半导体装置封装1a包括重布层(RDL)10、互连结构(或RDL)20、半导体裸片30和40、封装体50、基部60和连接元件70。
半导体裸片30和40设置在RDL 10上。半导体裸片30和半导体裸片40电连接到RDL10。互连结构20被RDL 10包围或嵌入RDL 10中，并且具有与RDL 10接触的侧壁20s。互连结构20电连接到半导体裸片30和半导体裸片40。互连结构20可以称为桥内插器。
半导体裸片30和40中的每一个可以包括多个半导体装置，例如但不限于通过裸片互连结构互连在一起成为功能电路从而形成集成电路的晶体管、电容器和电阻器。根据若干不同实施例，半导体裸片30和40中的每一个可以是任何合适的集成电路器件，包括但不限于微处理器(例如，单核或多核)、存储器装置、芯片组、图形装置或特定应用集成电路(ASIC)。在一些实施例中，半导体裸片30是存储器，并且半导体裸片40是ASIC。
半导体裸片30具有电性触点32。电性触点32电连接到RDL 10的电性触点12和互连结构20的电性触点22。半导体裸片40具有电性触点42。电性触点42电连接到RDL 10的电性触点14和互连结构20的电性触点24。
在图1A所示的实施例中，半导体裸片30的电性触点32通过RDL 10的电性触点12连接到互连结构20的电性触点22。在另一实施例中，RDL 10的电性触点12可以省略，并且半导体裸片30的电性触点32可以直接连接到互连结构20的电性触点22。在图1A所示的实施例中，半导体裸片40的电性触点42通过RDL 10的电性触点14连接到互连结构20的电性触点24。在另一实施例中，RDL 10的电性触点14可以省略，并且半导体裸片40的电性触点42可以直接连接到互连结构20的电性触点24。
在一些实施例中，半导体裸片30的电性触点32的尺寸(例如，宽度或直径)不同于半导体裸片40的电性触点42的尺寸。例如，半导体裸片30的电触点32的尺寸可以大于半导体裸片40的电性触点42的尺寸。半导体裸片30的电性触点32的尺寸和/或半导体裸片40的电性触点42的尺寸可以小于2μm，例如，大约0.4μm。在一些实施例中，RDL 10的电性触点12的尺寸不同于RDL 10的电性触点14的尺寸。例如，RDL 10的电性触点12的尺寸可以大于RDL10的电性触点14的尺寸。在一些实施例中，互连结构20的电性触点22的尺寸不同于互连结构20的电性触点24的尺寸。例如，互连结构20的电性触点22的尺寸可以大于互连结构20的电性触点24的尺寸。互连结构20的电性触点22的尺寸和/或互连结构20的电性触点24的尺寸可以小于2μm，例如，大约0.4μm。在一些实施例中，互连结构20的电性触点22的尺寸对应于半导体裸片30的电性触点32的尺寸。在一些实施例中，互连结构20的电性触点24的尺寸对应于半导体裸片40的电性触点42的尺寸。如图1A所示，互连结构20可以具有与电性触点22和24相对地面向的电性触点26和28。互连结构20可以具有包围电性触点22、24、26和28的绝缘材料或者介电材料。互连结构20可以具有电连接电性触点22、24、26和/或28的导电结构(例如，导电迹线、线、过孔或柱)。
半导体裸片30可以具有多个电性触点32。半导体裸片40可以具有多个电性触点42。半导体裸片30的电性触点32的间距可以大于半导体裸片40的电性触点42的间距。互连结构20可以具有多个电性触点22和多个电性触点24。电性触点22的间距可以大于电性触点24的间距。互连结构20的电性触点22的间距可以对应于半导体裸片30的电性触点32的间距。互连结构20的电性触点24的间距可以对应于半导体裸片40的电性触点42的间距。互连结构20可以在半导体裸片30的电性触点32和半导体裸片40的电性触点42之间提供细线或细间距连接。
半导体裸片30具有电连接到RDL 10的电性触点16的电性触点34。半导体裸片40具有电连接到RDL 10的电性触点18的电性触点44。电性触点34的尺寸可以与半导体裸片30的电性触点32的尺寸相同或不同。电性触点44的尺寸可以与半导体裸片40的电性触点42的尺寸相同或不同。RDL 10的电性触点16的尺寸和/或电性触点18的尺寸可以与第一RDL 10的电性触点12的尺寸和/或电性触点14的尺寸相同或不同。例如，RDL 10的电性触点16的尺寸和/或电性触点18的尺寸可以大于第一RDL 10的电性触点12的尺寸和/或电性触点14的尺寸。
RDL 10可以包括但不限于例如单层结构或多层结构。RDL 10可以包括但不限于例如导电过孔、迹线或压焊点。
基部60设置在互连结构20的表面201上。基部60与互连结构20接触。基部60的侧壁60s与RDL 10接触。基部60至少部分地被RDL 10包围。如图1A所示，基部60的上部被RDL 10覆盖，并且基部60的下部突出超过RDL 10。基部60的下部(或突出部分)的厚度T1可以等于或小于8微米(μm)。基部60的上部的厚度T2可以大于8μm。在一些实施例中，基部60的下部的厚度T1可以大于8μm。基部60的上部的厚度T2可以等于或小于8μm。基部60的表面601从RDL10露出。基部60的侧壁60s的一部分从RDL 10露出。在一些实施例中，基部60的突出部分可以便于半导体装置封装1a的散热。在一些其他实施例中，基部60不突出超过RDL 10，并且表面601与RDL 10的表面101共面。在一些实施例中，基部60包括硅。基部60可以增加半导体装置封装1a的整体结构强度。基部60和互连结构20可以一起形成桥内插器。
封装体50设置在RDL 10上并覆盖半导体裸片30和40。封装体50封装半导体裸片30和40。封装体50可包括但不限于树脂和颗粒(或填料)。
连接元件70设置在RDL 10的表面101上。连接元件70电连接到RDL 10中的导线、迹线、过孔或柱。连接元件70可以包括焊料。
图1B示出了根据本公开的一些实施例的半导体装置封装1b的截面图。半导体装置封装1b类似于半导体装置封装1a，具有下面描述的一些差异。
省略了图1A中的基部60。表面201被RDL 10覆盖。RDL 10具有电连接到互连结构20的电性触点26的导体(例如，导电迹线、线、过孔或柱)13和电连接到互连结构20的电性触点28的导体15。导体13和15可以通过互连结构20电连接到半导体裸片30和/或半导体裸片40。导体13和15从RDL 10的表面101露出，并且可以用作半导体装置封装1b的输入/输出接口。半导体装置封装1b可以比半导体装置1a薄。半导体裸片30的电性触点32和半导体裸片40的电性触点42分别连接到电性触点22和电性触点24。互连结构20可以在半导体裸片30的电性触点32和半导体裸片40的电性触点42之间提供细线或细间距连接。半导体裸片30的电性触点32和半导体裸片40的电性触点42可具有不同的尺寸。
图1C示出了根据本公开的一些实施例的半导体装置封装1c的截面图。半导体装置封装1c类似于半导体装置封装1b，具有下面描述的一些差异。
半导体裸片80设置在RDL 10的导体13和15上。半导体裸片80可以具有与半导体裸片30和40类似的特征。半导体裸片80具有电连接到RDL 10的导体13和15的导体(例如，导电压焊点或凸块)82。半导体裸片80的导体82可以电连接到互连结构20的电性触点26和/或互连结构20的电性触点28。半导体裸片80通过互连结构20电连接到半导体裸片30和/或半导体裸片40。半导体裸片80的导体82被底部填充物85包围。底部填充物85设置在半导体裸片80和RDL 10之间。底部填充物85至少部分地被RDL10包围。半导体裸片80可以部分地被RDL10包围，这可以为连接元件70提供足够的间隔公差并且可以降低半导体装置封装1c的总高度。当连接元件70连接到另一电子装置时，连接元件70的足够间隔可以防止非接触问题。
图1D示出根据本发明的一些实施例的半导体装置封装1d的截面图。除了互连结构20和基部60由桥内插器90代替之外，半导体装置封装1d类似于半导体装置封装1a。
桥内插器90包括电连接到半导体裸片30的电性触点32和半导体裸片40的电性触点42的导体(例如，导电凸块或压焊点)92和94。导体92和94被底部填充物95包围。底部填充物95可以包括树脂和填料。
图1E示出了根据本公开的一些实施例的半导体装置封装1e的截面图。除了省略图1A中的基部60之外，半导体装置封装1e类似于半导体装置封装1a。
互连结构20的表面201从RDL 10露出。互连结构20的表面201与RDL 10的表面101共面。电性触点26和28从互连结构20的表面201露出。互连结构20的电性触点26和28可以为半导体装置封装1e提供外部电连接。例如，电性触点26和/或电性触点28可以连接到另一电子部件。
图2A、图2B、图2C、图2D、图2E和图2F是根据本公开的一些实施例的在各个阶段制造的桥内插器2f的截面图。为了更好地理解本公开的方面，已经简化了各个附图。
参照图2A，提供了基部60。重布层(RDL)R1设置在基部60上。图2A中的基部60与参照图1A描述和示出的基部60类似或相同。RDL R1包括介电材料D1和被介电材料D1包围的导电结构C1。
参照图2B，在RDL R1上形成停止层S1，并且在停止层S1上形成介电材料D2。停止层S1可以包括但不限于例如金属或其他合适的材料。停止层S1可以抵抗用于蚀刻或去除在其上形成的介电材料D2的蚀刻剂。可以通过沉积技术、涂覆技术或溅射技术形成停止层S1。可以通过涂覆技术形成介电材料D2。
参照图2C，在介电材料D2上形成图案化的掩模层(例如，光敏抗蚀剂(PR)层)M1。图案化的掩模层M1可以通过光刻技术形成。图案化的掩模层M1可以通过涂覆技术形成。图案化的掩模层M1可以通过曝光技术形成。图案化的掩模层M1可以通过显影技术形成。对从图案化的掩模层M1露出的电介质材料D2的部分执行曝光操作。
参照图2D，去除未被图案化的掩模层M1覆盖的停止层S1和介电材料D2。去除图案化的掩模层M1。可以通过蚀刻技术去除停止层S1和介电材料D2。可以通过第一蚀刻剂蚀刻停止层S1。可以通过第二蚀刻剂蚀刻介电材料D2。第一蚀刻剂可以与第二蚀刻剂不同。可以通过化学技术或光学技术去除图案化的掩模层M1。
参照图2E，晶种层SE1共形地形成在图2D所示的结构上。晶种层SE1可包括但不限于例如钛(Ti)、铜(Cu)或其他合适的金属、合金或导电材料。晶种层SE1可以通过沉积技术或溅射技术形成。
参照图2F，在晶种层SE1上形成导电材料CM1。去除导电材料CM1的一部分和晶种层SE1的一部分。导电材料CM1可包括但不限于例如铜(Cu)、铝(Al)或其他合适的金属或合金。导电材料CM1可以通过电镀技术、沉积技术或溅射技术形成。导电材料CM1可以被平坦化、减薄或研磨。可以通过化学机械平面化(CMP)技术、研磨技术、喷砂技术或蚀刻技术来平坦化、减薄或研磨导电材料CM1。可以平坦化、减薄或研磨导电材料CM1以形成参照图1A、图1B、图1C和图1E所描述和说明的互连结构20的电性触点22和24，其中电性触点22和24可以具有不同的尺寸。去除介电材料D2上的晶种层SE1以形成桥内插器2f。可以通过蚀刻技术去除晶种层SE1。图1A、图1B、图1C和图1E中的互连结构20的制造方法可以类似于内插器2f。
图3A、图3B、图3C、图3D、图3E、图3F、图3G、图3H、图3I、图3J和图3K是根据本公开的一些实施例的在各个阶段制造的半导体装置封装3k的截面图。为了更好地理解本公开的方面，已经简化了各个附图。
参照图3A，释放层RL设置在载体CR上。载体CR可包括玻璃。参照图3B，桥内插器B1设置在释放层RL上。桥内插器B1包括互连结构B11和基部B12。桥内插器B1与图2F中的桥内插器2f类似或相同。互连结构B11与参照图1A、图1B、图1C和图1E所描述和说明的互连结构20类似或相同。互连结构B11包括电性触点22和24。基部B12与参照图1A描述和说明的基部60类似或相同。桥内插器B1的一部分突出到释放层RL中。
参照图3C，在释放层RL上形成钝化层(例如PI)P1以覆盖桥内插器B1。钝化层P1可以通过涂覆技术形成。参照图3D，钝化层P1被图案化以限定多个开口O1。钝化层P1可以通过光学技术、机械技术或化学技术图案化。
参照图3E，在开口O1中形成导电材料(例如，Cu层)以形成重布层L1。在形成重布层L1时，可以在图案化的钝化层P1和通过开口O1暴露的释放层RL上形成晶种层，并且在晶种层上形成导电材料。可以去除晶种层的一部分和导电材料以形成RDL L1。RDL L1包围桥内插器B1。参照图3F，RDL L2形成在RDL L1上。电性触点12和14形成为与互连结构B11的电性触点22和24连接。
参照图3G，半导体裸片30和40设置在RDL L2上。半导体裸片30包括电连接到电性触点12和22的电性触点32。半导体裸片40包括电连接到电性触点14和24的电性触点42。参照图3H，半导体裸片30和40被封装体(或模塑料)50封装或覆盖。参照图3I，去除释放层RL和载体CR。RDL L1的导电压焊点CP1暴露。参照图3J，在导电压焊点CP1RDL L1上形成连接元件(例如焊料球或焊料凸块)70。参照图3K，执行分割操作以形成半导体装置封装3k。半导体装置封装3k可以与图1A的半导体装置封装1a类似或相同。
图4A、图4B、图4C、图4D、图4E、图4F、图4G、图4H、图4I和图4J是根据本公开的一些实施例的在各个阶段制造的半导体装置封装4j的截面图。为了更好地理解本公开的方面，已经简化了各个附图。
参照图4A，释放层RL设置在载体CR上。参照图4B，桥内插器B1设置在释放层RL上。桥内插器B1与图3B中的桥内插器B1类似或相同，并且包括互连结构B11和基部B12。参照图4C，在桥内插器B1上形成RDL L3。参照图4D，半导体裸片30和40设置在RDL L3上。参照图4E，半导体裸片30和40由封装体(或模塑料)50封装。
参照图4F，去除释放层RL和载体CR。桥内插器B1被露出。参照图4G，通过研磨技术和/或蚀刻技术去除桥内插器B1的基部B12和RDL L3的一部分。桥内插器B1的互连结构B11被露出。可以露出互连结构B11的一些电性触点。参照图4H，RDL L4形成在RDL L3上和桥内插器B1(或互连结构B11)上。RDL L4的一些导电压焊点CP2被露出。参照图4I，在RDL L4的导电压焊点CP2上形成连接元件(例如焊料球或焊料凸块)70。参照图4J，执行分割操作以形成半导体装置封装4j。半导体装置封装4j可以与图1B的半导体装置封装1b类似或相同。
图5A、图5B、图5C、图5D、图5E、图5F、图5G、图5H、图5I和图5J是根据本公开的一些实施例的在各个阶段制造的半导体装置封装5j的截面图。为了更好地理解本公开的方面，已经简化了各个附图。
参照图5A，释放层RL设置在载体CR上。参照图5B，桥内插器B1设置在释放层RL上。桥内插器B1与图3B中的桥内插器B1类似或相同，并且包括互连结构B11和基部B12。参照图5C，在桥内插器B1上形成RDL L3。参照图5D，半导体裸片30和40设置在RDL L3上。参照图5E，半导体裸片30和40由封装体(或模塑料)50封装。参照图5F，去除释放层RL和载体CR。桥内插器B1被露出。
参照图5G，通过蚀刻技术去除桥内插器B1的基部B12以形成凹部。互连结构B11被露出。参照图5H，RDL L4形成在RDL L3上和桥内插器B1(或互连结构B11)上。RDLL4包括从RDL L4的表面露出的导体17和导电压焊点CP2。参照图5I，在RDL L4的导电压焊点CP2上形成连接元件(例如焊料球或焊料凸块)70。半导体裸片80设置在RDLL4上。半导体裸片80包括电连接到RDL L4的导体17的导体(例如，导电压焊点或凸块)82。导体82被底部填充物85包围。底部填充物85至少部分地被RDL L4包围。参照图5J，执行分割操作以形成半导体装置封装5j。半导体装置封装5j可以与图1C的半导体装置封装1c类似或相同。
图6A、图6B、图6C、图6D、图6E、图6F、图6G、图6H、图6I、图6J、图6K和图6L是根据本公开的一些实施例的在各个阶段制造的半导体装置封装61的截面图。为了更好地理解本公开的方面，已经简化了各个附图。
参照图6A，释放层RL设置在载体CR上。参照图6B，半导体30和40设置在释放层上。参照图6C，半导体30和40由封装体50封装。参照图6D，去除释放层RL和载体CR。参照图6E，RDL L5形成在封装体50上并电连接到半导体30和40。导电结构C2被露出。参照图6F，桥内插器90形成在RDL L5上并且电连接到RDL L5。桥内插器90包括连接到导电结构C2的导电凸块CB。桥内插器90的导电凸块CB可以电连接到半导体30和40。
参照图6G，RDL L5和桥内插器90之间的空间填充有底部填充物UF以包围桥内插器90的导电凸块CB。参照图6H，钝化层P2形成在RDL L5上以覆盖桥内插器90。参照图6I，通过例如研磨技术去除钝化层P2的一部分以露出桥内插器90。可以通过研磨技术去除桥内插器90的一部分。桥内插器90的表面902可以与钝化层P2的表面P22共面。
参照图6J，RDL L6形成在RDL L5上以包围桥内插器90。参照图6K，连接元件(例如焊料球或焊料凸块)70形成在RDL L6的导电压焊点CP2上。参照图6L，执行分割操作以形成半导体装置封装61。半导体装置封装61可以与图1D的半导体装置封装1d类似或相同。
图7A、图7B、图7C、图7D、图7E、图7F、图7G和图7H是根据本公开的一些实施例的在各个阶段制造的半导体装置封装7h的截面图。为了更好地理解本公开的方面，已经简化了各个附图。
参照图7A，提供载体CR。通过诸如钻孔、激光或蚀刻技术等的合适技术在载体CR上形成空腔CV。参照图7B，释放层RL共形地设置在载体CR上(并且在空腔CV中)。释放层RL可以通过涂覆技术形成。参照图7C，桥内插器B1设置在空腔CV中。桥内插器B1包括互连结构B11和基部B12。参照图7D，RDL L7形成在载体CR上和桥内插器B1上。参照图7E，半导体裸片30和40设置在RDL L7上。参照图7F，半导体裸片30和40由封装体50封装。参照图7G，去除载体CR和释放层RL。参照图7H，连接元件(例如焊料球或焊料凸块)70形成在RDL L7的导电压焊点CP3上。形成半导体装置封装7h。半导体装置封装7h可以与图1A的半导体装置封装1a类似或相同。在一些实施例中，在半导体装置封装7h中基部B12的突出超过RDL L7的部分可以大于在半导体装置封装1a中基部60的突出超过RDL 10的部分。
图8A、图8B、图8C和图8D是根据本公开的一些实施例的在各个阶段制造的半导体装置封装8d的截面图。为了更好地理解本公开的方面，已经简化了各个附图。
图8A中的结构与图7G中的结构类似或相同。参照图8B，在RDL L7上形成封装体(或模塑料)55。封装体55包围并覆盖桥内插器B1。参照图8C，通过诸如研磨技术等的合适技术去除封装体55和桥内插器B1的基部B12的一部分。桥内插器B1的基部B12的表面B122与RDLL7的表面L72共面。参照图8D，在RDL L7的导电压焊点CP3上形成连接元件(例如焊料球或焊料凸块)70。形成半导体装置封装8d。半导体装置封装8d可以与图1A的半导体装置封装1a类似或相同。
如本文所用，术语“近似”、“基本上”、“大致”和“大约”用于描述和解释小的变化。当与事件或情况一起使用时，术语可以指其中事件或情况恰好发生的实例以及其中事件或情况发生为接近近似的实例。例如，当与数值结合使用时，术语可以指小于或等于该数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。例如，如果两个数值之间的差小于或等于所述值的平均值的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％，则可以认为两个数值“基本上”或“大约”相同。例如，“基本上”平行可以指相对于0°的角度变化范围小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于至±0.05°。例如，“基本上”垂直可以指相对于90°的角度变化范围小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于至±0.05°。
如果两个表面之间的位移不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，则可以认为两个表面是共面的或基本上共面的。如果表面的最高点和最低点之间的差异不大于5μm、不大于2μm、不大于1μm或不大于0.5μm，则表面可以被认为是平面的或基本上是平面的。
如本文所用，除非上下文另有明确规定，否则单数术语“一”、“一个”和“所述”可包括复数指示物。在一些实施例的描述中，设置在另一部件“上”或“之上”的部件可包以括其中前一个部件直接位于后一个部件上(例如，与其物理接触)的情况以及其中一个或多个中介部件位于前一个部件和后一个部件之间的情况。
虽然已经参照本公开的具体实施例描述和说明了本公开，但是这些描述和说明并不限制本公开。本领域技术人员可以清楚地理解，在不脱离由所附权利要求限定的本公开的真实精神和范围的情况下，可以进行各种改变，并且可以在实施例内替换等同的部件。示图可能不一定按比例绘制。由于制造过程中的变量等原因，本公开中的艺术再现与实际装置之间可能存在区别。可能存在未具体示出的本公开的其他实施例。说明书和附图应被视为说明性的而非限制性的。可以进行修改以使特定情况、材料、物质组成、方法或过程适应本公开的目的、精神和范围。所有这些修改都旨在落入所附权利要求的范围内。虽然已经参照以特定顺序执行的特定操作描述了本文公开的方法，但是可以理解，在不脱离本公开的教导的情况下，可以组合、细分或重新排序这些操作以形成等效方法。因此，除非在此具体指出，否则操作的顺序和分组不是本公开的限制。

Claims (15)

1.一种半导体装置封装，其包括：
第一重布层；
第一裸片，位于所述第一重布层上且电连接到所述第一重布层，所述第一裸片具有第一电性触点；
第二裸片，位于所述第一重布层上且电连接到所述第一重布层，所述第二裸片具有第一电性触点；
第二重布层，被所述第一重布层包围，所述第二重布层具有电连接到所述第一裸片的所述第一电性触点的第一电性触点，和电连接到所述第二裸片的所述第一电性触点的第二电性触点，所述第二重布层的所述第一电性触点的尺寸大于所述第二重布层的所述第二电性触点的尺寸；以及
封装体，位于所述第一重布层上且覆盖所述第一裸片和所述第二裸片。
2.如权利要求1所述的半导体装置封装，其中，所述第一裸片的所述第一电性触点的尺寸大于所述第二裸片的所述第一电性触点的尺寸。
3.如权利要求1所述的半导体装置封装，其中，所述第一重布层具有电连接在所述第一裸片的所述第一电性触点与所述第二重布层的所述第一电性触点之间的第一电性触点，和电连接在所述第二裸片的所述第一电性触点与所述第二重布层的所述第二电性触点之间的第二电性触点，且其中，所述第一重布层的所述第一电性触点的尺寸大于所述第一重布层的所述第二电性触点的尺寸。
4.如权利要求1所述的半导体装置封装，其中
所述第一裸片具有电连接到所述第一重布层的第三电性触点的第二电性触点；
所述第二裸片具有电连接到所述第一重布层的第四电性触点的第二电性触点；以及
所述第一重布层的所述第三电性触点和所述第四电性触点的尺寸分别大于所述第一重布层的所述第一电性触点和所述第二电性触点的尺寸。
5.如权利要求1所述的半导体装置封装，其中，所述第二重布层的侧壁接触所述第一重布层。
6.如权利要求1所述的半导体装置封装，其还包括接触所述第二重布层的基部。
7.如权利要求6所述的半导体装置封装，其中，所述基部中背向所述第二重布层的表面从所述第一重布层暴露。
8.如权利要求6所述的半导体装置封装，其中，所述基部的侧壁的至少一部分从所述第一重布层暴露。
9.如权利要求1所述的半导体装置封装，其中
所述第二重布层具有背向所述第一裸片且从所述第一重布层暴露的表面；以及所述第二重布层具有邻近于所述第二重布层的所述表面且从所述第二重布层的所述表面暴露的第三电性触点。
10.一种制造半导体装置封装的方法，其包括：
提供载体；
在所述载体上设置互连结构；
在所述载体上形成部分地包围所述互连结构的重布层；
在所述重布层和所述互连结构上设置第一裸片和第二裸片；以及
在所述载体上形成封装体以覆盖所述第一裸片和所述第二裸片。
11.如权利要求10所述的方法，其中
所述互连结构具有电连接到所述第一裸片的第一电性触点和电连接到所述第二裸片的第二电性触点；以及
所述第一电性触点的尺寸大于所述第二电性触点的尺寸。
12.如权利要求10所述的方法，其还包括移除所述载体以暴露所述互连结构的一部分。
13.如权利要求10所述的方法，其中，设置所述互连结构包括在所述载体中形成空腔，且设置所述互连结构于所述空腔中。
14.一种制造半导体装置封装的方法，其包括：
提供载体；
在所述载体上设置第一裸片和第二裸片；
形成覆盖所述第一裸片和所述第二裸片的封装体；
移除所述载体以暴露所述第一裸片和所述第二裸片；
在所述第一裸片和所述第二裸片上设置互连结构，其中，所述互连结构的第一电性触点电连接到所述第一裸片，且所述互连结构的第二电性触点电连接到所述第二裸片；以及
形成包围所述互连结构的第一重布层。
15.如权利要求14所述的方法，其中，所述互连结构的所述第一电性触点的尺寸大于所述互连结构的所述第二电性触点的尺寸。
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