CN109632791B - Method for evaluating bonding quality of semiconductor device bonding wire - Google Patents
Method for evaluating bonding quality of semiconductor device bonding wire Download PDFInfo
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- CN109632791B CN109632791B CN201811339293.0A CN201811339293A CN109632791B CN 109632791 B CN109632791 B CN 109632791B CN 201811339293 A CN201811339293 A CN 201811339293A CN 109632791 B CN109632791 B CN 109632791B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B19/00—Single-purpose machines or devices for particular grinding operations not covered by any other main group
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/01—Arrangements or apparatus for facilitating the optical investigation
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
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Abstract
The invention discloses a method for evaluating the bonding quality of a bonding wire of a semiconductor device, which comprises the following steps: manufacturing a sample through a semiconductor device; grinding the sample to obtain a central section of a bonding point of the bonding wire; observing the central section through a metallographic microscope to obtain a morphology result; testing the central section through a digital multipurpose meter and a probe station to obtain an electrical test result; and evaluating the bonding quality of the bonding wire according to the morphology result and the electrical test result. The evaluation method provided by the invention replaces the traditional bonding quality evaluation method with a narrow application range, is applicable to copper wires, can evaluate the bonding quality of the bonding wires from the aspects of morphology and electrical test, and ensures the accuracy of the evaluation result so as to improve the use reliability of the device.
Description
Technical Field
The invention relates to the technical field of component reliability, in particular to a method for evaluating the bonding quality of a bonding wire of a semiconductor device.
Background
The bonding lead of the semiconductor device mainly comprises three types of gold wires, aluminum wires and copper wires, and compared with the traditional gold wire material, the copper wire has advantages in cost, electric conduction, heat conduction and mechanical properties, and the growth rate of intermetallic compounds formed on a copper and aluminum bonding interface is slower than that of intermetallic compounds formed on a gold and aluminum bonding interface; meanwhile, a Kekender cavity similar to that existing between gold and aluminum interfaces is not easily formed on the copper and aluminum bonding interface, so that the mechanical property and the electrical property of a bonding point are enhanced, and the long-term reliability of the bonding point is improved. However, the copper wire material is more easily oxidized and has higher hardness, so that poor bonding is easily caused in the bonding process, and the poor bonding directly affects the use reliability of the copper wire bonding device, so that the quality of copper wire bonding needs to be evaluated.
In the prior art, the bonding quality of the bonding wire is mainly evaluated through a bonding strength test, however, the bonding quality of the copper wire cannot be accurately evaluated by the method. The traditional method for evaluating the bonding quality is narrow in application range, the method for evaluating the bonding quality of the gold wire and the aluminum wire is not suitable for the copper wire, the bonding quality of the copper wire cannot be accurately evaluated, and the use reliability of a device is directly influenced.
Disclosure of Invention
In view of the above, the present invention is directed to a method for evaluating bonding quality of a bonding wire of a semiconductor device, which can be widely applied to bonding wires of different materials and accurately evaluate the bonding quality of the bonding wire. Based on the above purpose, the invention provides a method for evaluating the bonding quality of a bonding wire of a semiconductor device. A method for evaluating the bonding quality of a bonding wire of a semiconductor device comprises the following steps: manufacturing a sample through a semiconductor device; grinding the sample to obtain a central section of a bonding point of the bonding wire; observing the central section through a metallographic microscope to obtain a morphology result; testing the central section through a digital multipurpose meter and a probe station to obtain an electrical test result; and evaluating the bonding quality of the bonding wire according to the morphology result and the electrical test result.
In some other embodiments, the sample preparation process comprises: and removing the outer lead of the semiconductor device and the heat dissipation plate, and then carrying out cold inlaying on the semiconductor device through a transparent resin powder material.
In other embodiments, the cold setting has a cure time of no less than 30 minutes.
In other embodiments, the direction of the ground sample is parallel to the outer leads before removal.
In some other embodiments, the milled sample comprises: a first grinding stage, a second grinding stage and a third grinding stage; the first grinding stage is to grind the sample by sand paper with the granularity of 600 meshes until the substrate of the sample is exposed; the second grinding stage is to grind the sample by sand paper with the granularity of 1200 meshes until the chip of the sample is exposed; the third grinding stage was to grind the sample by sandpaper with a grit of 2500 mesh to expose the central section.
In some other embodiments, the milled sample further comprises: a first polishing stage, a second polishing stage, a third polishing stage, and a fourth polishing stage; the first polishing stage is to polish the sample for 120s by silk with the granularity of 9 microns and alumina polishing solution with the diameter of 9 microns; the second polishing stage is to polish the sample for 90s by silk with the granularity of 3 mu m and alumina polishing solution with the diameter of 3 microns; the third polishing stage is to polish the sample for 60s by silk with the granularity of 1 micron and alumina polishing solution with the diameter of 1 micron; the fourth polishing stage is to polish the sample by lint and deionized water for 60 s.
In some other embodiments, the first polishing stage, the second polishing stage, the third polishing stage, and the fourth polishing stage rinse the sample with deionized water after polishing.
In some other embodiments, the bond site of the bonding wire includes: the chip bonding structure comprises a bonding ball and a chip bonding pad, wherein the bonding ball is connected with a chip through the chip bonding pad.
In some other embodiments, testing the center section with a digital multimeter and a probe station to obtain electrical test results comprises: the first probe of the probe station is connected with the central section of the bonding ball, and the second probe of the probe station is connected with the central section of the chip bonding pad; the diameter of the probe is not larger than the diameter of the bonding wire; and carrying out resistance value test on the central section through the digital multimeter.
In other embodiments, obtaining the topographical result by observing the central section with a metallographic microscope comprises: the metallographic microscope observation is in a bright field mode.
From the above, the method for evaluating the bonding quality of the bonding wire of the semiconductor device provided by the invention has the advantages that the center section of the bonding point of the bonding wire is obtained by a grinding method, and then metallographic observation, electrical test and the like are carried out on the center section.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for evaluating the bonding quality of a bonding wire of a semiconductor device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
The method for evaluating the bonding quality of the bonding wire of the semiconductor device provided by the embodiment, referring to fig. 1, includes:
step 101: manufacturing a sample through a semiconductor device;
step 102: grinding the sample to obtain a central section of a bonding point of the bonding wire;
step 103: observing the central section through a metallographic microscope to obtain a morphology result;
step 104: testing the central section through a digital multipurpose meter and a probe station to obtain an electrical test result;
step 105: and evaluating the bonding quality of the bonding wire according to the morphology result and the electrical test result.
The operation sequence of step 103 and step 104 is not intermodulation, that is, in the present invention, after the topography observation of step 103, the electrical test of step 104 can be performed. If the electrical test in step 104 is performed first, and then the topography observation in step 103 is performed, at this time, the electrical test in step 104 has a certain influence on the central profile, so that the topography observation result in step 103 is inaccurate.
In this embodiment, the sample preparation process includes: and removing the outer lead of the semiconductor device and the heat dissipation plate, and then carrying out cold inlaying on the semiconductor device through a transparent resin powder material.
Specifically, the removal of the outer leads and the heat sink plate in the sample preparation enables a good center profile to be obtained after grinding the sample, and the outer leads and the heat sink plate remaining in the sample can cause more impurities in the sample to affect the quality of the obtained center profile, thereby affecting the subsequent morphology result and electrical test result, and further affecting the bonding quality of the bonding wire to be evaluated.
Specifically, in the present embodiment, after removing the outer leads and the heat dissipation plate of the semiconductor device, the semiconductor device is injection-molded by a transparent resin powder material, and the curing time is not less than 30 minutes, so that the semiconductor device is completely cured and the fixing effect is better achieved, thereby preventing the sample from being unnecessarily damaged in the process of grinding the sample. In the sample preparation process, a hot damascene manner is not adopted, because the temperature required by the hot damascene is higher than that required by the cold damascene, the stress in the process is large, and the semiconductor device is easily damaged unnecessarily in the hot damascene process.
In this embodiment, the direction of the ground sample is parallel to the outer leads before removal. Wherein the direction of the outer lead needs to be recorded in advance by an operator before removal.
In this embodiment, the ground sample comprises: a first grinding stage, a second grinding stage and a third grinding stage; the first grinding stage is to grind the sample by sand paper with the granularity of 600 meshes until the substrate of the sample is exposed; the second grinding stage is to grind the sample by sand paper with the granularity of 1200 meshes until the chip of the sample is exposed; the third grinding stage was to grind the sample by sandpaper with a grit of 2500 mesh to expose the central section.
Specifically, the first grinding stage, the second grinding stage and the third grinding stage are sequentially performed in the grinding process, because the sample portions required to be displayed in the first grinding stage, the second grinding stage and the third grinding stage are finer and finer, and the granularity of the sand paper used in the first grinding stage, the second grinding stage and the third grinding stage is sequentially increased, so that finer portions of the sample can be ground.
Of course, in other embodiments of the present invention, the grinding stage is not limited to the first grinding stage, the second grinding stage and the third grinding stage, and other stages may be used to expose the relevant portion of the sample. Further, it is obvious that the granularity of the sand paper used in the first, second and third grinding stages is not limited to 600 mesh, 1200 mesh and 2500 mesh, respectively, but other mesh numbers that can expose the substrate, the chip and the central section of the sample, respectively.
The ground sample further includes: a first polishing stage, a second polishing stage, a third polishing stage, and a fourth polishing stage; the first polishing stage is to polish the sample for 120s by silk with the granularity of 9 microns and alumina polishing solution with the diameter of 9 microns; the second polishing stage is to polish the sample for 90s by silk with the granularity of 3 mu m and alumina polishing solution with the diameter of 3 microns; the third polishing stage is to polish the sample for 60s by silk with the granularity of 1 micron and alumina polishing solution with the diameter of 1 micron; the fourth polishing stage is to polish the sample by lint and deionized water for 60 s.
Specifically, in the polishing process, the first polishing stage, the second polishing stage, the third polishing stage and the fourth polishing stage are sequentially performed, because the polishing degree effect required by the first polishing stage, the second polishing stage, the third polishing stage and the fourth polishing stage is smaller and smaller, the silk granularity and the diameter of the alumina polishing solution required by the first polishing stage, the second polishing stage, the third polishing stage and the fourth polishing stage are smaller and smaller, and the polishing time is shorter and shorter, so that the polishing process of the sample is finer, and the polishing process cannot cause unnecessary damage to the sample.
Of course, in other embodiments of the present invention, the polishing stage in the grinding process is not limited to the first polishing stage, the second polishing stage, the third polishing stage and the fourth polishing stage, but may be other stages that can enable the sample to achieve the polishing effect. Furthermore, it is obvious that the particle sizes of the silk used in the first polishing stage, the second polishing stage and the third polishing stage are not limited to 9 μm, 3 μm and 1 μm, respectively, but may be other particle sizes that can make the sample finally achieve the polishing effect; the diameter of the alumina polishing solution is not limited to 9 microns, 3 microns and 1 micron, and can be other sizes which can enable the sample to achieve the final polishing effect; the polishing times of the first polishing stage, the second polishing stage, the third polishing stage and the fourth polishing stage were 120s, 90s and 60s, respectively. 60s, and other polishing time which can enable the sample to finally achieve the polishing effect.
In this embodiment, the first polishing stage, the second polishing stage, the third polishing stage, and the fourth polishing stage all rinse the sample with deionized water after polishing.
In this embodiment, the bonding point of the bonding wire includes: the chip bonding structure comprises a bonding ball and a chip bonding pad, wherein the bonding ball is connected with a chip through the chip bonding pad. Specifically, a bonding wire is connected to a chip through a chip pad, and a connection portion of the bonding wire to the chip, i.e., a bonding point. In this embodiment, the bonding method may also be a bonding method such as pressure bonding.
In this embodiment, the obtaining of the electrical test results by testing the center section with a digital multimeter and a probe station comprises: the first probe of the probe station is connected with the central section of the bonding ball, and the second probe of the probe station is connected with the central section of the chip bonding pad; the diameter of the probe is not larger than the diameter of the bonding wire; and carrying out resistance value test on the central section through the digital multimeter.
In this embodiment, observing the central section through a metallographic microscope to obtain a topographic result includes: the metallographic microscope observation is in a bright field mode. The metallographic microscope mainly adopts bright field observation, dark field observation and the like, and the bright field observation utilizes the illumination light to directly irradiate the surface of the sample to be measured and reflect the surface of the sample to be measured so as to observe the sample, thereby displaying various different tissue appearances of the sample more truly.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the invention, also features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity.
In addition, connections to the chip and the bond wire may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the invention. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present invention is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details are set forth in order to describe example embodiments of the invention, it will be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.
While the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other grinding stages may use the discussed embodiments.
The embodiments of the invention are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. A method for evaluating the bonding quality of a bonding wire of a semiconductor device is characterized by comprising the following steps:
manufacturing a sample through a semiconductor device;
grinding the sample to obtain a central section of a bonding point of the bonding wire; wherein the ground sample comprises: a first grinding stage, a second grinding stage and a third grinding stage; the first grinding stage is to grind the sample by sand paper with the granularity of 600 meshes until the substrate of the sample is exposed; the second grinding stage is to grind the sample by sand paper with the granularity of 1200 meshes until the chip of the sample is exposed; the third grinding stage is to grind the sample by using sand paper with the granularity of 2500 meshes until the central section is exposed;
the ground sample further includes: a first polishing stage, a second polishing stage, a third polishing stage, and a fourth polishing stage; the first polishing stage is to polish the sample for 120s by silk with the granularity of 9 microns and alumina polishing solution with the diameter of 9 microns; the second polishing stage is to polish the sample for 90s by silk with the granularity of 3 mu m and alumina polishing solution with the diameter of 3 microns; the third polishing stage is to polish the sample for 60s by silk with the granularity of 1 micron and alumina polishing solution with the diameter of 1 micron; the fourth polishing stage is to polish the sample by lint and deionized water for 60 s;
observing the central section through a metallographic microscope to obtain a morphology result;
testing the central section through a digital multipurpose meter and a probe station to obtain an electrical test result;
and evaluating the bonding quality of the bonding wire according to the morphology result and the electrical test result.
2. The method for evaluating the bonding quality of the bonding wire of the semiconductor device according to claim 1, wherein the fabricating the sample process comprises: and removing the outer lead of the semiconductor device and the heat dissipation plate, and then carrying out cold inlaying on the semiconductor device through a transparent resin powder material.
3. The method of claim 2, wherein the cold-damascene curing time is not less than 30 minutes.
4. The method of claim 2, wherein the grinding of the sample is performed in a direction parallel to the outer lead before removal.
5. The method of claim 1, wherein the first polishing stage, the second polishing stage, the third polishing stage, and the fourth polishing stage rinse the sample with deionized water after polishing.
6. The method of claim 1, wherein the bonding point of the bonding wire comprises: the chip bonding structure comprises a bonding ball and a chip bonding pad, wherein the bonding ball is connected with a chip through the chip bonding pad.
7. The method of claim 6, wherein the obtaining of electrical test results from testing the center profile with a digital multimeter and a probe station comprises: the first probe of the probe station is connected with the central section of the bonding ball, and the second probe of the probe station is connected with the central section of the chip bonding pad; the diameter of the probe is not larger than the diameter of the bonding wire; and carrying out resistance value test on the central section through the digital multimeter.
8. The method for evaluating the bonding quality of the bonding wire of the semiconductor device according to claim 1, wherein the observing the central section through a metallographic microscope to obtain a morphology result comprises: the metallographic microscope observation is in a bright field mode.
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