CN109546969A - Distort CMOS low-noise amplifier after one kind - Google Patents

Distort CMOS low-noise amplifier after one kind Download PDF

Info

Publication number
CN109546969A
CN109546969A CN201811268081.8A CN201811268081A CN109546969A CN 109546969 A CN109546969 A CN 109546969A CN 201811268081 A CN201811268081 A CN 201811268081A CN 109546969 A CN109546969 A CN 109546969A
Authority
CN
China
Prior art keywords
nmos transistor
source
gate
distortion
load
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811268081.8A
Other languages
Chinese (zh)
Inventor
郭本青
陈鸿鹏
王雪冰
陈俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201811268081.8A priority Critical patent/CN109546969A/en
Publication of CN109546969A publication Critical patent/CN109546969A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)

Abstract

The invention belongs to integrated circuit fields, specifically provide distortion CMOS low-noise amplifier after one kind, comprising: input stage (ML1With MR1), cascaded stages (ML2With MR2), rear distortion eliminate grade (M1aLWith M1aR) and resonant load, respectively from input stage input, amplified differential output signal is exported from cascaded stages radio-frequency differential signal respectively, and it is NMOS transistor of the work in strong inversion area that grade is eliminated in distortion, is connected to cascaded stages.The CMOS low-noise amplifier that distorts after the present invention can significantly improve the linearity of LNA, and obtain higher gain and lower noiseproof feature simultaneously.

Description

Distort CMOS low-noise amplifier after one kind
Technical field
The invention belongs to integrated circuit fields more particularly to a kind of low-noise amplifier designing techniques, specifically provide one kind Distort CMOS low-noise amplifier afterwards.
Background technique
The equal proportion reduction of complementary metal oxide semiconductor (CMOS) technique allows us to easily design low Noise, low-power consumption amplifier, however, the linearity of CMOS transistor but since supply voltage successively decreases the degeneration with mobility and Deteriorate, this challenge has expedited the emergence of several linearization techniques.
In the backtracking past, most effective linearization technique is multiple-gate transistor (MGTR) technology, such as document " T.W.Kim, B.- K.Kim,and K.-R.Lee,“Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors,”IEEE J.Solid- State Circuits, vol.39, no.1, pp.223-229, Jan.2004 ", as shown in Figure 1, the technology passes through in host crystal One in parallel works in weak inversion regime beside pipe, the auxiliary tube with positive third-order nonlinear optical coefficient, to offset the negative of supervisor Third-order nonlinear optical coefficient, and then increase in a wider bias voltage ranges linearity of circuit；Nevertheless, but Under high frequency, the interaction of second order nonlinear coefficient and input network usually limits the actual effect of the technology.Then, it improves Derivative superposition method be suggested, what it is to alleviate the contradiction, but with it is that input matching network structure becomes complicated, the linearity with Matching present fluctuation the phenomenon that.On the other hand, noise cancellation technique can also obtain the promotion effect of the linearity, such as document "Chen,Jun；Guo,Benqing；,A Highly Linear Wideband CMOS LNTA Employing Noise/ Distortion Cancellation and Gain Compensation,Circuits,Systems,and Signal Processing, VOL.36, NO.2,2017 " a kind of low-noise amplifier that noise is eliminated is disclosed, as shown in Fig. 2, wherein inputting The non-linear principle eliminated by similar noise of pipe is able to eliminate certainly；And the non-linear partial offset of secondary path transistor Current mirror transistor it is non-linear, to obtain the High Linear of 18dBm IIP3 on the whole；However, the circuit power consumption is big, it is 27mW, and circuit is the stacked structure of 4 transistors, so that circuit is difficult to work at low supply voltages, is not suitable for integrated Circuit equal proportion reduces the demand that supply voltage reduces.
Summary of the invention
It, can it is an object of the invention in view of the above technical defects, propose the CMOS low-noise amplifier that distorts after one kind The linearity of LNA is enough improved, and low-power consumption can be obtained simultaneously.
To achieve the above object, the technical solution adopted by the present invention are as follows:
Distort CMOS low-noise amplifier after one kind, comprising: input stage (ML1With MR1), cascaded stages (ML2With MR2), rear distortion Eliminate grade (M1aLWith M1aR) and resonant load, which is characterized in that
The cascaded stages include: NMOS tube ML2With NMOS tube MR2, the NMOS tube ML2With MR2Grid be all connected to power supply VDD, NMOS tube ML2With MR2Drain electrode pass through resonance circuit respectively and be connected to power supply VDD；
The input stage includes: NMOS tube ML1With NMOS tube MR1, capacitor CcLWith capacitor CcR, inductance Ls, wherein it is described NMOS tube ML1Drain electrode connect NMOS tube ML2Source electrode, source electrode connects as the anode+Vin of input signal, grid through biasing resistor Bias voltage VBais, NMOS tube MR1Drain electrode meet NMOS tube MR2Source electrode, source electrode passes through as the negative terminal-Vin of input signal, grid Biasing resistor meets bias voltage VBais, capacitor CcLIt is connected to NMOS tube ML1Source electrode and NMOS tube MR1Grid between, capacitor CcR It is connected to NMOS tube ML1Grid and NMOS tube MR1Source electrode between；NMOS tube ML1With NMOS tube MR1Source electrode pass through inductance LsAfter be grounded；
It includes: NMOS tube M that grade is eliminated in distortion after described1aLWith NMOS tube M1aR, grid capacitance and gate bias resistor, Wherein, the NMOS tube M1aLSource level be connected to NMOS tube ML2Source electrode, NMOS tube M1aRSource level be connected to NMOS tube MR2's Source electrode, the NMOS tube M1aLWith M1aRGrid pass through gate bias resistor respectively and be connected to bias voltage Vb, NMOS tube M1aLWith M1aRDrain electrode be connected and be connected to power supply VDD, the NMOS tube M1aLSource level M is connected to by grid capacitance1aRLeakage Grade, the NMOS tube M1aRSource level M is connected to by grid capacitance1aLDrain.
Further, the cascaded stages further include an inductance Ladd, the inductance LaddConnection and NMOS tube ML2Source electrode With NMOS tube MR2Source electrode between.
Further, the resonant load is by load inductance (LdL、LdR), load capacitance (CdL、CdR) and load resistance (RdL、RdR) constitute, wherein load inductance connect with load resistance after, composition resonant load in parallel with load capacitance again.
The beneficial effects of the present invention are:
The present invention provides distortion CMOS low-noise amplifier after one kind:
1, the present invention can significantly improve the linearity of LNA, and obtain higher gain and lower noise-induced simultaneously Energy.
2, distort technology after present invention use, does not influence circuit input matching；And auxiliary transistor is intersected using grid source Coupled structure, under the premise of maintaining nonlinear component certain, so that the mutual conductance of auxiliary tube reduces, conducive to the low-power consumption of circuit.
Detailed description of the invention
Fig. 1 is the circuit diagram of existing multiple-gate transistor (MGTR) technology.
Fig. 2 is the existing High Linear low-noise amplifier schematic diagram that principle is eliminated based on noise.
Fig. 3 is the schematic diagram of distortion CMOS amplifier circuit in low noise after one kind of the invention.
Fig. 4 is gain, noise and the input reflection coefficient knot of distortion CMOS amplifier circuit in low noise after one kind of the invention Fruit curve.
Fig. 5 is that distortion CMOS amplifier circuit in low noise is linearizing IIP3 result figure before and after the processing after the present invention is a kind of.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right The present invention is further elaborated.
The present embodiment provides the CMOS low-noise amplifiers that distorts after one kind, as shown in figure 3, the amplifier circuit is differential pair Claim structure, radio-frequency differential signal is respectively from differential pair tube M1(ML1With MR1) source electrode input, amplified differential output signal Respectively through differential pair tube M2(ML2With MR2) buffering, finally parallel resonance load (Ld、Cd、Rd) obtain differential output signal； Vb、VBiasFor pipe M1a(M1aLWith M1aR)、M1Bias voltage is provided；Specifically, the present invention is a kind of linearizes grid CMOS low noise altogether Amplifier circuit includes input stage (ML1With MR1), cascaded stages (ML2With MR2), rear distortion eliminate grade (M1aLWith M1aR) and resonance it is negative It carries.
Above-mentioned LNA (amplifier) circuit realizes that the distortion as additional device is eliminated using 0.18 μm of rf CMOS technology Grade M1aGrid source bias Vgs=0.7V, to provide linearisation effect；Under 1.8V supply voltage, the total bias current of chip is only For 5mA, and two auxiliary tube M1aTotal current be 45uA；Coupled capacitor CcLWith CcRIt is 5pF, bandwidth optimization resistance RdIt is 10 Ohm.LNA gain is given as shown in Figure 4, at centre frequency 6GHz, the gain of the LNA of linearization process has reached 21dB. Give noise figure as shown in Figure 5 as a result, at centre frequency, noise figure 2.5dB.Using constant amplitude double-tone 5.8GHz, The test signal of 5.81GHz, carrys out the linearity of artificial circuit；It is closed and it is possible to disconnect auxiliary tube M1a in the connection of v2 to emulate After closed linearization function the case where the linearity.As shown in figure 5, the IIP3 after linearisation has reached 16dBm, comparison is not assisted The case where pipe, the linearity improve 8.1dB.The above result shows that the LNA obtains the superior linearity and gain, it is suitble to high line Property degree application.
The raising of the linearity of above-mentioned low-noise amplifier is based on the technology that distorts after one kind: using work in strong inversion area Auxiliary NMOS tube to M1a, to eliminate the third-order non-linear electric current of total grid LNA and weaken second nonlinear electric current.It is cross-linked Auxiliary tube is played to capacitive source grid cross-coupling is used to the nonlinear multiplication effect of auxiliary tube itself, so that auxiliary tube It can work under low mutual conductance, to contribute low additional noise.In addition, by introducing an inductance Ladd, with cascade transistor The parasitic capacitance of source node forms resonance, and according to pipeline principle, the noise of cascade transistor non-linear passes through the node The suction ring rood of parasitic capacitance is to break, so as to ignore.
The LNA is considered as a total grid-and is total to grid dual-stage amplifier.Common-gate input stage provides input resistant matching, simultaneously The noise characteristic having had due to coupling (CCC) structure which employs capacitive cross.Cascade grade is then used to increase output Impedance and raising input and output isolation.At load resonant network, small resistance R is addeddSuitably to reduce resonant network product Prime factor obtains widening for bandwidth of operation.
By to node v2The impedance at place carries out small-signal analysis, with the presence of following resonant relationship, i.e.,
Here, Cgs2Cgs1aFor pipe M2、M1aGate-source parasitic capacitance., pass through LaddResonance effect so that v2At node Parasitic capacitance be absorbed, conducive to the improvement of high frequency performance.Again because of M2Source impedance it is low, make LaddResonant network have It is low to carry Q value, is widened conducive to the frequency band of circuit.In turn, it can be deduced that the voltage gain of LNA is
Wherein, gm1And gm2It is M1Grid mutual conductance, M2Grid mutual conductance, ZLIt is load resistance.As can be seen from the above equation, if inductance LaddResonance occurs with the equivalent parasitic capacitances at x node, the gain of LNA can improve.
Under conditions of input resistant matching, 1/Rs=2gm1, the additional noise factor expression of the auxiliary tube in LNA is
Wherein, α and γ is that biasing relies on parameter.Because of gm1a/gm1(being 0.03 in our design).Therefore noise system Several deteriorations can be ignored.In addition, because LaddIn the resonance effect of x node, M2It is approximately equivalent to a current buffer, no Noise can be generated.
On the other hand, because of LaddResonance at node x, so that M2It is equivalent to a current buffer, is not generated non-thread Property.Just because of this, the linearity of the LNA is mainly determined by common-gate input stage.Such as Fig. 3
Wherein, giAnd giaIt is M1And M1aI-V derivation coefficient (i takes 1,2,3).According to Circuit theory, v2With v1Relationship be v2=bv1, parameter b is positive value.In node X, i is used1Subtract i1a:
Because of auxiliary transistor M1aWith main transistor M1It all works in strong inversion area, has identical second order, three ranks non-thread Property polarity.Therefore, auxiliary transistor M is adjusted1aBias voltage and size, the Section 3 in formula can be allowed to eliminate. Similarly, Section 2 can also weaken, and then the linearity is improved.Furthermore, it is possible to find that the first item for representing fundamental frequency is certain Weaken in degree, i.e. the gain of LNA is weakened.Intuition is because Fundamental-frequency Current generates leakage by auxiliary tube. But because auxiliary tube uses capacitive cross coupled structure, current drain is extremely low, and bring gain loss is also that can neglect Slightly.
Similar principle, auxiliary transistor M1aIt is designed as the form of PMOS tube, emulation shows equally to also obtain linear The promotion effect of degree.But in semiconductor integrated circuit flow, there is a matching in NMOS/PMOS work in-process. NMOS, which is all made of, not as good as all transistors in hereinbefore circuit arrangement realizes the realization succinct, easy to produce of coming.Furthermore PMOS tube Has low mobility, it is meant that auxiliary transistor M1aPMOS tube design need to increase 2-3 times of size, corresponding parasitic capacitor It will increase, this is also unfavorable factor.It integrates, auxiliary transistor M1aNMOS tube be embodied as prioritization scheme.
The above description is merely a specific embodiment, any feature disclosed in this specification, except non-specifically Narration, can be replaced by other alternative features that are equivalent or have similar purpose；Disclosed all features or all sides Method or in the process the step of, other than mutually exclusive feature and/or step, can be combined in any way.

Claims (3)

1.一种后畸变CMOS低噪声放大器，包括：输入级(ML1与MR1)、级联级(ML2与MR2)、后畸变消除级(M1aL与M1aR)及谐振负载，其特征在于，1. A post-distortion CMOS low-noise amplifier, comprising: an input stage (M L1 and M R1 ), a cascade stage (M L2 and M R2 ), a post-distortion cancellation stage (M 1aL and M 1aR ) and a resonant load, which is characterized by, 所述级联级包括：NMOS管ML2与NMOS管MR2，所述NMOS管ML2与MR2的栅极均连接到电源VDD，NMOS管ML2与MR2的漏极分别通过谐振电路连接到电源VDD；The cascade stage includes: an NMOS transistor ML2 and an NMOS transistor MR2 , the gates of the NMOS transistors ML2 and MR2 are both connected to the power supply V DD , and the drains of the NMOS transistors ML2 and MR2 pass through the resonant circuit respectively connected to the power supply V DD ; 所述输入级包括：NMOS管ML1与NMOS管MR1、电容CcL与电容CcR、电感Ls，其中，所述NMOS管ML1的漏极连接NMOS管ML2的源极、源极作为输入信号的正端+Vin、栅极经偏置电阻接偏置电压VBais，NMOS管MR1的漏极接NMOS管MR2的源极、源极作为输入信号的负端-Vin、栅极经偏置电阻接偏置电压VBais，电容CcL连接于NMOS管ML1的源极与NMOS管MR1的栅极之间，电容CcR连接于NMOS管ML1的栅极与NMOS管MR1的源极之间；NMOS管ML1和NMOS管MR1的源极均通过电感Ls后接地；The input stage includes: NMOS transistor M L1 and NMOS transistor M R1 , capacitors C cL and C cR , and inductor L s , wherein the drain of the NMOS transistor M L1 is connected to the source and source of the NMOS transistor M L2 As the positive terminal +Vin of the input signal, the gate is connected to the bias voltage V Bais through the bias resistor, the drain of the NMOS transistor MR1 is connected to the source of the NMOS transistor MR2 , and the source is used as the negative terminal of the input signal -Vin, the gate The electrode is connected to the bias voltage V Bais through the bias resistor, the capacitor C cL is connected between the source of the NMOS transistor M L1 and the gate of the NMOS transistor M R1 , and the capacitor C cR is connected to the gate of the NMOS transistor M L1 and the NMOS transistor Between the sources of MR1 ; the sources of the NMOS transistor ML1 and the NMOS transistor MR1 are grounded through the inductor L s ; 所述后畸变消除级包括：NMOS管M1aL与NMOS管M1aR、栅极隔直电容及栅极偏置电阻，其中，所述NMOS管M1aL的源级连接到NMOS管ML2的源极、NMOS管M1aR的源级连接到NMOS管MR2的源极，所述NMOS管M1aL与M1aR的栅极分别通过栅极偏置电阻连接到偏置电压Vb，NMOS管M1aL与M1aR的漏极相连、且接到电源VDD，所述NMOS管M1aL的源级通过栅极隔直电容连接到M1aR的漏级、所述NMOS管M1aR的源级通过栅极隔直电容连接到M1aL的漏级。The post-distortion elimination stage includes: an NMOS transistor M 1aL and an NMOS transistor M 1aR , a gate blocking capacitor and a gate bias resistor, wherein the source stage of the NMOS transistor M 1aL is connected to the source of the NMOS transistor M L2 , The source stage of the NMOS transistor M1aR is connected to the source of the NMOS transistor MR2, the gates of the NMOS transistors M1aL and M1aR are respectively connected to the bias voltage Vb through the gate bias resistor, and the NMOS transistor M1aL and the The drain of M 1aR is connected to the power supply V DD , the source of the NMOS transistor M 1aL is connected to the drain of M 1aR through a gate blocking capacitor, and the source of the NMOS transistor M 1aR is isolated through the gate A direct capacitor is connected to the drain of M 1aL . 2.按权利要求1所述后畸变CMOS低噪声放大器，其特征在于，所述级联级还包括一个电感Ladd，，所述电感Ladd连接与NMOS管ML2的源极与NMOS管MR2的源极之间。2. The post-distortion CMOS low-noise amplifier according to claim 1, wherein the cascade stage further comprises an inductance L add , and the inductance L add is connected to the source of the NMOS transistor M L2 and the NMOS transistor M between the source of R2 . 3.按权利要求1所述后畸变CMOS低噪声放大器，其特征在于，所述谐振负载均由负载电感(LdL、LdR)、负载电容(CdL、CdR)及负载电阻(RdL、RdR)构成，其中，负载电感与负载电阻串联后、再与负载电容并联构成谐振负载。3. The post-distortion CMOS low-noise amplifier according to claim 1, wherein the resonant load is composed of load inductance (L dL , L dR ), load capacitance (C dL , C dR ) and load resistance (R dL ) , R dR ), wherein the load inductance and the load resistance are connected in series, and then connected in parallel with the load capacitance to form a resonant load.
CN201811268081.8A 2018-10-29 2018-10-29 Distort CMOS low-noise amplifier after one kind Pending CN109546969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811268081.8A CN109546969A (en) 2018-10-29 2018-10-29 Distort CMOS low-noise amplifier after one kind

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811268081.8A CN109546969A (en) 2018-10-29 2018-10-29 Distort CMOS low-noise amplifier after one kind

Publications (1)

Publication Number Publication Date
CN109546969A true CN109546969A (en) 2019-03-29

Family

ID=65845797

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811268081.8A Pending CN109546969A (en) 2018-10-29 2018-10-29 Distort CMOS low-noise amplifier after one kind

Country Status (1)

Country Link
CN (1) CN109546969A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112886932A (en) * 2021-01-22 2021-06-01 上海华虹宏力半导体制造有限公司 Power amplifier with linear design

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080036537A1 (en) * 2006-08-11 2008-02-14 Motorola, Inc. Wide-band low-noise cmos amplifier
CN103219951A (en) * 2013-03-22 2013-07-24 中国科学技术大学 Low-power consumption and low-noise amplifier adopting noise cancellation technology
CN103780207A (en) * 2012-10-22 2014-05-07 上海华虹宏力半导体制造有限公司 Cmos radio frequency power amplifier
US20140312973A1 (en) * 2013-04-19 2014-10-23 Industry-Academic Cooperation Foundation, Yonsei University Low noise amplifier
CN104124924A (en) * 2014-06-25 2014-10-29 中国电子科技集团公司第三十八研究所 Linearization common-gate CMOS low-noise amplifier circuit
CN104579184A (en) * 2015-02-11 2015-04-29 中国科学技术大学 High-linearity broadband barron low-noise amplifier
US20160072442A1 (en) * 2014-09-05 2016-03-10 Innophase Inc. System and Method for Inductor Isolation
US20170373647A1 (en) * 2015-02-19 2017-12-28 Northeastern University Linearity Enhancement Method For Low-Power Low-Noise Amplifiers Biased In The Subthreshold Region

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080036537A1 (en) * 2006-08-11 2008-02-14 Motorola, Inc. Wide-band low-noise cmos amplifier
CN103780207A (en) * 2012-10-22 2014-05-07 上海华虹宏力半导体制造有限公司 Cmos radio frequency power amplifier
CN103219951A (en) * 2013-03-22 2013-07-24 中国科学技术大学 Low-power consumption and low-noise amplifier adopting noise cancellation technology
US20140312973A1 (en) * 2013-04-19 2014-10-23 Industry-Academic Cooperation Foundation, Yonsei University Low noise amplifier
CN104124924A (en) * 2014-06-25 2014-10-29 中国电子科技集团公司第三十八研究所 Linearization common-gate CMOS low-noise amplifier circuit
US20160072442A1 (en) * 2014-09-05 2016-03-10 Innophase Inc. System and Method for Inductor Isolation
CN104579184A (en) * 2015-02-11 2015-04-29 中国科学技术大学 High-linearity broadband barron low-noise amplifier
US20170373647A1 (en) * 2015-02-19 2017-12-28 Northeastern University Linearity Enhancement Method For Low-Power Low-Noise Amplifiers Biased In The Subthreshold Region

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
(美）毕查德•拉扎维著；陈贵灿，程军，张瑞智等译: "《模拟CMOS集成电路设计 简编版》", 30 April 2013, 西安交通大学出版社 *
HABIB RASTEGAR: "A High linearity CMOS low noise amplifier for 3.66 GHz applications using current-reused topology", 《MICROELECTRONICS JOURNAL》 *
付华: "《数字电子技术基础》", 30 April 2002, 东北大学出版社 *
兰萍: "一种高线性度共栅CMOS混频器的分析与设计", 《西藏科技》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112886932A (en) * 2021-01-22 2021-06-01 上海华虹宏力半导体制造有限公司 Power amplifier with linear design
CN112886932B (en) * 2021-01-22 2024-04-12 上海华虹宏力半导体制造有限公司 Power amplifier with linearization design

Similar Documents

Publication Publication Date Title
CN102394571B (en) In-chip integrated low noise amplifier
CN103248324B (en) A kind of high linearity low noise amplifier
JP5175389B2 (en) Amplifier with improved linearization
CN104124924B (en) A kind of common grid CMOS amplifier circuit in low noise of linearisation
CN107070425B (en) Broadband low-power-consumption low-noise amplifier applied to wireless sensor network
JP5798635B2 (en) Current mirror and high compliance single stage amplifier
CN103219951B (en) A kind of low-power consumption low noise amplifier adopting noise cancellation technique
CN102651633B (en) Noise current feed-forward type noise cancellation circuit
CN103219952B (en) A kind of wideband low noise amplifier adopting noise cancellation technique
CN105305981B (en) One kind linearisation wideband low noise amplifier
CN104113293A (en) High-gain and low-noise differential trans-impedance amplifier
CN110729974A (en) Ultra-wideband high-gain low-noise amplifier
CN104579184B (en) A kind of high linearity broadband balun low-noise amplifier
Rafati et al. A 0.65 V, linearized cascade UWB LNA by application of modified derivative superposition technique in 130 nm CMOS technology
CN111478671B (en) A Novel Low Noise Amplifier Applied in Sub-GHz Frequency Band
CN206712752U (en) Broadband low-power consumption low-noise amplifier applied to wireless sensor network
CN109546969A (en) Distort CMOS low-noise amplifier after one kind
WO2021135435A1 (en) Radio-frequency signal processing circuit
CN112953419A (en) Nonlinear cancellation power amplifier based on cascode structure
Manjula et al. Design of low power 2.4 GHz CMOS cascode LNA with reduced noise figure for WSN applications
Guo et al. A differential CMOS common-gate LNA linearized by cross-coupled post distortion technique
KR101387975B1 (en) Low noise amplifier
CN116865690A (en) Ultra-wideband, low-power, compact low-noise amplifier based on asymmetric transformer
CN107104647B (en) Power amplifier based on neural network
CN107579715A (en) A Broadband Linearized CMOS Low Noise Amplifier Circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190329

RJ01 Rejection of invention patent application after publication