CN109509736A - Circuit board and chip packing-body - Google Patents
Circuit board and chip packing-body Download PDFInfo
- Publication number
- CN109509736A CN109509736A CN201710828809.7A CN201710828809A CN109509736A CN 109509736 A CN109509736 A CN 109509736A CN 201710828809 A CN201710828809 A CN 201710828809A CN 109509736 A CN109509736 A CN 109509736A
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- Prior art keywords
- ground connection
- circuit board
- conductive
- packing
- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15162—Top view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Geometry (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The present invention provides a kind of circuit board and chip packing-body.Chip packing-body of the invention includes circuit board, packing colloid, multiple conductive structures and electromagnetic interference protective layer.Circuit board includes multiple ground connection conductive pads, is set on its lower surface.Packing colloid is set on the upper surface of circuit board.Conductive structure is set in packing colloid, and is electrically connected ground connection conductive pad, wherein the endpoint of each conductive structure exposes from the side wall of packing colloid.Electromagnetic interference protective layer is set on packing colloid, and is electrically connected through the endpoint of conductive structure with ground connection conductive pad.
Description
Technical field
The present invention reveals about a kind of circuit board and chip packing-body, espespecially a kind of circuit board and chip packing-body, side
Earth lead out with electromagnetic interference protective layer to be electrically connected.
Background technique
Semiconductor packages (semiconductor package) is one kind to be integrated one or more die seals
Technology, to provide the protection of the certain impact of crystal grain or friction.With the evolution of science and technology, the size of chip is smaller and smaller,
In route it is more and more intensive, the electromagnetic interference problem of chip packing-body is also increasingly severe, therefore, can wrap in chip packing-body
It containing an electromagnetic interference protective layer, is electrically connected with earth lead, to provide electromagnetic interference shielding.However, chip packing-body is being surveyed
Disengaging test socket can be repeated when examination, caused between electromagnetic interference protective layer and earth lead due to the abrasion of electromagnetic interference protective layer
Open circuit is formed, electromagnetic interference protective layer is made to generate antenna effect.
Summary of the invention
One of the objects of the present invention is to provide a kind of chip packing-body and circuit boards, through in the side wall dew of packing colloid
Conductive structure out, or expose the endpoint of a plurality of earth lead in the side wall of circuit board, make electromagnetic interference protective layer and earth lead
Between be not easy because test generate open circuit.
One embodiment of the invention provides a kind of chip packing-body comprising a circuit board, a packing colloid, multiple conductions
Structure and an electromagnetic interference protective layer.Circuit board has upper surface and lower surface relative to each other, and wherein circuit board includes
Multiple ground connection conductive pads, are set on lower surface.Packing colloid is set on the upper surface of circuit board.Conductive structure is set to envelope
It fills in colloid, conductive structure is electrically connected ground connection conductive pad, wherein the endpoint of each conductive structure reveals from the side wall of packing colloid
Out.Electromagnetic interference protective layer is set on packing colloid, and is electrically connected through the endpoint of conductive structure with ground connection conductive pad.
Another embodiment of the present invention provides a kind of circuit board comprising an insulating layer and a plurality of ground connection cabling.Ground connection
Cabling is set in insulating layer, and each ground connection cabling includes a plurality of earth lead, wherein the endpoint of each earth lead is from circuit board
Side wall expose, and earth lead expose endpoint overlap in the overlook direction of circuit board.
Detailed description of the invention
Fig. 1 depicts the side view of the chip packing-body of first embodiment of the invention.
Fig. 2 depicts the chip packing-body of first embodiment of the invention along the cross-sectional view of the hatching line A-A' of Fig. 1.
Fig. 3 depicts the side view of the chip packing-body of second embodiment of the invention.
Fig. 4 depicts the chip packing-body of second embodiment of the invention along the cross-sectional view of the hatching line A-A' of Fig. 3.
Fig. 5 depicts the cross-sectional view of the chip packing-body of third embodiment of the invention.
Fig. 6 depicts the side view that the circuit board of third embodiment of the invention is watched from the arrow C of Fig. 5.
Fig. 7 depicts the cross-sectional view of the chip packing-body of fourth embodiment of the invention.
Fig. 8 depicts the cross-sectional view of the chip packing-body of fifth embodiment of the invention.
Symbol description
10,100,200,300,400 chip packing-body
CB, CB', CB ", the upper surface CB " ' circuit board CBa
The lower surface CBb IN insulating layer
BP connection pad CP conductive pad
GBP is grounded connection pad CBP1, CBP2 chip connecting pad
GCP is grounded the ungrounded conductive pad of conductive pad NGCP
GTR is grounded cabling CTR chip cabling
V overlook direction CL conductor wire
WL conductor layer GW, GW' earth lead
The GV earth-continuity hole bonding pad CR
The interval H horizontal direction NP
DR element region GS, GS' conductive structure
CH electronic component SB tin ball
EN packing colloid ELP interconnecting piece
EL electromagnetic interference protective layer
Specific embodiment
It is hereafter special to arrange to enable the those skilled in the art for being familiar with the technical field of the invention to be further understood that the present invention
Lift presently preferred embodiments of the present invention, and cooperate attached drawing, the constitution content that the present invention will be described in detail and it is to be reached the effect of.In order to
Facilitate expression and can will readily appreciate that, attached drawing not with the actual size of finished product or scale, therefore in attached drawing element ruler
Very little or ratio is only not intended to illustrate to limit the scope of the invention.
Fig. 1 depicts the side view of the chip packing-body of first embodiment of the invention, and Fig. 2, which depicts the present invention first, to be implemented
Example chip packing-body along Fig. 1 hatching line A-A' cross-sectional view.As shown in Figures 1 and 2, chip packing-body 10 includes a circuit
Plate CB, an electronic component CH, a packing colloid EN and an electromagnetic interference protective layer EL.Circuit board CB has opposite to each other upper
Surface C Ba and lower surface CBb, circuit board CB include an insulating layer IN, multiple connection pad BP, multiple conductive pad CP and a plurality of core
Piece cabling CTR, insulating layer IN are set between upper surface CBa and lower surface CBb, and connection pad BP is set on the CBa of upper surface, conductive
Pad CP is set on the CBb of lower surface, and chip cabling CTR is set in insulating layer IN.Electronic component CH (such as chip) setting
In on the upper surface CBa of circuit board CB, and it for example can be electrically connected to connection pad BP through conductor wire CL, to penetrate connection pad BP and chip
Cabling CTR is connected to corresponding conductive pad CP.Connection pad BP may include chip connecting pad CBP1, CBP2, and wherein chip connecting pad CBP1 is used
To be electrically connected to the ground terminal of electronic component CH, ungrounded signal of the chip connecting pad CBP2 to be electrically connected to electronic component CH
End.Conductive pad CP may include ground connection conductive pad GCP and ungrounded conductive pad NGCP, wherein ground connection conductive pad GCP is to be electrically connected
It is connected to external ground terminal, ungrounded conductive pad NGCP is to be electrically connected to external ungrounded end.It is familiar with the technology in this field
Personnel's Ying Zhi chip cabling CTR can have different structures according to design requirement.For example, chip cabling CTR can be by multilayer
Conductor layer WL and multiple via holes are formed, and insulating layer IN may include multilayer dielectric layer, wherein each conductor layer WL is set to
Between wantonly two adjacent insulating layers, so that adjacent wire layers WL can pass through therebetween insulating layer and separate, and each via hole
One or more layers corresponding insulating layer can be run through.Therefore, in same chip cabling CTR, conducting wire can be used to reach horizontal direction H
Electrical connection, and via hole can be used to reach the electrical connection of vertical direction V.
Packing colloid EN is set on the upper surface CBa of circuit board CB, to seal electronic element CH.Electromagnetic interference shielding
Layer EL is arranged and is covered on packing colloid EN, and electromagnetic interference protective layer EL may include at least two interconnecting pieces separated from one another
ELP, from the side wall that the upper surface of packing colloid EN extends to circuit board CB.It is worth noting that one of chip cabling CTR
Person can be for the ground connection cabling that chip connecting pad CBP1 is electrically connected to ground connection conductive pad GCP comprising a plurality of respectively by difference
Conductive layer WL is formed by earth lead GW, and the endpoint of at least the two can be respectively from circuit board CB difference portion in earth lead GW
Side wall is divided to expose, to be in contact respectively from different interconnecting piece ELP.Whereby, each interconnecting piece ELP of circuit board CB side wall is extended to
It can be electrically connected with the endpoint of corresponding earth lead GW, to be further electrically coupled to ground connection conductive pad GCP, therefore electromagnetic interference
Protective layer EL can have the function of electromagnetic interference shielding.
However, since chip packing-body 10 can repeat disengaging test socket in test, and circuit board CB side wall is being tested
When can completely attach to test socket, therefore electromagnetic interference protective layer EL be located at the interconnecting piece ELP on circuit board CB side wall be easy by
To test socket friction and fall off, cause to form open circuit between electromagnetic interference protective layer EL and earth lead GW, so that electromagnetism is dry
It disturbs protective layer EL and generates antenna effect.
Fig. 3 is painted the side view of the chip packing-body of second embodiment of the invention, and Fig. 4 is painted second embodiment of the invention
Chip packing-body along the hatching line A-A' of Fig. 3 cross-sectional view.Fig. 3, chip packing-body 100 and Fig. 1 shown in 4, chip shown in 2
The difference of packaging body 10 is that chip packing-body 100 further includes multiple conductive structure GS, is set in packing colloid EN, and lead
Electric structure GS electrical connection ground connection conductive pad GCP.Conductive structure GS may be, for example, metal wire, but not limited to this.In embodiment, electric
The connection pad BP of road plate CB' can include separately multiple ground connection connection pad GBP, and the side wall of proximate circuitry plate CB', which is arranged and is electrically connected ground connection, leads
Electrical pad GCP.Also, each conductive structure GS can connect ground connection connection pad GBP, and extend to packaging plastic from circuit board CB' upper surface CBa
The side wall of body EN, so that the end point of each conductive structure GS can expose from the side wall of packing colloid EN.Due to electromagnetic interference shielding
The interconnecting piece ELP of layer EL can be extended on the side wall of packing colloid EN, therefore electromagnetic interference protective layer EL can pass through and tie with conductive
The contact of structure GS is electrically connected to ground connection connection pad GBP, and to be further electrically connected to ground connection conductive pad GCP, and it is dry to can reach electromagnetism
Disturb the function of protection.To avoid extending to the conductive structure GS and ground connection connection pad GBP of packing colloid EN side wall from influencing electronic component
The configuration of CH and conductor wire CL, conductive structure GS and ground connection connection pad GBP can for example be located at chip connecting pad CBP1, CBP2 and circuit board
Between the side wall of CB'.
In an embodiment, cabling of the circuit board CB' of chip packing-body 100 in insulating layer IN can be similar to Figure 2
Chip packing-body 10 cabling of the circuit board CB' in insulating layer IN, and the ground connection connection pad GBP of circuit board CB' can pass through and lead
Through-hole is electrically connected to earth lead GW as shown in Figure 2.
In this way, the endpoint due to each conductive structure GS can expose from the side wall of packing colloid EN, electromagnetic interference
The electrically connecting position of protective layer EL and conductive structure GS can keep whereby electromagnetic interference protective layer EL and ground connection far from test socket
The electrical connection of conductive pad GCP, to avoid antenna effect is generated.
Circuit board of the invention is not limited to the design of above-described embodiment.Fig. 5 depicts the core of third embodiment of the invention
The cross-sectional view of piece packaging body 200, Fig. 6 are painted the circuit board of chip packing-body 200 of the present invention from the side that the arrow C of Fig. 5 is watched
Figure.Chip packing-body 200 and Fig. 3, chip packing-body 100 shown in 4 difference be, the circuit board CB " of chip packing-body 200
It can include separately a plurality of ground connection cabling GTR, be set in insulating layer IN, and be grounded connection pad GBP and can pass through ground connection cabling GTR electrical connection
It is grounded conductive pad GCP.Specifically, respectively ground connection cabling GTR may include a plurality of earth lead GW, respectively by different conductive layer WL
It is formed, and can pass through earth-continuity hole GV and be electrically connected to each other, and then the ground connection connection pad of circuit board CB " upper surface CBa will be located at
GBP is electrically connected to the ground connection conductive pad GCP positioned at circuit board CB " lower surface CBb.The present embodiment difference ground connection cabling GTR's connects
Ground wire GW can be connected to each other, so that ground connection cabling GTR is electrically connected to each other, but not limited to this.In another embodiment, difference is connect
The earth lead GW of ground cabling GTR also can be separated from one another, is electrically insulated from different ground connection cabling GTR.
In this present embodiment, at least the two respectively in the earth lead GW of ground connection cabling GTR may extend to circuit board CB "
Side wall makes each ground connection cabling GTR have the endpoint of at least two earth lead GW that can expose from the side wall of circuit board CB ", to help with
The interconnecting piece ELP of electromagnetic interference protective layer EL is electrically connected, that is to say, that circuit board CB " can for plating line (plating line,
PL) type circuit plate.For example, the side wall of circuit board CB " can have multiple bonding pad CR, extend respectively from upper surface CBa
To lower surface CBb, the interconnecting piece ELP of electromagnetic interference protective layer EL is arranged, and the ground connection of corresponding same ground connection cabling GTR is led
The endpoint of line GW can expose from the side wall of same bonding pad CR, to connect with same interconnecting piece ELP.Therefore, the number of interconnecting piece ELP
Amount can be identical as the ground connection quantity of cabling GTR.For example, the quantity of interconnecting piece ELP can be even number, such as two, four or
More than.
It is worth noting that since each ground connection cabling GTR has the endpoint of at least two earth lead GW can be from circuit board CB "
Side wall exposes, and to increase the quantity of each interconnecting piece ELP with the tie point of corresponding ground connection cabling GTR, therefore can reduce each interconnecting piece
ELP is worn with the electrical connection of corresponding ground connection cabling GTR and the probability that breaks, to avoid the generation antenna of chip packing-body 200
Effect.To make the earth lead GW of same ground connection cabling GTR conveniently extend to the side wall of circuit board CB ", corresponding ground connection connection pad GBP
Ground connection cabling GTR be preferably located between the side wall of chip cabling CTR and circuit board CB ".
It is worth noting that the 2 abutting end points that the earth lead GW of corresponding same ground connection cabling GTR is exposed are in circuit
It overlaps each other on the overlook direction V of plate CB ", and this feature violates the design principle at legacy endpoint interval, also that is, earth lead GW
The 2 abutting end points exposed in the horizontal direction interval (pitch) NP on H less than 80 microns.Specifically, due to containing electricity
The chip packing-body 200 of road plate CB " when testing, can repeat disengaging test socket, and the endpoint of circuit board CB " is easy because of quilt
Test socket squeezes, and wire is caused to extend towards upper surface CBa.In traditional circuit-board, neighbouring conductive layer WL is in water
E.g., about 50 microns of processing procedure bit errors square on H, the width of conducting wire endpoint is, for example, about 20 microns, and from circuit
Plate side wall exposes endpoint and is not electrically connected to same chip cabling, therefore short to avoid causing because of the metal extension of endpoint
Road, when the configuration relation of endpoint is exposed in design, design principle, which can be set in, to be located in upper and lower two adjacent conductive layers WL
Interval of the 2 abutting end points in the horizontal direction on H need to be greater than or equal to about 80 microns.However, the same ground connection cabling of the present embodiment
The earth lead GW of GTR is electrical connection, therefore will not be led to the problem of forming short circuit between the two.
Referring to FIG. 7, the cross-sectional view of its chip packing-body 300 for being painted fourth embodiment of the invention.Compared to shown in Fig. 5
Chip packing-body 200, the conductive structure GS' of chip packing-body 300 can be sheet metal.
Referring to FIG. 8, the cross-sectional view of its chip packing-body 400 for being painted fifth embodiment of the invention.Compared to shown in Fig. 5
Chip packing-body 200, the earth lead GW' of the circuit board CB " ' of chip packing-body 400 can be not extend to circuit board CB's " '
Side wall, so that the side wall of circuit board CB " ' and being not exposed from the endpoint of earth lead GW'.That is, circuit board CB " ' can also
For non-electrical plate wire (non-plating line, NPL) type circuit plate.In this present embodiment, electromagnetic interference protective layer EL still may be used
Ground connection conductive pad GCP is electrically connected to through conductive structure GS.
The above description is only an embodiment of the present invention, all equivalent changes done according to scope of the present invention patent with repair
Decorations, are all covered by the present invention.
Claims (10)
1. a kind of chip packing-body, comprising:
One circuit board has a upper surface and a lower surface relative to each other, and wherein the circuit board includes that multiple ground connection are conductive
Pad, is set on the lower surface；
One packing colloid is set on the upper surface of the circuit board；
Multiple conductive structures are set in the packing colloid, these conductive structures are electrically connected these ground connection conductive pads, wherein
Respectively the end point of the conductive structure exposes from the side wall of the packing colloid；And
One electromagnetic interference protective layer is set on the packing colloid, and is connect through these endpoints of these conductive structures with these
The electrical connection of ground conductive pad.
2. chip packing-body as described in claim 1, which is characterized in that the circuit board separately includes multiple ground connection connection pads, setting
In on the upper surface, and these conductive structures are electrically connected these ground connection conductive pads through these ground connection connection pads.
3. chip packing-body as claimed in claim 2, which is characterized in that the circuit board separately includes an insulating layer and a plurality of sets
The ground connection cabling being placed in the insulating layer, and these ground connection connection pads are electrically connected these ground connection conductive pads through these ground connection cablings.
4. chip packing-body as claimed in claim 3, which is characterized in that respectively the ground connection cabling includes a plurality of is electrically connected to each other
Earth lead, the endpoint both at least in these earth leads exposes from the side wall of the circuit board, and the electromagnetic interference shielding
Layer is in contact with the endpoint that at least the two is exposed in these earth leads.
5. chip packing-body as claimed in claim 4, which is characterized in that this in these earth leads both at least exposed
Endpoint overlaps in the overlook direction of the circuit board.
6. chip packing-body as claimed in claim 4, which is characterized in that this in these earth leads both at least exposed
The interval of endpoint in the horizontal direction is less than 80 microns.
7. chip packing-body as described in claim 1, which is characterized in that respectively the conductive structure includes metal wire or sheet metal.
8. a kind of circuit board, comprising:
One insulating layer；And
A plurality of ground connection cabling, is set in the insulating layer, and respectively the ground connection cabling includes a plurality of earth lead, wherein the respectively ground connection
The end point of conducting wire exposes from the side wall of the circuit board, and these endpoints of these earth leads exposing are in the vertical view of the circuit board
It overlaps on direction.
9. circuit board as claimed in claim 8, which is characterized in that further include multiple ground connection connection pads being set on the upper surface
And multiple ground connection conductive pads being set on the lower surface, and these ground connection connection pads are electrically connected these through these ground connection cablings
It is grounded conductive pad.
10. circuit board as claimed in claim 8, which is characterized in that the interval of two these adjacent endpoints in the horizontal direction
Less than 80 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710828809.7A CN109509736A (en) | 2017-09-14 | 2017-09-14 | Circuit board and chip packing-body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710828809.7A CN109509736A (en) | 2017-09-14 | 2017-09-14 | Circuit board and chip packing-body |
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| Publication Number | Publication Date |
|---|---|
| CN109509736A true CN109509736A (en) | 2019-03-22 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710828809.7A Pending CN109509736A (en) | 2017-09-14 | 2017-09-14 | Circuit board and chip packing-body |
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| CN (1) | CN109509736A (en) |
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