CN109411441A - Chip after circuit board and encapsulation - Google Patents
Chip after circuit board and encapsulation Download PDFInfo
- Publication number
- CN109411441A CN109411441A CN201710701201.8A CN201710701201A CN109411441A CN 109411441 A CN109411441 A CN 109411441A CN 201710701201 A CN201710701201 A CN 201710701201A CN 109411441 A CN109411441 A CN 109411441A
- Authority
- CN
- China
- Prior art keywords
- chip
- heat dissipation
- pad
- circuit board
- cabling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
The present invention provides a kind of circuit board comprising a upper surface and a lower surface, multiple heat dissipation connection pads and multiple radiation conductive pads relative to each other.Connection pad setting radiate on an upper, to be electrically connected heat dissipation element, wherein heat dissipation connection pad is electrically insulated from.Radiation conductive pad is arranged on the lower surface, and radiation conductive pad is electrically insulated from, and radiation conductive pad is electrically connected heat dissipation connection pad.
Description
Technical field
The present disclosure generally relates to chip after a kind of circuit board and encapsulation, espespecially a kind of permeable electric signal tests heat dissipation element
Chip after the circuit board being electrically connected and encapsulation between circuit board.
Background technique
With the evolution and development of electronic product, electronic product has become indispensable article in society now,
Middle chip is even more to be widely used in electronic product.In the operation of chip, inevitably generates high fever and cause
Chip temperature rises, therefore in order to avoid chip is influenced its running by high temperature, would generally be arranged for example in chip after encapsulation
Cooling fin.However, may result in so-called antenna effect if sticking together for heat dissipation element is in poor shape, that is to say, that heat dissipation member
Part sticks together in poor shape one end, can receive extraneous electromagnetic signal and chip is interfered to operate, or thus end issues electromagnetism letter
Number and influence other elements.
Summary of the invention
One of the objects of the present invention is to provide chips after a kind of circuit board and encapsulation, through insulated from each other in circuit board
Heat dissipation cabling is separately connected multiple heat dissipation connection pads and multiple radiation conductive pads, makes with the envelope for sticking together in poor shape heat dissipation element
Chip can be found after dress.
One embodiment of the invention provides a kind of circuit board comprising a relative to each other upper surface and a lower surface,
Multiple heat dissipation connection pads and multiple radiation conductive pads.Connection pad setting radiate on an upper, heat dissipation connection pad is to be electrically connected heat dissipation
Element, wherein heat dissipation connection pad is electrically insulated from.Radiation conductive pad is arranged on the lower surface, and radiation conductive pad is electrically exhausted each other
Edge, and radiation conductive pad is respectively electrically connected to heat dissipation connection pad.
Another embodiment of the present invention provides chip after a kind of encapsulation comprising circuit board and heat dissipation element.Heat dissipation member
Part sticks together on the heat dissipation connection pad of circuit board, heat dissipation element with heat dissipation connection pad be electrically connected, and radiate connection pad penetrate heat dissipation element that
This electrical connection.
Detailed description of the invention
Fig. 1 is painted the diagrammatic cross-section of the circuit board of one embodiment of the invention.
Fig. 2 is painted the top view of chip after the encapsulation of one embodiment of the invention.
Fig. 3 be painted encapsulation after chip along Fig. 2 hatching line A-A ' diagrammatic cross-section.
Fig. 4 be painted encapsulation after chip along Fig. 2 hatching line B-B ' diagrammatic cross-section.
Fig. 5 is painted the schematic top plan view of the cooling fin of one embodiment of the invention.
Symbol description
100 circuit boards
The upper surface 100a
The lower surface 100b
110 circuit layers
112 insulating layers
Chip after 200 encapsulation
210 cooling fins
210a covers main body
210b pin
212 openings
220 chips
230 metal wires
240 packing colloids
250 tin balls
CBP1, CBP2 chip connecting pad
HP radiation conductive pad
CP1, CP2 chip conductive pad
HBP heat dissipation connection pad
TRH heat dissipation cabling
TRC1, TRC2 chip cabling
Z overlook direction
Specific embodiment
The present invention is further understood that enable to be familiar with general technical staff of the technical field of the invention, hereafter special column
Lift the embodiment of the present invention, and cooperate institute's accompanying drawings, the constitution content that the present invention will be described in detail and it is to be reached the effect of, this theory
Every details in bright book also can be carried out without departing from the spirit of the present invention various modifications and be become based on different viewpoints and application
More.Separately it is noted that following figures is simplified signal schema, and the basic structure that only the invention is illustrated in a schematic way
Think, only shows element related to the present invention in schema then rather than component number, shape and size when according to actual implementation are drawn
System, when actual implementation kenel, quantity and the ratio of each element can be changed with demand, and component placement kenel can be answered more
It is miscellaneous.
Fig. 1 is painted the diagrammatic cross-section of the circuit board of one embodiment of the invention.As shown in Figure 1, the circuit board of the present embodiment
100 include upper surface 100a and lower surface 100b relative to each other, a circuit layer 110, the upper surface for being set to circuit board 100
Multiple heat dissipation connection pad HBP on 100a and multiple chip connecting pads CBP1, CBP2 and the lower surface for being set to circuit board 100
Multiple radiation conductives pad HP and multiple chip conductives on 100b pad CP1, CP2.
Circuit layer 110 may include an insulating layer 112, a plurality of heat dissipation cabling TRH and a plurality of chip cabling TRC1, TRC2.
The cabling TRH that radiates is arranged in insulating layer 112 with chip cabling TRC1, TRC2, so that respectively heat dissipation cabling TRH and chip cabling
TRC1, TRC2 can pass through insulating layer 112 and separate and make to be electrically insulated from.Due to it is well known that this those skilled in the art should know heat dissipation
Cabling TRH can pass through multilayer dielectric layer with chip cabling TRC1, TRC2 and multi-layer conductor leads layer is formed, and can pass through insulating layer
The conducting wire of different conductive layers is carried out the electrical connection of vertical direction by opening, therefore not described here any more.
To be electrically connected heat dissipation element (such as cooling fin), heat dissipation connection pad HBP is electrically insulated from heat dissipation connection pad HBP, and
Each heat dissipation connection pad HBP is electrically insulated with chip connecting pad CBP1, CBP2, that is, electronics member is not yet provided on circuit board 100
In the case where part or heat dissipation element, it is each radiate connection pad HBP not with other heat dissipation connection pad HBP or any chip connecting pad CBP1, CBP2
Electrical connection.Heat dissipation connection pad HBP can be electrically connected to radiation conductive pad HP through the heat dissipation cabling TRH in circuit layer 110 respectively, that is,
In the case where being not provided with electronic component or heat dissipation element on circuit board 100, a heat dissipation connection pad HBP only transmits a heat dissipation
Cabling TRH is electrically connected with a radiation conductive pad HP, without being electrically connected with chip conductive pad CP1, CP2.Radiation conductive pad HP that
This is electrically insulated, and each radiation conductive pad HP is electrically insulated with chip conductive pad CP1, CP2, that is, on circuit board 100 still
In the case where being not provided with electronic component or heat dissipation element, each radiation conductive pad HP is not led with other conductive pads HP or any chip
The electrical connection of electrical pad CP1, CP2.Radiation conductive pads HP to be electrically connected to external ground terminal.
Chip connecting pad CBP1, CBP2 is to be electrically connected electronic component (such as chip).Chip connecting pad CBP1 can be used to be electrically connected
It is connected to the ground terminal of electronic component, and the chip cabling TRC1 that can pass through in circuit layer 110 is electrically connected to an at least chip conductive
CP1 is padded, and is not electrically connected with radiation conductive pad HP.For example, chip connecting pad CBP1 may be electrically connected to two chip conductive pads
CP1.Chip conductive pads CP1 to be electrically connected to external ground terminal.Chip connecting pad CBP2 can be used to be electrically connected to electronic component
Ungrounded end (such as: other voltage signal ends), and the chip cabling TRC2 that can pass through in circuit layer 110 is electrically connected to a core
Piece conductive pad CP2.Chip conductive pads CP2 to be electrically connected to external ungrounded end (such as: voltage signal).It note that core
Electric connection mode between piece connection pad CBP1, CBP2 and chip conductive pad CP1, CP2 is not limited to this.In other embodiments,
Electric connection mode between chip connecting pad CBP1, CBP2 and chip conductive pad CP1, CP2 can be designed according to demand.
Fig. 2 is painted the top view of chip 200 after the encapsulation of one embodiment of the invention, Fig. 3 be painted after encapsulation chip 200 along
The diagrammatic cross-section of Fig. 2 hatching line A-A ', Fig. 4 be painted encapsulation after chip 200 along Fig. 2 hatching line B-B ' diagrammatic cross-section.Such as Fig. 2
With shown in Fig. 3, chip 200 includes circuit board 100, cooling fin 210, chip 220, metal wire 230, envelope after the encapsulation of the present embodiment
Colloid 240 and tin ball (solderball) 250 are filled, wherein the structure of circuit board 100 can consider explanation above in light of actual conditions, be not repeated
It repeats.
Cooling fin 210 is electrically connected through adhesive agent (such as conducting resinl) with the heat dissipation connection pad HBP of circuit board 100.Cooling fin
210 cover chip 220 on the overlook direction Z of circuit board 100, and the upper surface of cooling fin 210 exposes outside packing colloid 240,
It whereby can in running, generated heat sheds by chip 220.Since cooling fin 210 includes the good conductive material of thermal conductivity
(such as metal), therefore cooling fin 210 also has electromagnetic interference (electromagnetic interference, EMI) protection
Effect, interference of the maskable chip 220 by outer signals.
Fig. 5 is painted the top view of the cooling fin 210 of one embodiment of the invention, and cooling fin 210 includes 4 pin 210b.It dissipates
4 pin 210b of backing 210 are attached to respectively on 4 heat dissipation connection pad HBP on circuit board 100, as shown in Figure 2 and Figure 3, with
Cooling fin 210 is set to be electrically connected to ground terminal through 4 radiation conductive pad HP.In addition, each pin 210b can have an opening 212,
A possibility that pin 210b is produced fracture after by multiple dilation can be reduced whereby.It note that in the present invention and drawing
The quantity of foot 210b is not limited to 4, and in another embodiment, the quantity of pin 210b is 8, and in the case, circuit board 100 is also right
Should have 8 heat dissipation connection pad HBP and 8 radiation conductive pad HP.It note that in the present invention and be also not limited in the quantity of pin 210b
Even number.
Chip 220 can pass through metal wire 230 and be electrically connected with the chip connecting pad CBP on circuit board 100.In the present embodiment,
The weld pad system of chip 220 is electrically connected to chip connecting pad CBP1, CBP2 by the mode of routing engagement (wire bonding), but not
As limit.In alternate embodiment, weld pad also by Flip Chip (flip-chip) or can be otherwise electrically connected to chip
Connection pad CBP1, CBP2.
Packing colloid 240 is provided with inside and outside cooling fin 210, and packing colloid 240 covers chip 220.In another implementation
In example, packing colloid can be only set in cooling fin.In another embodiment, chip can also not have packing colloid after encapsulation.
Tin ball 250 is engaged with radiation conductive pad HP with chip conductive pad CP1, CP2 respectively, to improve chip 200 after encapsulation
The success rate engaged with other circuit boards.In another embodiment, chip can also not have tin ball after encapsulation.
It is worth noting that after traditional encapsulation in chip, being connected to the ground connection of radiation conductive pad, to walk linear system electric mutually
Connection.In the case, bad situation is binded even if having between the pin of cooling fin and heat dissipation connection pad, radiation conductive pad also can be saturating
It crosses ground connection cabling to be electrically connected with other radiation conductive pads, therefore can not be by the resistance value measured between two radiation conductive pads, to sentence
Whether have between the pin and heat dissipation connection pad of disconnected cooling fin and bind bad situation, to find out core after the encapsulation with antenna effect
Piece.
However, in the case that cooling fin 210 is not yet adhered to circuit board 100, radiation conductive pads HP each other in the present invention
It is electrically insulated.After cooling fin 210 is adhered to circuit board 100, radiation conductive pad insulated from each other in circuit board 100 originally
HP can be electrically connected to cooling fin 210 via respective heat dissipation cabling TRH, and then be electrically connected to each other through cooling fin 210.Therefore,
When have between the pin 210b of cooling fin 210 and heat dissipation connection pad HBP bind bad situation when, corresponding radiation conductive pad HP with
Resistance value between other radiation conductives pad HP will increase dramatically, in this way, can be by between measurement two radiation conductives pad HP
Resistance value have to judge whether to have between the pin 210b of cooling fin and heat dissipation connection pad HBP to bind bad situation to find out
Chip after the encapsulation of antenna effect.For example, the resistance value between having wantonly two radiation conductives pad is not fallen in a preset range
When, just represent to have between the pin of cooling fin and heat dissipation connection pad and bind bad situation, after the encapsulation chip have an antenna effect and
Defective products should be determined into.
The above description is only an embodiment of the present invention, all equivalent changes done according to the present patent application claim with repair
Decorations, are all covered by the present invention.
Claims (12)
1. a kind of circuit board, comprising:
A upper surface relative to each other and a lower surface；
Multiple heat dissipation connection pads, on this upper surface, to be electrically connected a heat dissipation element, wherein this waits heat dissipation connection pad electric each other for setting
Property insulation；And
Multiple radiation conductive pads, be arranged on the lower surface, wherein the grade radiation conductives pad is electrically insulated from, and this etc. radiate
Conductive pad is respectively electrically connected to grade heat dissipation connection pad.
2. circuit board as described in claim 1, which is characterized in that separately include:
One circuit layer, including a plurality of heat dissipation cabling, wherein the grade radiation conductives pad penetrates grade heat dissipation cabling respectively and is electrically connected to
The equal heat dissipation connection pad, and grade heat dissipation cabling is electrically insulated from.
3. circuit board as claimed in claim 2, which is characterized in that separately include:
Multiple chip connecting pads, setting on this upper surface, to be electrically connected an electronic component, wherein respectively the heat dissipation connection pad with this
Etc. chip connecting pads be electrically insulated.
4. circuit board as claimed in claim 3, which is characterized in that separately include:
Multiple chip conductive pads are arranged on the lower surface, wherein respectively the radiation conductive pad waits chip conductives pad electrical with this
Insulation.
5. circuit board as claimed in claim 4, which is characterized in that the circuit layer separately includes:
A plurality of chip cabling, wherein at least one of the equal chip conductives pad waits at least one of chips cabling person's electricity through this
At least one of chip connecting pads such as this are connected to, and grade heat dissipation cabling is electrically insulated from the grade chips cabling.
6. chip after a kind of encapsulation, comprising:
The circuit board as described in claim 1；And
One heat dissipation element sticks together on the grade heat dissipation connection pad of the circuit board, which is electrically connected with grade heat dissipation connection pad,
And grade heat dissipation connection pad is electrically connected to each other through the heat dissipation element.
7. chip after encapsulation as claimed in claim 6, which is characterized in that the circuit layer separately includes:
A plurality of heat dissipation cabling, wherein the grade radiation conductives pad penetrates grade heat dissipation cabling respectively and is electrically connected to grade heat dissipation connection pad.
8. chip after encapsulation as claimed in claim 7, which is characterized in that separately include:
One electronic component is arranged between the circuit board and the heat dissipation element；
Wherein the circuit board separately includes multiple chip connecting pads, and setting on this upper surface, is electrically connected the electronic component, and respectively this is dissipated
Hot connection pad with this etc. chip connecting pads be electrically insulated.
9. chip after encapsulation as claimed in claim 8, which is characterized in that the circuit board separately includes:
Multiple chip conductive pads, are arranged on the lower surface of the circuit board, and respectively the radiation conductive pad is led with the grade chips
Electrical pad is electrically insulated.
10. chip after encapsulation as claimed in claim 9, which is characterized in that the circuit layer separately includes:
A plurality of chip cabling, wherein at least one of the equal chip conductives pad waits at least one of chips cabling person's electricity through this
At least one of chip connecting pads such as this are connected to, and grade heat dissipation cabling is electrically insulated from the grade chips cabling.
11. chip after encapsulation as claimed in claim 6, which is characterized in that further include a packing colloid, be set to the circuit board
On.
12. chip after encapsulation as claimed in claim 6, which is characterized in that further include multiple tin balls, led respectively with the grade heat dissipations
Electrical pad engagement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710701201.8A CN109411441A (en) | 2017-08-16 | 2017-08-16 | Chip after circuit board and encapsulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710701201.8A CN109411441A (en) | 2017-08-16 | 2017-08-16 | Chip after circuit board and encapsulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109411441A true CN109411441A (en) | 2019-03-01 |
Family
ID=65454370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710701201.8A Pending CN109411441A (en) | 2017-08-16 | 2017-08-16 | Chip after circuit board and encapsulation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109411441A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011187497A (en) * | 2010-03-04 | 2011-09-22 | Casio Computer Co Ltd | Structure and method of mounting semiconductor device |
| CN103400825A (en) * | 2013-07-31 | 2013-11-20 | 日月光半导体制造股份有限公司 | Semiconductor wrapper and manufacturing method thereof |
| US8946886B1 (en) * | 2010-05-13 | 2015-02-03 | Amkor Technology, Inc. | Shielded electronic component package and method |
| CN104637924A (en) * | 2013-11-14 | 2015-05-20 | 爱思开海力士有限公司 | Emi shielding in semiconductor packages |
-
2017
- 2017-08-16 CN CN201710701201.8A patent/CN109411441A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011187497A (en) * | 2010-03-04 | 2011-09-22 | Casio Computer Co Ltd | Structure and method of mounting semiconductor device |
| US8946886B1 (en) * | 2010-05-13 | 2015-02-03 | Amkor Technology, Inc. | Shielded electronic component package and method |
| CN103400825A (en) * | 2013-07-31 | 2013-11-20 | 日月光半导体制造股份有限公司 | Semiconductor wrapper and manufacturing method thereof |
| CN104637924A (en) * | 2013-11-14 | 2015-05-20 | 爱思开海力士有限公司 | Emi shielding in semiconductor packages |
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| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20191227 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Applicant after: MediaTek.Inc Address before: 1/2, 4th floor, 26 Taiyuan Street, Zhubei City, Hsinchu County, Taiwan, China Applicant before: MStar Semiconductor Co., Ltd. |
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| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190301 |