JP4452627B2 - Integrated circuit assembly - Google Patents

Integrated circuit assembly Download PDF

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Publication number
JP4452627B2
JP4452627B2 JP2004560802A JP2004560802A JP4452627B2 JP 4452627 B2 JP4452627 B2 JP 4452627B2 JP 2004560802 A JP2004560802 A JP 2004560802A JP 2004560802 A JP2004560802 A JP 2004560802A JP 4452627 B2 JP4452627 B2 JP 4452627B2
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Japan
Prior art keywords
trace
integrated circuit
substrate
circuit assembly
die
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Expired - Fee Related
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JP2004560802A
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Japanese (ja)
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JP2006510224A (en
JP2006510224A5 (en
Inventor
カンドロス，イゴー，ケイ
エルドリッジ，ベンジャミン，エヌ
ミラー，チャールズ，エイ
スポーク，エイ，ニコラス
グルーブ，ゲーリー，ダブリュー
マシュー，ゲータン，エル
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フォームファクター， インコーポレイテッド
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Publication of JP2006510224A publication Critical patent/JP2006510224A/en
Publication of JP2006510224A5 publication Critical patent/JP2006510224A5/ja
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Description

本発明は集積回路に関し、詳しくは基板上にＫｎｏｗ−Ｇｏｏｄ−Ｄｉｅを使用した集積回路アセンブリに関する。   The present invention relates to an integrated circuit, and more particularly to an integrated circuit assembly using Know-Good-Die on a substrate.

集積回路は、ＬＯＣ（Lead-Over-Chip)リードフレームに機械的に取り付けられ、且つＬＯＣリードフレームに電気的に接続された半導体ダイを有する場合がある。半導体ダイとリードフレームは通常、プラスチックパッケージ、セラミックパッケージ、または金属パッケージの中にトランスファー封入成形される。パッケージ化されたダイの代わりにＫｎｏｗ−Ｇｏｏｄ−Ｄｉｅ（ＫＧＤ）を使用することにより、製造効率を向上させコストを低減できることがある。ＫＧＤとは、検査および／または稼動試験により、他の同等のパッケージ化されたダイと同じ品質および信頼性を有していると概ね判断されたパッケージ化されていないダイのことである。   An integrated circuit may have a semiconductor die that is mechanically attached to a LOC (Lead-Over-Chip) lead frame and electrically connected to the LOC lead frame. The semiconductor die and lead frame are typically transfer encapsulated in a plastic package, ceramic package, or metal package. Using a Know-Good-Die (KGD) instead of a packaged die may improve manufacturing efficiency and reduce costs. A KGD is an unpackaged die that has been generally determined by inspection and / or operational testing to have the same quality and reliability as other equivalent packaged dies.

性能を向上させ、製造コストを低減した集積回路アセンブリと、その製造方法が必要とされている。   What is needed is an integrated circuit assembly with improved performance and reduced manufacturing costs, and a method of manufacturing the same.

大まかに言えば、基板上にＫｎｏｗ−Ｇｏｏｄ−Ｄｉｅ（ＫＧＤ）を使用した改良型集積回路アセンブリを提供する。基板上のパッドをトレースその他の導体に配線要素を用いて電気接続したり、基板上のパッドを他のダイ上のパッドに接続したりする。   Broadly speaking, an improved integrated circuit assembly using Know-Good-Die (KGD) on a substrate is provided. Pads on the substrate are electrically connected to traces or other conductors using wiring elements, or pads on the substrate are connected to pads on other dies.

次に、本発明の原理の理解を助けるために、図面に描かれた実施形態を参照して、具体的な言葉を用いてそれらの実施形態について説明する。ただし、それらに本発明の範囲を制限する意図はなく、例示する装置の変形や変更、並びに本明細書に記載する発明の原理のさらなる応用はすべて、本発明に関連する技術分野の当業者にとって普通に想起されるものと考えられる。   Next, in order to help understanding of the principle of the present invention, specific embodiments will be described with reference to the embodiments illustrated in the drawings. However, they are not intended to limit the scope of the present invention, and variations and modifications of the illustrated apparatus, as well as further applications of the principles of the invention described herein, are all known to those of ordinary skill in the art related to the present invention. It is thought to be recalled normally.

図１および図２は、本発明の一実施形態による集積回路アセンブリ１０を示す。アセンブリ１０は一般に、複数のダイ、好ましくは事前にテストされたＫｎｏｗ−Ｇｏｏｄ−Ｄｉｅ（ＫＧＤ）１２〜１５、および複数のボンディングワイヤ１８のような配線を含む。基板１９は、ダイの組み付けに適したものであればどのような基板でもよく、プリント回路基板、セラミック、プラスチック、可撓性回路などが挙げられるが、それらに限定される訳ではない。全ての集積回路を基板上に組み付ける最終組立ての前または後に、基板１９を研削または研磨して基板１９を薄くする場合があることに注意して欲しい。トレース２１は様々な組み合わせにより、電力、グラウンド、並びにデータ、アドレス、および制御などの信号を基板１９に接続された１以上のＫＧＤに提供するためのバスを形成する。基板１９には複数の開口部２３〜２６が互いに間隔を空けて形成され、それらが複数の位置でトレース１９を遮断している。開口部のサイズや形は様々であってよく、開口部は基板で完全に囲まれたものでも部分的に囲まれたものでもよく、それらの周辺付近に画定されるものであってもよい。このように、トレース２１のうちのあるものは、図示のように隣り合う一組の開口部２３〜２６間に延び、中央トレース２７と呼ばれる。各グループのトレース（すなわち、開口部２４と開口部２５の間に延びる５本のトレースからなるグループや、開口部２３から外側へ向けて延びる５本のトレースからなるグループ）は並んで延び、実質的に平行で、且つ実質的に同じ長さであることが望ましい。場合によっては、縁部補強材２８が基板１９の十分な部分に結合または使用され、その部分が補強される。図１の実施形態の場合、縁部補強材２８は、図示のように基板１９の周辺を取り囲む一対の金属ストリップ（１つは上、１つは下）からなる。トレース２１のうちのあるものは、基板１９の縁部から外側へ向けて延び、上位回路に接続するためのコネクタ２９を形成する。基板１９の縁部から外側へ向けて延びるトレースは、縁部トレース３０と呼ばれる。縁部トレース３０は補強材２８を貫通して延びている。補強材２８は、ヒートシンクとして機能するサイズおよび構成にしてもよい。ヒートシンクのサイズ、形、組成はどのようなものでもよく、棒状、プレート状、周囲フレーム（全部または一部）、その他が挙げられるが、それらに限定される訳ではない。基板１９が薄いものである場合（例えば、可撓性回路材料のような可撓性フィルムの場合）、補強材２８は、通常ならばダイの重さで湾曲してしまうであろう可撓性フィルム基板を実質的に平坦な形状に保つのに役立つ。ただし、上記のように可撓性フィルムは基板の一例に過ぎない。もっと硬い基板を使用すれば（例えば、プリント回路基板材料など）、補強材は不要な場合もある。   1 and 2 illustrate an integrated circuit assembly 10 according to one embodiment of the present invention. The assembly 10 generally includes a plurality of dies, preferably pre-tested Know-Good-Die (KGD) 12-15, and wiring such as a plurality of bonding wires 18. The substrate 19 may be any substrate suitable for die assembly and includes, but is not limited to, a printed circuit board, ceramic, plastic, flexible circuit, and the like. Note that the substrate 19 may be ground or polished to thin the substrate 19 before or after final assembly of all integrated circuits on the substrate. Traces 21 can be combined in various combinations to form a bus for providing power, ground, and signals such as data, address, and control to one or more KGDs connected to substrate 19. A plurality of openings 23 to 26 are formed in the substrate 19 at intervals, and these block the trace 19 at a plurality of positions. The size and shape of the openings may vary, and the openings may be completely enclosed or partially enclosed by the substrate and may be defined near their periphery. Thus, some of the traces 21 extend between a pair of adjacent openings 23-26 as shown and are referred to as central traces 27. Each group of traces (ie, a group of five traces extending between openings 24 and 25, or a group of five traces extending outwardly from opening 23) extends side by side, Preferably parallel and substantially the same length. In some cases, edge reinforcement 28 is bonded or used to a sufficient portion of substrate 19 to reinforce that portion. In the embodiment of FIG. 1, the edge reinforcement 28 consists of a pair of metal strips (one top and one bottom) surrounding the periphery of the substrate 19 as shown. Some of the traces 21 extend outward from the edge of the substrate 19 and form a connector 29 for connection to a higher circuit. A trace extending outward from the edge of the substrate 19 is referred to as an edge trace 30. The edge trace 30 extends through the stiffener 28. The reinforcement 28 may be sized and configured to function as a heat sink. The size, shape and composition of the heat sink may be anything, including but not limited to rods, plates, surrounding frames (all or part), etc. If the substrate 19 is thin (eg, in the case of a flexible film such as a flexible circuit material), the stiffener 28 is a flexible material that would normally be bent by the weight of the die. It helps to keep the film substrate in a substantially flat shape. However, as described above, the flexible film is only an example of a substrate. If a harder substrate is used (eg, a printed circuit board material), the reinforcing material may not be necessary.

米国特許第６，２１４，６４１Ｂ１号および第６，２１９，９０８Ｂ１号に記載されているように（これらは参照によって取り込まれる）、Ｋｎｏｗ−Ｇｏｏｄ−Ｄｉｅ（ＫＧＤ）とは、検査および／または稼動試験により、他の同等のパッケージ化されたダイと同じ品質および信頼性を概ね有しているものと判断されたパッケージ化されていないダイのことである。こうしたＫＧＤは基板に固定され、コンピュータ、電気通信装置、自動車、腕時計、電気器具、そして恐らくは非常に様々な電子機器に使用されるマルチチップモジュールを形成する。図１の集積回路アセンブリにおいて、ＫＧＤ１２〜１５はそれぞれ１以上の電気的なダイ接点、すなわちダイパッド３１を有している。各ダイパッド３１は、ＫＧＤの電気接点（例えば、グラウンド接続、電力接続、信号接続などに使用される）として機能する。ダイパッドの形や数は、ダイの設計に応じて任意の適当な形および数であってよい。ＫＧＤ１２〜１５は（図２に示すように）基板１９の下面３２に固定され、ダイパッド３１は対応する開口部２３〜２６の中に配置される。すなわち、ダイパッド３１には、基板１９の上面から開口部を通じて接続することができる。ＫＧＤ１２〜１５を基板１９に固定する手段は、接着剤３３のような一般的な任意の適当な手段であってよい。一般的なボンディング技術を使用して、トレース２１からダイパッド３１までワイヤ１８を接続したり、あるトレースの一端３６から別のトレースの一端３７まで開口部２４をまたいでワイヤ１８をジャンパ接続したりすることができる。ワイヤ接続を容易にするために、トレース端部（例えば３６や３７）は開口部２３〜２６の近くにおいてそれぞれ拡大されているので、ワイヤはそのようなトレース端部に接続することが望ましい。ただし、必要に応じて、あるいは特定の電気的構成を実現するために、トレース上の任意の点に１以上のワイヤ１８を接続する場合もあるものと考えられる。   As described in US Pat. Nos. 6,214,641B1 and 6,219,908B1, which are incorporated by reference, Know-Good-Die (KGD) is an inspection and / or operational test. Thus, an unpackaged die that has been determined to generally have the same quality and reliability as other equivalent packaged dies. These KGDs are secured to a substrate and form a multichip module used in computers, telecommunications devices, automobiles, watches, appliances, and possibly a great variety of electronic equipment. In the integrated circuit assembly of FIG. 1, each of the KGDs 12-15 has one or more electrical die contacts or die pads 31. Each die pad 31 functions as an electrical contact of KGD (for example, used for ground connection, power connection, signal connection, etc.). The shape and number of die pads may be any suitable shape and number depending on the die design. The KGDs 12-15 are fixed to the lower surface 32 of the substrate 19 (as shown in FIG. 2), and the die pad 31 is disposed in the corresponding openings 23-26. That is, the die pad 31 can be connected from the upper surface of the substrate 19 through the opening. The means for fixing the KGDs 12 to 15 to the substrate 19 may be any general suitable means such as the adhesive 33. A common bonding technique is used to connect the wire 18 from the trace 21 to the die pad 31 or to jumper the wire 18 across the opening 24 from one end 36 of one trace to the other end 37 of another trace. be able to. In order to facilitate wire connection, the trace ends (e.g., 36 and 37) are enlarged near the openings 23-26, respectively, so it is desirable to connect the wires to such trace ends. However, it is contemplated that one or more wires 18 may be connected to any point on the trace as needed or to achieve a specific electrical configuration.

図３は、基板１９の下側のダイ面にだけ補強材３９（およびヒートシンク）を使用する代替実施形態を示している。この例の場合、基板１９は可撓性回路であり、可撓性回路は外縁３４まで延び、そこで捲り返されるか、または小さな挿入基板（図示せず）を巻き込んで捲り返され、上位回路に接続するための代替接続面を形成する。   FIG. 3 shows an alternative embodiment that uses reinforcement 39 (and a heat sink) only on the lower die surface of substrate 19. In this example, the substrate 19 is a flexible circuit, which extends to the outer edge 34 where it is turned over or rolled back with a small insertion board (not shown) to the upper circuit. Form an alternate connection surface for connection.

図４および図５は、代替実施形態による集積回路アセンブリ４０を示す。トレース２１からなる層とトレース４１からなる層の２つの層が、基板１９に取り付けられている。トレース４１の通り道は絶縁層４２に埋め込まれ、トレース２１とトレース４１の間が絶縁層４２により絶縁されている。トレース２１からなる上側の層は図１の実施形態と同様に長手方向に延び、トレース４１からなる下側の層はそのトレース２１に対して横向きに、すなわち概ね垂直に延びている。トレース４１の外側の端部は基板１９および補強材４４から外向きに延び、基板１９の一部に沿ってその上にコネクタ４３が形成される。バイア４６は基板１９を貫通して延び、長手方向に延びる上側トレース２１を、それを横切る方向に延びる下側トレース４１に接続する働きをする。このような長手方向に延びるトレース、横切る方向に延びるトレース、およびバイアは、複雑な多層回路構造を形成するために、基板１９のどの部分に形成してもよい。例えば、基板１９の開口部２３〜２６の上および／または下にある層に途切れのないトレースを設け、別の層にその長手方向に延びるトレースから開口部間の表面領域まで通じる垂直バイアを形成し、さらに、バイアからダイパッドまでワイヤを接続する場合がある。横切る方向のトレースは、長手方向のトレース２１に対して概ね垂直に延びるものとして描かれている。ただし、この第２の下側トレース４１は、上側のトレース２１に対して９０度以外の角度で、互いに平行にならない角度で配置される場合もある。第２のトレース層（もし有れば第３のトレース層や第４のトレース層も）は単に、上側トレースの層に対して相互排他的であればよい。   4 and 5 show an integrated circuit assembly 40 according to an alternative embodiment. Two layers, a layer made of trace 21 and a layer made of trace 41, are attached to the substrate 19. The path of the trace 41 is embedded in the insulating layer 42, and the trace 21 and the trace 41 are insulated from each other by the insulating layer 42. The upper layer consisting of the traces 21 extends in the longitudinal direction as in the embodiment of FIG. 1, and the lower layer consisting of the traces 41 extends transversely, ie generally perpendicular to the traces 21. The outer end of the trace 41 extends outward from the substrate 19 and the reinforcing member 44, and a connector 43 is formed thereon along a part of the substrate 19. Via 46 extends through substrate 19 and serves to connect longitudinally extending upper trace 21 to lower trace 41 extending transversely thereto. Such longitudinally extending traces, transversely extending traces, and vias may be formed on any portion of the substrate 19 to form complex multilayer circuit structures. For example, uninterrupted traces are provided in the layers above and / or below the openings 23-26 of the substrate 19 and vertical vias extending from the longitudinally extending traces to the surface area between the openings are formed in another layer. In addition, there are cases where wires are connected from vias to die pads. The transverse trace is depicted as extending generally perpendicular to the longitudinal trace 21. However, the second lower trace 41 may be arranged at an angle other than 90 degrees with respect to the upper trace 21 and at an angle that is not parallel to each other. The second trace layer (and the third trace layer and fourth trace layer, if any) need only be mutually exclusive with respect to the upper trace layer.

図６〜図８は、基板４８が多層化された代替実施形態による集積回路アセンブリ４７を示す。バストレース４９（図７に描かれ、図６にも１本だけ破線で描かれている）はトレース２１と同様に基板４８に埋め込まれ、開口部５０〜５３により分断されている。開口部５０〜５３のうちの１つに向かって延びる大部分のトレース４９の端部は、接合端５５を形成する。基板４８の上側を外側へ向けて延びるトレース４９は、その一端４６に上位回路と接続するためのコネクタ５７を形成する。集積回路アセンブリ１０と同様に、接合端５５から基板４８の裏面に取り付けられたＫＧＤ６０〜６３のダイパッド５８にワイヤ６４を接続したり、ある接合端５５から別の接合端５５にワイヤ６４を接続したりすることができる。アセンブリ４７は更に、グラウンド平面トレース６４と電源平面トレース６７を有し、これらがそれぞれ基板４８の上側を長手方向に延びている。グラウンドトレース６６と電源トレース６７は、バイアにより基板４８に接続され（グラウンドトレース６６の場合、符号６９で示されているように）、それぞれ対応する横方向のトレース４９に接続され、横方向の埋め込みグラウンドトレースと横方向の埋め込み電源トレースを形成している（図面にはグラウンドトレース７０しか描いていない）。基板４８から外向きに延びるグラウンドトレースおよび電源トレースは、基板４８の縁部５６に、上位回路と接続するためのグランドコネクタ７２および電源コネクタ７３を形成している。   6-8 illustrate an integrated circuit assembly 47 according to an alternative embodiment in which the substrate 48 is multi-layered. A bus trace 49 (shown in FIG. 7 and only one broken line in FIG. 6) is embedded in the substrate 48 in the same manner as the trace 21 and is divided by openings 50 to 53. The end of most of the traces 49 extending toward one of the openings 50-53 forms a junction end 55. The trace 49 extending outward from the upper side of the substrate 48 forms a connector 57 for connecting to the upper circuit at one end 46 thereof. Similar to the integrated circuit assembly 10, the wire 64 is connected from the joint end 55 to the die pad 58 of the KGD 60 to 63 attached to the back surface of the substrate 48, or the wire 64 is connected from one joint end 55 to another joint end 55. Can be. The assembly 47 further includes a ground plane trace 64 and a power plane trace 67, each extending longitudinally above the substrate 48. The ground trace 66 and the power supply trace 67 are connected to the substrate 48 by vias (in the case of the ground trace 66, as indicated by reference numeral 69), each connected to a corresponding lateral trace 49 and laterally embedded. A ground trace and a laterally embedded power supply trace are formed (only the ground trace 70 is shown in the drawing). The ground trace and the power supply trace extending outward from the board 48 form a ground connector 72 and a power supply connector 73 for connecting to the upper circuit on the edge 56 of the board 48.

信号反射を抑制または低減するために、任意選択で、バスの末端部またはその近くに（任意形状の）抵抗器を設けてもよい。抵抗器は、ボンディングワイヤその他の配線要素によりトレースに接続される。任意選択で、抵抗器はグラウンドに接続してもよい。また、トレース間、またはトレースの周りにワイヤ、トレース、シールド、フィルムなどを配置し、アセンブリのトレース間または他の導体間における電気信号その他の信号の干渉を抑制または防止してもよい。   Optionally, a resistor (of any shape) may be provided at or near the end of the bus to suppress or reduce signal reflection. The resistor is connected to the trace by a bonding wire or other wiring element. Optionally, the resistor may be connected to ground. Also, wires, traces, shields, films, etc. may be placed between or around the traces to suppress or prevent electrical or other signal interference between the traces of the assembly or other conductors.

グラウンド平面トレース６６と電源平面トレース６７を基板４８へ向けて下向きに折り曲げ（符号６９に示すように）た後、さらに外向きに折り曲げ、基板４８の縁部５６から取り出してグラウンドコネクタ７２と電源コネクタ７３を直接形成し、グラウンドトレース７０や電源トレース７１を使用しない代替実施形態も考えられる。   The ground plane trace 66 and the power plane trace 67 are bent downward (as indicated by reference numeral 69) toward the board 48, then further bent outward, taken out from the edge 56 of the board 48, and ground connector 72 and the power connector. Alternative embodiments are possible where 73 is formed directly and no ground trace 70 or power supply trace 71 is used.

グラウンドや電源をグラウンドトレース７０と電源トレース７１のみによって供給し、グランドトレース７０と電源トレース７１を縁部コネクタ７１および７２で終端し、グラウンド平面トレース６６や電源平面トレース６７を全く形成しない代替実施形態も考えられる。   An alternative embodiment in which ground or power is supplied by ground trace 70 and power trace 71 only, ground trace 70 and power trace 71 are terminated by edge connectors 71 and 72, and no ground plane trace 66 or power plane trace 67 is formed. Is also possible.

グラウンド平面トレース６６と電源平面トレース６７をバストレース（図１のトレース２１のような）で置き換える実施形態も考えられ、その場合、埋め込みグラウンドトレース７０および／または埋め込み電源トレース７１は使用してもしなくてもよい。   Embodiments in which the ground plane trace 66 and the power plane trace 67 are replaced with bus traces (such as trace 21 in FIG. 1) are also contemplated, in which case the embedded ground trace 70 and / or embedded power trace 71 may or may not be used. May be.

バストレースを基板４８の外側表面に設け（図１や他の図面のトレース２１のように）、そこに接続されたボンディングワイヤを用いて、必要に応じて電源、グラウンド、信号などを供給する代替実施形態も考えられる。このような表面実装型バストレースは、本明細書に記載する埋め込みトレースや平面トレースの代わりに設けてもよいし、それらに追加して設けてもよい。   An alternative to providing bus traces on the outer surface of the substrate 48 (like trace 21 in FIG. 1 and other figures) and using bonding wires connected thereto to supply power, ground, signals, etc. as needed Embodiments are also conceivable. Such a surface mount type bus trace may be provided in place of the embedded trace or the planar trace described in this specification, or may be additionally provided.

図９は、ＫＧＤ７７〜８０が基板８１の両面に取り付けられた代替実施形態による集積回路アセンブリ７６を示す。   FIG. 9 shows an integrated circuit assembly 76 according to an alternative embodiment with KGD 77-80 attached to both sides of the substrate 81. FIG.

図１０は、図１や図２のアセンブリ１０と同様にバストレース８３が基板８４に表面実装された代替実施形態による集積回路アセンブリ８２を示す。ＫＧＤ８６〜８９は基板８４の両面に表面実装され、少なくとも１つのＫＧＤが表面実装トレース８３の上に直接取り付けられている。ＫＧＤ８７および８９をトレース８３上に取り付けできるようにするために、一部のトレース８３は図示のように対応する開口部９１および９２の中にまで延び、そこにワイヤ９３を接続できるようになっている。あるいは、図４および図５の集積回路アセンブリ４０について説明したように、複数階層のトレースを使用してもよい。例えば、基板開口部の上および／または下にある層に途切れのない横方向トレースを設け、別の層にそれらの横方向トレースから開口部間の領域まで延びる垂直トレースを設け、さらに、垂直トレースからダイパッドまでワイヤを接続することもできる。このようなトレース構成は、基板の片面に設けることも両面に設けることもできる。   FIG. 10 shows an integrated circuit assembly 82 according to an alternative embodiment in which a bus trace 83 is surface mounted to a substrate 84, similar to the assembly 10 of FIGS. The KGDs 86-89 are surface mounted on both sides of the substrate 84 and at least one KGD is mounted directly on the surface mounted trace 83. In order to allow KGDs 87 and 89 to be mounted on trace 83, some traces 83 extend into corresponding openings 91 and 92 as shown so that wire 93 can be connected thereto. Yes. Alternatively, multiple layers of traces may be used as described for integrated circuit assembly 40 of FIGS. For example, there are uninterrupted lateral traces in the layers above and / or below the substrate openings, vertical traces extending from those lateral traces to the area between the openings in the other layers, and the vertical traces Wires can also be connected from to the die pad. Such a trace configuration can be provided on one side or both sides of the substrate.

図１１は、複数の縁部トレース９６が外側の開口部から外側へ向けて延び、基板長手方向の中間点まで折り返し、基板の横縁から外側へ延びて横縁コネクタ９７を形成する、代替実施形態による集積回路アセンブリ９５を示す。   FIG. 11 shows an alternative implementation in which a plurality of edge traces 96 extend outwardly from the outer opening, fold back to the mid-board midpoint, and extend outwardly from the lateral edge of the substrate to form the lateral edge connector 97. Fig. 9 shows an integrated circuit assembly 95 according to configuration.

図１〜図１１に開示した実施形態の種々の態様を詳しく開示されていない組み合わせで組み合わせた実施形態も考えられる。限定はしないが例えば、図１１の実施形態は、基板の上面と下面の両方に取り付けられたＫＧＤを有することもでき、および／または、２以上の異なるトレース層を有することもできる。種々の形の補強材、カバー、および／または、他の適当な保護材料（参照により本明細書に取り込まれた米国特許第６，２１４，６４１号に開示されている非導電性粘性物質の塊など）を基板、および／または、基板の周りに使用し、基板、ＫＧＤ、トレース、ワイヤなどを補強または保護する実施形態も考えられる。ＫＧＤ、ワイヤおよび関連部品を支持するとともに、取り扱い、およびいかなる磨耗および亀裂にも耐える何らかの適当な材料から基板を構成する実施形態も考えられる。限定はしないが、そうした材料には、可撓性のシリコン、セラミック、エポキシ樹脂、ポリアミド、テフロン、フッ素樹脂の他、有機材料や誘電体材料などがある。   Embodiments combining various aspects of the embodiments disclosed in FIGS. 1-11 in combinations not disclosed in detail are also contemplated. For example, without limitation, the embodiment of FIG. 11 can have a KGD attached to both the top and bottom surfaces of the substrate, and / or can have two or more different trace layers. Various forms of reinforcements, covers, and / or other suitable protective materials (a mass of non-conductive viscous material as disclosed in US Pat. No. 6,214,641, incorporated herein by reference) Etc.) may be used to reinforce or protect the substrate, KGD, traces, wires, etc. using the substrate and / or around the substrate. Embodiments are also contemplated in which the substrate is constructed from any suitable material that supports the KGD, wires, and related components, and that is resistant to handling and any wear and cracking. Such materials include, but are not limited to, flexible silicon, ceramics, epoxy resins, polyamides, Teflon, fluororesins, organic materials and dielectric materials.

図１２および図１３は、トレース１０６がバスとして機能するように配線された集積回路アセンブリ１０５の一構成例を示す。つまり、バスの形成は、各トレースの端部（例えば１０７）をワイヤ１０９でダイパッド１０８に接続した後、さらにそれを次のトレース端部（例えば１１０）に別のワイヤ１０９で接続することにより行われる。   12 and 13 show an example configuration of the integrated circuit assembly 105 in which the trace 106 is wired so as to function as a bus. In other words, the bus is formed by connecting the end of each trace (for example 107) to the die pad 108 with a wire 109 and then connecting it to the next trace end (for example 110) with another wire 109. Is called.

図１４は、集積回路アセンブリ１０５と同様にトレースがバスとして機能するように配線された代替実施形態による集積回路アセンブリ１１３を示す。隣りあう各対の開口部（例えば１１４と１１５）の間において、基板１１７の上に配置されたトレース１１６は、バイア１１８により基板１１７下側のトレース１１９に接続される。ＫＧＤは、フィルム１１７の上側と下側に交互に取り付けられ、あるＫＧＤのダイパッド１２０は、図示のようにワイヤ１２１、上側トレース１１６、下側トレース１１９、およびもう１つのワイヤ１２１を介して隣りのＫＧＤ１２４のダイパッド１２０に接続される。このようにして、すべてのＫＧＤ１２３〜１２６が実質的に共通バスに沿って接続される。あるいは、バイア１１８で相互接続された互い違い構成のトレース（すなわち１１６と１１９）を何らかの所望の態様でＫＧＤに接続し、それを連続バス等にしてもよい。図７のグラウンドトレース７０のように、基板１９の上面と下面の間にグラウンド平面板を埋め込む代替実施形態も考えられる。こうしたグラウンド平面板は、バイアおよびトレースのインピーダンスを調節するのに使用される。グラウンド平面板は、任意の所望の形に作成することができる。グラウンド平面版は、例えば図６のトレース４９と同じくらい細く作成してもよいし、基板の全幅と同じくらい太く作成することもでき、両者の間の任意の幅または形に作成することができる。グラウンド平面板は、絶縁された開口部を有することが望ましく、その中に１以上のバイア１１８を通すことが望ましい。トレースのうちの１以上は、グラウンド平面板に接続される場合がある。   FIG. 14 shows an integrated circuit assembly 113 according to an alternative embodiment in which the traces are wired to function as a bus, similar to the integrated circuit assembly 105. Between each pair of adjacent openings (eg, 114 and 115), trace 116 disposed on substrate 117 is connected to trace 119 below substrate 117 by via 118. The KGD is mounted alternately on the upper and lower sides of the film 117, and one KGD die pad 120 is adjacent to each other via a wire 121, an upper trace 116, a lower trace 119, and another wire 121 as shown. Connected to the die pad 120 of the KGD 124. In this way, all KGDs 123-126 are connected substantially along the common bus. Alternatively, staggered traces (ie, 116 and 119) interconnected by vias 118 may be connected to the KGD in any desired manner, making it a continuous bus or the like. Alternative embodiments in which a ground plane plate is embedded between the upper and lower surfaces of the substrate 19, such as the ground trace 70 of FIG. Such ground plane plates are used to adjust the impedance of vias and traces. The ground plane plate can be made in any desired shape. The ground plane plate may be made as thin as, for example, the trace 49 in FIG. 6, or as thick as the entire width of the substrate, and can be made in any width or shape between them. . The ground plane plate preferably has an insulated opening and one or more vias 118 are preferably passed therethrough. One or more of the traces may be connected to a ground plane plate.

図１５は、図５の集積回路アセンブリ４０に似た代替実施形態による集積回路アセンブリ１３２を示す。ただし、横方向に延びるトレース１３４が基板１９に埋め込まれ、トレース１３４が必要に応じてバイア１３６により上側の長手方向に延びるトレース１３５の層に接続されている点が異なる。   FIG. 15 shows an integrated circuit assembly 132 according to an alternative embodiment similar to the integrated circuit assembly 40 of FIG. The only difference is that a laterally extending trace 134 is embedded in the substrate 19 and that the trace 134 is connected to an upper longitudinally extending layer of trace 135 by vias 136 as required.

本明細書に記載する実施形態は、トレースをダイパッドや他のトレースに接続するための配線としてワイヤ（例えば、図１のワイヤ１８）を使用している。本発明で使用される配線には、ある電気的なダイ接点またはトレースを別の電気的なダイ接点またはトレースに電気接続するのに適した任意のデバイス、材料または要素が含まれる。他の配線や、他の配線を使用する方法も考えられ、限定はしないが、例えば導電性ポリマー、接着剤またはエポキシなどをリソグラフィにより転写し、マスクスクリーンやディスペンサを使用するといった方法もある。図１６〜図１７はさらに他の実施形態を示す。図１６に示す集積回路アセンブリ１３９では、超音波ボンディングにより、あるトレース１４１から別のトレース１４２までストリップトレース１４０を接着している。図１７の場合、ストリップトレース１４０は、あるトレース１４１からダイパッド１４３まで下がり、反対側の隣りのトレース１４２に戻るように接着される。   The embodiments described herein use wires (eg, wire 18 in FIG. 1) as wiring to connect traces to die pads or other traces. The wiring used in the present invention includes any device, material or element suitable for electrically connecting one electrical die contact or trace to another electrical die contact or trace. Other wirings and methods using other wirings are also conceivable and are not limited. For example, there is a method of transferring a conductive polymer, adhesive, epoxy, or the like by lithography and using a mask screen or a dispenser. 16 to 17 show still another embodiment. In the integrated circuit assembly 139 shown in FIG. 16, the strip trace 140 is bonded from one trace 141 to another trace 142 by ultrasonic bonding. In the case of FIG. 17, the strip trace 140 is glued so as to descend from one trace 141 to the die pad 143 and back to the adjacent trace 142 on the opposite side.

図１８〜図１９は、ストリップトレース１４８が基板１４９の長手方向に沿って種々の開口部１５１および１５２の上に配置された代替回路アセンブリ１４７を示す。その後必要に応じて、ワイヤボンディングや本明細書に記載している他の方法などの任意の適当な方法を用いて、ストリップトレース１４８がその下のダイパッド１５３に接続される。ストリップトレース１４８をダイパッド１５８に接続する方法は他にもあり、例えば導電性ボール１５４（図１９）を使用すること、ストリップトレース１４８を接着するときにバンプ１５５を最初から形成しておくこと（図２０）、ストリップトレース１４８を接着（図１８のように）した後でストリップトレース１４８のダイパッドの位置を変形させ、接続用バンプ１５５を形成することなどが考えられる。あるいは、トレースを接続しようとするダイパッド１５３の上に、バンプやボールを直接形成してもよい（ダイを基板に接着する前に行うのが好ましい）。   FIGS. 18-19 illustrate alternative circuit assemblies 147 in which strip traces 148 are disposed over various openings 151 and 152 along the length of substrate 149. The strip trace 148 is then connected to the underlying die pad 153 using any suitable method, such as wire bonding or other methods described herein, as needed. There are other ways to connect the strip trace 148 to the die pad 158, for example, using conductive balls 154 (FIG. 19), or forming the bump 155 from the beginning when bonding the strip trace 148 (FIG. 20) After bonding the strip trace 148 (as shown in FIG. 18), the position of the die pad of the strip trace 148 may be deformed to form the connection bump 155. Alternatively, bumps or balls may be formed directly on the die pad 153 to which the trace is to be connected (preferably before bonding the die to the substrate).

図２１は、図１７の構造を示し、トレース１４１と配線要素１４０の上に第１の絶縁材料１６０が配置されている。第１の絶縁材料１６０の上に導電体層１６２が配置され、導電体層１６２の上に第２の絶縁材料１６４が配置される。トレース１４１および配線要素１４０のインピーダンスを調節するために、導電体層１６２はグラウンドまたは電源に接続することができる。あるいは、導電体層１６２は、グラウンドにも電源にも接続せず、トレース１４１、配線要素１４０およびダイ１２３を単にシールドするものにしてもよい。当然ながら、層１６０、１６２および１６４は、アセンブリの一部を包むものであってもよいし、全体を包むものであってもよい。さらに他の代替として、導電体層１６２は、基板１１７に取り付けられた金属ケースであってもよい。そのような場合、層１６４は空気として実施することができ、層１６０も空気にすることができる。当然ながら、類似の層１６０、１６２、および１６４は、本明細書に記載しているどの実施形態にも使用することができる。   FIG. 21 shows the structure of FIG. 17, in which a first insulating material 160 is disposed on the trace 141 and the wiring element 140. A conductor layer 162 is disposed on the first insulating material 160, and a second insulating material 164 is disposed on the conductor layer 162. In order to adjust the impedance of the trace 141 and the wiring element 140, the conductor layer 162 can be connected to ground or a power source. Alternatively, the conductor layer 162 may simply shield the trace 141, the wiring element 140, and the die 123 without connecting to ground or a power source. Of course, the layers 160, 162 and 164 may wrap part of the assembly or wrap the whole. As yet another alternative, the conductor layer 162 may be a metal case attached to the substrate 117. In such cases, layer 164 can be implemented as air and layer 160 can also be air. Of course, similar layers 160, 162, and 164 can be used in any of the embodiments described herein.

図２２および図２３は、マイクロプロセッサ２０２がはんだボール２１８によりトレース２１０および２１２に接続される実施形態を示す。４つのメモリダイ２０４が、図２２および図２３に示すように、配線要素２１４およびトレース２１０によってマイクロプロセッサ２０２に接続されている。当然ながら、図２２および図２３は、様々なタイプのダイを組み合わせて電子システムを形成するシステムの一例を示しているに過ぎない。無線周波数ダイ、アナログダイ、ロジックダイ、または、他のタイプのダイを組み合わせて配線することにより、そのようなシステムが形成される。   22 and 23 illustrate an embodiment in which the microprocessor 202 is connected to traces 210 and 212 by solder balls 218. FIG. Four memory dies 204 are connected to the microprocessor 202 by wiring elements 214 and traces 210 as shown in FIGS. Of course, FIGS. 22 and 23 show only one example of a system that combines various types of dies to form an electronic system. Such systems are formed by wiring a combination of radio frequency dies, analog dies, logic dies, or other types of dies.

図２４および図２５は、ダイ３０４が基板３０６の表面に接着される実施形態を示す。トレース３１０が、接続端３２０からダイ３０４の横の空間まで延びている。配線要素３１４は、ダイ３０４上の端子３１６をトレース３１０に接続している。また、幾つかの配線要素３２０は、ダイ３０４上の端子３１６を別のダイ上の端子３１６に接続している。   FIGS. 24 and 25 illustrate an embodiment in which the die 304 is bonded to the surface of the substrate 306. A trace 310 extends from the connection end 320 to the space next to the die 304. Wiring element 314 connects terminal 316 on die 304 to trace 310. Some wiring elements 320 also connect a terminal 316 on the die 304 to a terminal 316 on another die.

図２６および図２７は、基板４０６の裏面（すなわち、ダイ４０４が接着される面）の開口部間にトレース４１０が配置される、更に他の実施形態を示す。図２６および図２７に示すように、配線要素４１４はダイ４０４上の端子４１６をバイア４２０に接続している。バイア４２０は基板４０６を貫通してトレース４１０まで通じている。   FIGS. 26 and 27 show yet another embodiment in which traces 410 are disposed between openings in the back surface of substrate 406 (ie, the surface to which die 404 is bonded). As shown in FIGS. 26 and 27, the wiring element 414 connects the terminal 416 on the die 404 to the via 420. Via 420 passes through substrate 406 to trace 410.

本発明は図面と上記の説明に詳しく描かれ説明されているが、それらは例と考えるべきものであり、制限的性質を有するものではなく、好ましい実施形態を図示説明したものにすぎない。本発明の思想の範囲内に属する変形や変更は、すべて保護されることが望ましい。「ａ」、「ａｎ」、「ｓａｉｄ」、および「ｔｈｅ」という冠詞は、単数の要素に限定するためのものではなく、そのような要素を１以上含むことを意味している。   While the invention has been illustrated and described in detail in the drawings and foregoing description, they are to be considered as illustrative and not restrictive in nature and are merely illustrative of preferred embodiments. It is desirable that all modifications and changes belonging to the scope of the idea of the present invention be protected. The articles “a”, “an”, “said”, and “the” are not intended to be limiting to a single element, but are meant to include one or more such elements.

本発明の一実施形態による集積回路アセンブリ１０を示す平面図である。1 is a plan view illustrating an integrated circuit assembly 10 according to an embodiment of the present invention. 図１の集積回路アセンブリ１０を線２−２に沿って切断し、矢印の方向から見たときの側断面図である。FIG. 2 is a side sectional view of the integrated circuit assembly 10 of FIG. 1 taken along line 2-2 and viewed from the direction of the arrow. 図１の集積回路アセンブリ１０の代替実施形態の側断面図である。2 is a cross-sectional side view of an alternative embodiment of the integrated circuit assembly 10 of FIG. 本発明の他の実施形態による集積回路アセンブリ４０を示す平面図である。6 is a plan view illustrating an integrated circuit assembly 40 according to another embodiment of the present invention. FIG. 図４の集積回路アセンブリ４０を線５−５に沿って切断し、矢印の方向から見たときの側断面図である。FIG. 5 is a side sectional view of the integrated circuit assembly 40 of FIG. 4 taken along line 5-5 and viewed from the direction of the arrow. 本発明の他の実施形態による集積回路アセンブリ４７を示す平面図である。FIG. 6 is a plan view showing an integrated circuit assembly 47 according to another embodiment of the present invention. 図６の集積回路アセンブリ４７を線７−７に沿って切断し、矢印の方向から見たときの側断面図である。FIG. 7 is a side cross-sectional view of the integrated circuit assembly 47 of FIG. 6 taken along line 7-7 and viewed from the direction of the arrow. 図６の集積回路アセンブリ４７の底面図である。FIG. 7 is a bottom view of the integrated circuit assembly 47 of FIG. 6. 本発明の他の実施形態による集積回路アセンブリ７６の側断面図である。FIG. 7 is a side cross-sectional view of an integrated circuit assembly 76 according to another embodiment of the present invention. 本発明の他の実施形態による集積回路アセンブリ８２の側断面図である。FIG. 6 is a side cross-sectional view of an integrated circuit assembly 82 according to another embodiment of the present invention. 本発明の他の実施形態による集積回路アセンブリ９５を示す平面図である。FIG. 9 is a plan view illustrating an integrated circuit assembly 95 according to another embodiment of the present invention. 本発明の他の実施形態による集積回路アセンブリ１０５を示す平面図である。FIG. 6 is a plan view illustrating an integrated circuit assembly 105 according to another embodiment of the present invention. 図１２の集積回路アセンブリ１０５を線１３−１３に沿って切断し、矢印の方向から見たときの側断面図である。FIG. 13 is a cross-sectional side view of the integrated circuit assembly 105 of FIG. 12 taken along line 13-13 and viewed from the direction of the arrows. 本発明の他の実施形態による集積回路アセンブリ１１３の側断面図である。FIG. 11 is a side cross-sectional view of an integrated circuit assembly 113 according to another embodiment of the present invention. 本発明の他の実施形態による集積回路アセンブリの側断面図である。6 is a cross-sectional side view of an integrated circuit assembly according to another embodiment of the present invention. FIG. 本発明の他の実施形態による集積回路アセンブリの側断面図である。6 is a cross-sectional side view of an integrated circuit assembly according to another embodiment of the present invention. FIG. 本発明の他の実施形態による集積回路アセンブリの側断面図である。6 is a cross-sectional side view of an integrated circuit assembly according to another embodiment of the present invention. FIG. 本発明の他の実施形態による集積回路アセンブリの側断面図である。6 is a cross-sectional side view of an integrated circuit assembly according to another embodiment of the present invention. FIG. 本発明の他の実施形態による集積回路アセンブリの側断面図である。6 is a cross-sectional side view of an integrated circuit assembly according to another embodiment of the present invention. FIG. 本発明の他の実施形態による集積回路アセンブリの側断面図である。6 is a cross-sectional side view of an integrated circuit assembly according to another embodiment of the present invention. FIG. 導電性トレースおよび配線要素のインピーダンスを調節するための、導電性トレースおよび配線要素から絶縁された導電性平面板の追加を示す図である。FIG. 5 shows the addition of a conductive planar plate insulated from the conductive traces and wiring elements to adjust the impedance of the conductive traces and wiring elements. 相互接続された異なるタイプの集積回路を含むシステムの組み立てを示す平面図である。1 is a plan view illustrating the assembly of a system including different types of integrated circuits interconnected. FIG. 図２２のアセンブリの側面図である。FIG. 23 is a side view of the assembly of FIG. ある集積回路から別の集積回路に直接配線されるアセンブリの平面図である。1 is a plan view of an assembly that is wired directly from one integrated circuit to another. FIG. 図２４のアセンブリの側断面図である。FIG. 25 is a cross-sectional side view of the assembly of FIG. 24. ダイ上の端子から基板のバイアまで配線され接続される本発明の一実施形態を示す平面図である。It is a top view which shows one Embodiment of this invention wired and connected from the terminal on die | dye to the via | veer of a board | substrate. 図２６のアセンブリの側断面図である。FIG. 27 is a side cross-sectional view of the assembly of FIG. 26.

Claims (17)

基板と、
前記基板を貫通する第１の開口部と、
前記基板に取り付けられた第１のダイであって、前記開口部の中に位置する第１のダイ接点を有する第１のダイと、
前記基板に取り付けられた第１のトレースと、
前記基板に取り付けられた第２のトレースと、
前記第１の開口部の上をまたいで前記第１のトレースを前記第２のトレースに接続する第１の配線と、
を含む集積回路アセンブリ。A substrate,
A first opening penetrating the substrate;
A first die attached to the substrate, the first die having a first die contact located in the opening;
A first trace attached to the substrate;
A second trace attached to the substrate;
A first interconnect connecting the first trace to the second trace across the first opening;
An integrated circuit assembly. 前記第１の配線は、前記第１のトレースおよび前記第２のトレースに接続されたワイヤを含む、請求項１に記載の集積回路アセンブリ。The integrated circuit assembly of claim 1, wherein the first wiring includes wires connected to the first trace and the second trace. 前記ワイヤは更に、前記第１のダイ接点にも接続される、請求項２に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 2, wherein the wire is further connected to the first die contact. 前記第１の配線は、
前記第１のトレースおよび前記第１のダイ接点に接続された第１のワイヤと、
前記第２のトレースおよび前記第１のダイ接点に接続された第２のワイヤと、
を含む、請求項１に記載の集積回路アセンブリ。The first wiring is
A first wire connected to the first trace and the first die contact;
A second wire connected to the second trace and the first die contact;
The integrated circuit assembly of claim 1, comprising: 前記第１の配線はストリップトレースを含む、請求項１に記載の集積回路アセンブリ。The first wiring comprises a strip traces, integrated circuit assembly according to claim 1. 前記ストリップトレースは、前記第１のトレースおよび前記第２のトレースに接続される、請求項５に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 5, wherein the strip trace is connected to the first trace and the second trace. 前記ストリップトレースは更に、前記第１のダイ接点にも接続される、請求項６に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 6, wherein the strip trace is further connected to the first die contact. 前記第１のトレースと、前記第２のトレースと、前記ストリップトレースとが、１つの一体型トレースを形成する、請求項５に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 5, wherein the first trace, the second trace, and the strip trace form one integrated trace. 前記第１のトレースは前記基板に埋め込まれ、前記基板から前記第１の開口部の中に張り出している、請求項１に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 1, wherein the first trace is embedded in the substrate and extends from the substrate into the first opening. 前記第２のトレースは前記基板に埋め込まれ、前記基板から前記第１の開口部の中に張り出している、請求項９に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 9, wherein the second trace is embedded in the substrate and extends from the substrate into the first opening. 前記基板は薄い可撓性フィルムを含む、請求項１に記載の集積回路アセンブリ。Wherein the substrate comprises a thin flexible film, integrated circuit assembly according to claim 1. 前記基板は第２の開口部を更に備え、前記集積回路アセンブリは、
前記基板に取り付けられた第２のダイであって、前記第２の開口部の中に位置する第２のダイ接点を有する第２のダイと、
前記第２のダイ接点を前記第２のトレースに接続する第２の配線と、
を更に含む、請求項１に記載の集積回路アセンブリ。The substrate further comprises a second opening, and the integrated circuit assembly comprises:
A second die attached to the substrate, the second die having a second die contact located in the second opening;
A second wiring connecting the second die contact to the second trace;
The integrated circuit assembly of claim 1, further comprising: 前記第１のダイおよび前記第２のダイは、前記基板の両面で基板に取り付けられる、請求項１２に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 12, wherein the first die and the second die are attached to a substrate on both sides of the substrate. 前記第１のトレース、前記第２のトレース、および前記第１の配線を電気的にシールドする手段を更に含む、請求項１に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 1 further comprising means for electrically shielding the first trace, the second trace, and the first wiring. 前記第１のトレース、前記第２のトレース、および前記第１の配線のインピーダンスを調節する手段を更に含む、請求項１に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 1 further comprising means for adjusting impedance of the first trace, the second trace, and the first wiring. 前記第１のトレースおよび前記第２のトレースのうちの一方の末端部の近くに抵抗器手段を更に含む、請求項１に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 1 further comprising resistor means near a distal end of one of the first trace and the second trace. 前記第１のダイは、パッケージ化されていないダイである、請求項１に記載の集積回路アセンブリ。  The integrated circuit assembly of claim 1, wherein the first die is an unpackaged die.
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KR20050085561A (en) 2005-08-29
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TWI339435B (en) 2011-03-21
AU2003299608A1 (en) 2004-07-09
US20040113250A1 (en) 2004-06-17
CN1742372A (en) 2006-03-01
WO2004055895A1 (en) 2004-07-01
US7550842B2 (en) 2009-06-23
EP1573815A1 (en) 2005-09-14
JP2006510224A (en) 2006-03-23
TW200425462A (en) 2004-11-16

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