CN109509728B - Electronic package - Google Patents
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- CN109509728B CN109509728B CN201711062669.3A CN201711062669A CN109509728B CN 109509728 B CN109509728 B CN 109509728B CN 201711062669 A CN201711062669 A CN 201711062669A CN 109509728 B CN109509728 B CN 109509728B
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- 238000009826 distribution Methods 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 24
- 239000004065 semiconductor Substances 0.000 description 20
- 239000000758 substrate Substances 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- 239000012792 core layer Substances 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
An electronic package is provided, and a plurality of grounding areas with grounding contacts are defined on the surface of a bearing structure, so that an electronic element can be selectively and electrically connected with the grounding contact of at least one grounding area according to the functional specification of the electronic element, and the larger or smaller grounding potential required by the electronic element is met.
Description
Technical Field
The present invention relates to a package technology, and more particularly, to an electronic package capable of improving electrical performance.
Background
With the development of semiconductor technology, semiconductor products have been developed with different types of package products, and in order to improve electrical quality, various semiconductor products have a shielding function to prevent Electromagnetic Interference (EMI).
As shown in fig. 1A and 1B, in the conventional semiconductor package 1, a semiconductor chip 11 is disposed on a package substrate 10, an encapsulant 12 is used to encapsulate the semiconductor chip 11, and then a metal shielding layer 13 is formed on the encapsulant 12 and the side surface 10c of the package substrate 10, so as to be electrically connected to a grounding portion 102 exposed on the side surface 10c of the package substrate 10 through the metal shielding layer 13, and then grounded to an external system, thereby protecting the semiconductor chip 11 from being damaged by external EMI.
The conventional package substrate 10 generally has a plurality of circuit layers 100, wherein the circuit layers 100 are separated from each other by an insulating layer, and a plurality of conductive blind vias are formed in the insulating layer to electrically connect the circuit layers 100. The lower circuit layer 100 also has a plurality of ball-mounting pads 101 for the semiconductor package 1 to be externally connected to a printed circuit board (not shown), and the upper circuit layer 100 includes a ground region G and a signal region S, such that the ground contact 103 of the ground region G is electrically connected to the ground portion 102 of the circuit layer 100 and electrically connected to the ground pad 110 of the semiconductor chip 11 through a plurality of bonding wires 14, and the signal contact 104 of the signal region S is electrically connected to the signal pad 111 of the semiconductor chip 11 through a plurality of bonding wires 14.
However, in the conventional semiconductor package 1, the functions required by the semiconductor chip 11 are more and more, so that the semiconductor chip 11 needs to transmit/receive more signals, and the current passing through the semiconductor chip 11 through the signal pad 111 increases, so that the ground potential required by the semiconductor chip 11 increases, and the single ground region G of the package substrate 10 cannot meet the ground potential requirement of the semiconductor chip 11.
Therefore, how to overcome the above problems of the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides an electronic package that satisfies the ground potential requirements of the electronic component, which may be larger or smaller.
The electronic package of the present invention includes: the bearing structure is defined with a first grounding area and a second grounding area, wherein the first grounding area is provided with at least one first grounding contact, and the second grounding area is provided with at least one second grounding contact; and the electronic element is arranged on the bearing structure and is electrically connected with the first grounding contact and/or the second grounding contact, and the electronic element is positioned in the first grounding area, so that part of the first grounding area is positioned between the second grounding area and the electronic element.
In the electronic package, the distribution area of the first ground region is greater than or equal to the distribution area of the second ground region.
In the electronic package, the carrier structure is provided with a plurality of the first ground contacts and a plurality of the second ground contacts.
In the foregoing electronic package, the electronic element has a pad, and the pad is electrically connected to the first ground contact through a first conductive element. For example, the first conductive element is a bonding wire. Further, the first ground contact is electrically connected to a second ground contact through a second conductive element, for example, the second conductive element is a bonding wire.
In the electronic package, the second ground region is further provided with at least one signal contact electrically connected to the signal contact and the electronic device through a third conductive element. For example, the third conductive element is a bonding wire. Furthermore, the electronic element is provided with an electrode pad which is used for electrically connecting the third conductive element, and the electrode pad and the signal contact are arranged on the same straight line.
In the foregoing electronic package, the electronic component has a pad for electrically connecting the first and/or second ground contacts, and the pad, the first ground contact and the second ground contact are arranged in a same straight line.
The electronic package further includes a package layer formed on the carrier structure and covering the electronic device.
In the electronic package, a signal line is formed between the first ground region and the second ground region.
In the electronic package, the electronic element has a pad, and the pad is electrically connected to the second ground contact through a fourth conductive element.
As can be seen from the above, the electronic package of the present invention defines a plurality of grounding areas (i.e., a first grounding area and a second grounding area) mainly through the supporting structure, so that the electronic component can be selectively electrically connected to the first and/or second grounding contacts.
Drawings
FIG. 1A is a cross-sectional view of a conventional semiconductor package;
FIG. 1B is a partial top view of FIG. 1A;
FIG. 2A is a schematic cross-sectional view of an electronic package according to the present invention;
FIGS. 2B and 2C are partial top views of FIG. 2A;
FIG. 2D is another schematic cross-sectional view of an electronic package according to the present invention;
FIG. 3 is a schematic partial top view of another embodiment of an electronic package of the present invention;
FIG. 4A is a schematic cross-sectional view of an electronic package according to still another embodiment of the present invention; and
fig. 4B is a partial top view of fig. 4A.
Description of the symbols:
1 semiconductor package
10 packaging substrate
10c side surface
100 line layer
101 ball-planting pad
102 ground part
103 ground contact
104,200b signal contact
11 semiconductor wafer
110 ground pad
111 signal pad
12 packaging colloid
13 metallic shield layer
14 welding wire
2,3 electronic package
20 load bearing structure
20a surface
200 line
200a conductive trace
200c electrical terminals
201 first ground contact
202 second ground contact
21,51 first conductive element
22 second conductive element
23 third conductive element
24 electronic component
240 pad
241 electrode pad
25 encapsulation layer
300 signal line
54 fourth conductive element
A first ground region
B second ground region
C, D dotted line
Length of L, r, t
G ground region
An S signal region.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Fig. 2A to 2D are schematic diagrams of a first embodiment of an electronic package 2 according to the present invention.
As shown in fig. 2A to 2D, the electronic package 2 includes: a carrier structure 20, at least one electronic component 24, at least one first conductive element 21, at least one second conductive element 22, and an encapsulation layer 25.
The carrier structure 20 defines a first ground area a and a second ground area B separated from each other on a surface 20a, and the electronic component 24 is located in the first ground area a, such that a portion of the first ground area a is located between the second ground area B and the electronic component 24, that is, the first ground area a is closer to the electronic component 24 than the second ground area B, wherein a plurality of (three as shown in the figure) first ground contacts 201 are disposed on the first ground area a, and a plurality of (three as shown in the figure) circuits 200 and a plurality of (three as shown in the figure) second ground contacts 202 are disposed on the second ground area B.
In the present embodiment, the carrier structure 20 is a circuit structure with a core layer or a circuit structure without a core layer (refer to the circuit layer 100 in fig. 1), and has a plurality of circuit layers (for example, a core substrate, a coreless substrate or a fan-out (fan out) redistribution layer (RDL), and the circuit layers include the first ground contacts 201, the circuit 200 and the second ground contacts 202 on the surface 20a of the carrier structure 20.
In addition, the material of the interlayer isolation circuit layer of the carrier structure 20 is a dielectric material such as Polyoxadiazole (PBO), Polyimide (PI), Prepreg (PP), and the like. It should be understood that the supporting structure 20 can also be other chip supporting components, such as an organic board, a wafer (wafer), or other carrier boards with metal wires (routing), and is not limited to the above.
The distribution area of the first ground contact region a (the area of the ㄩ shape surrounded by the imaginary line in fig. 2B) is larger than the distribution area of the second ground contact region B (the area of the rectangle surrounded by the imaginary line in fig. 2B). It should be understood that the distribution area of the first grounding segment A can also be equal to the distribution area of the second grounding segment B.
In addition, the circuit 200 includes a conductive trace 200a, and a signal contact 200b and an electrical terminal 200c respectively located at two ends of the conductive trace 200 a.
The electronic component 24 is disposed on the supporting structure 20 and has a plurality (three as shown) of pads 240 for electrically connecting the first and/or second ground contacts 201,202 and a plurality (three as shown) of electrode pads 241 for electrically connecting the circuit 200.
In the present embodiment, the electronic component 24 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, and an inductor, or a combination thereof.
Furthermore, the bonding pad 240 is a ground pad of the electronic device 24, and the electrode pad 241 is a signal pad of the electronic device 24.
In addition, the electrode pad 241 of the electronic component 24 is electrically connected to the signal contacts 200b through a plurality of third conductive elements 23, wherein the third conductive elements 23 are bonding wires.
In addition, as shown in fig. 2C, the pad 240, the first ground contact 201 and the second ground contact 202 are arranged on the same straight line (as indicated by a dashed line C in fig. 2C), and the signal contact 200b and the electrode pad 241 are located on the same straight line (as indicated by a dashed line D in fig. 2C).
The first conductive element 21 is a bonding wire, which contacts and electrically connects the bonding pad 240 and the first ground contact 201.
The second conductive element 22 is a bonding wire, which contacts and electrically connects the first ground contact 201 and the second ground contact 202.
In the present embodiment, the length r of the first conductive element 21 and the length t of the second conductive element 22 are smaller than the length L of the third conductive element 23.
In another embodiment, as shown in fig. 3, the bonding pad 240 of the electronic component 24 can also be directly electrically connected to the second ground contact 202 through the fourth conductive element 54, such as a bonding wire, without jumping through the first ground contact 201; alternatively, as shown in fig. 3, the pad 240 of the electronic component 24 can be electrically connected to the first ground contact 201 only through the first conductive element 51, such as a bonding wire, and is no longer jumped to the second ground contact 202.
The encapsulation layer 25 is formed on the surface 20a of the carrier structure 20 to encapsulate the electronic element 24, the first conductive element 21, the second conductive element 22 and the third conductive element 23.
In the present embodiment, the package layer 25 is an insulating material, such as Polyimide (PI), dry film (dry film), epoxy resin (epoxy), or molding compound (molding compound), and may be formed on the surface 20a of the supporting structure 20 by pressing or molding. However, the material and the manufacturing method of the encapsulating layer 25 are not limited to the above.
Therefore, the electronic package 2 of the present invention defines the first grounding area a and the second grounding area B through the carrying structure 20, so that the electronic component 24 can be selectively electrically connected to the first and/or second grounding contacts 201,202, and compared with the prior art, when the functions of the electronic component 24 are increased and the current passing through the electronic component 24 is increased, the electronic component 24 can be electrically connected to the first and second grounding contacts 201,202 to meet the requirement of the grounding potential of the electronic component 24.
Furthermore, when the electronic component 24 has a small function, the electronic component 24 can be electrically connected to only the first ground contact 201 (or the second ground contact 202) to meet the requirement of the electronic component 24 with a small ground potential.
Fig. 4A and 4B are schematic views of an electronic package 3 according to still another embodiment of the invention. The difference between the present embodiment and the previous embodiments is only the wiring of the carrying structure 20, and other components are substantially the same, so only the differences will be described below, and the description of the same parts will be omitted.
As shown in fig. 4A and 4B, the carrying structure 20 forms a signal line 300 between the first ground area a and the second ground area B.
In the embodiment, the signal line 300 is electrically connected to the circuit 200 through the circuit layer in the carrying structure 20, so that the electronic component 24 is electrically connected to the signal contact 200b through wire bonding to the signal line 300, thereby improving the flexibility of circuit layout.
In summary, the electronic package of the present invention defines the first grounding area and the second grounding area through the supporting structure, so that the electronic component can be selectively electrically connected to the first and/or second grounding contacts according to the functional specification thereof, so as to satisfy the requirement of the electronic component for a larger or smaller grounding potential, thereby improving the practicability of the electronic package.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications to the above would be obvious to those of ordinary skill in the art, but would not bring the invention so modified beyond the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (13)
1. An electronic package, characterized in that the electronic package comprises:
a carrier structure, which defines a first ground area and a second ground area, and has a circuit layer and a signal line, wherein the first ground area is provided with at least one first ground contact, and the second ground area is provided with at least one second ground contact, and wherein the signal line is electrically connected to the second ground area through the circuit layer, and is formed between the first ground area and the second ground area but not located in the first ground area and the second ground area; and
and the electronic element is arranged on the bearing structure and is electrically connected with the first grounding contact and/or the second grounding contact, and the electronic element is positioned in the first grounding area, so that part of the first grounding area is positioned between the second grounding area and the electronic element.
2. The electronic package of claim 1, wherein the first ground region has a distribution area greater than or equal to a distribution area of the second ground region.
3. The electronic package of claim 1, wherein the electronic component has a pad for electrically connecting the pad to the first ground contact through a first conductive element.
4. The electronic package of claim 3, wherein the first conductive element is a wire bond.
5. The electronic package of claim 3, wherein the first ground contact is electrically connected to the second ground contact through a second conductive element.
6. The electronic package of claim 5, wherein the second conductive element is a wire bond.
7. The electronic package according to claim 1, wherein the second ground region further comprises at least one signal contact, and the signal contact is electrically connected to the electronic component through a third conductive element.
8. The electronic package of claim 7, wherein the third conductive element is a wire bond.
9. The electronic package according to claim 7, wherein the electronic component has electrode pads for electrically connecting to the third conductive element, and the electrode pads and the signal contacts are arranged in a same line.
10. The electronic package according to claim 1, wherein the electronic component has a pad for electrically connecting to the first ground contact and/or the second ground contact, and the pad is aligned with the first ground contact and the second ground contact.
11. The electronic package of claim 1, further comprising an encapsulation layer formed on the carrier structure and encapsulating the electronic component.
12. The electronic package of claim 1, wherein the electronic component has a pad, and a fourth conductive element electrically connects the pad and the second ground contact.
13. The electronic package of claim 12, wherein the fourth conductive element is a wire bond.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW106131573 | 2017-09-14 | ||
TW106131573A TW201916182A (en) | 2017-09-14 | 2017-09-14 | Electronic package |
Publications (2)
Publication Number | Publication Date |
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CN109509728A CN109509728A (en) | 2019-03-22 |
CN109509728B true CN109509728B (en) | 2021-05-04 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201711062669.3A Active CN109509728B (en) | 2017-09-14 | 2017-11-02 | Electronic package |
Country Status (2)
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CN (1) | CN109509728B (en) |
TW (1) | TW201916182A (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1650425A (en) * | 2002-04-30 | 2005-08-03 | 株式会社瑞萨科技 | Semiconductor device and electronic device |
JP2006140202A (en) * | 2004-11-10 | 2006-06-01 | Matsushita Electric Ind Co Ltd | Semiconductor device |
TW200830484A (en) * | 2007-01-04 | 2008-07-16 | Chipmos Technologies Bermuda | Chip package structure |
CN101587868A (en) * | 2008-05-19 | 2009-11-25 | 联发科技股份有限公司 | Qfn semiconductor package and fabrication method thereof |
CN101656238A (en) * | 2008-08-21 | 2010-02-24 | 日月光半导体制造股份有限公司 | Advanced quad flat non-leaded package structure and manufacturing method thereof |
CN104064530A (en) * | 2013-03-21 | 2014-09-24 | 矽品精密工业股份有限公司 | Semiconductor Package And Fabrication Method Thereof |
CN104617000A (en) * | 2013-11-01 | 2015-05-13 | 爱思开海力士有限公司 | Semiconductor package and method for fabricating the same |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014229679A (en) * | 2013-05-21 | 2014-12-08 | 株式会社リコー | Semiconductor device |
JP2016171157A (en) * | 2015-03-12 | 2016-09-23 | 株式会社東芝 | High frequency semiconductor package |
-
2017
- 2017-09-14 TW TW106131573A patent/TW201916182A/en unknown
- 2017-11-02 CN CN201711062669.3A patent/CN109509728B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1650425A (en) * | 2002-04-30 | 2005-08-03 | 株式会社瑞萨科技 | Semiconductor device and electronic device |
JP2006140202A (en) * | 2004-11-10 | 2006-06-01 | Matsushita Electric Ind Co Ltd | Semiconductor device |
TW200830484A (en) * | 2007-01-04 | 2008-07-16 | Chipmos Technologies Bermuda | Chip package structure |
CN101587868A (en) * | 2008-05-19 | 2009-11-25 | 联发科技股份有限公司 | Qfn semiconductor package and fabrication method thereof |
CN101656238A (en) * | 2008-08-21 | 2010-02-24 | 日月光半导体制造股份有限公司 | Advanced quad flat non-leaded package structure and manufacturing method thereof |
CN104064530A (en) * | 2013-03-21 | 2014-09-24 | 矽品精密工业股份有限公司 | Semiconductor Package And Fabrication Method Thereof |
CN104617000A (en) * | 2013-11-01 | 2015-05-13 | 爱思开海力士有限公司 | Semiconductor package and method for fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
CN109509728A (en) | 2019-03-22 |
TW201916182A (en) | 2019-04-16 |
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