CN109494254A - 改进栅控型功率器件安全工作区性能的自对准工艺 - Google Patents

改进栅控型功率器件安全工作区性能的自对准工艺 Download PDF

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CN109494254A
CN109494254A CN201811201838.1A CN201811201838A CN109494254A CN 109494254 A CN109494254 A CN 109494254A CN 201811201838 A CN201811201838 A CN 201811201838A CN 109494254 A CN109494254 A CN 109494254A
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刘剑
郑泽人
龚大卫
王玉林
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Yangzhou Guoyang Electronic Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

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Abstract

本发明公开了一种改进栅控型功率器件安全工作区性能的自对准工艺,在进行重掺杂P型注入之前,在栅极端部向发射极接触孔的方向形成衬垫结构,然后以该衬垫结构作为阻挡进行重掺杂P型注入,重掺杂P型注入之后,去除衬垫结构。本发明能够通过调节氮化层沉积的时间、气体流量和压力等工艺参数来调节衬垫结构的宽度,从而能够将重掺杂P型区和栅极之间距离缩短至1um之内,从而能够大幅提高栅控型功率器件的安全工作区性能;本发明通过衬垫结构进行阻挡,不再需要光刻胶阻挡就能实现重掺杂P型注入的自对准,从根本上消除了发射极接触孔与栅极两层之间的光刻工艺对位存在的偏差对器件的影响;本发明工艺简单,有利于器件性能一致性的提高。

Description

改进栅控型功率器件安全工作区性能的自对准工艺
技术领域
本发明涉及栅控型功率器件,特别是涉及改进栅控型功率器件安全工作区性能的自对准工艺。
背景技术
栅控型功率器件(如功率MOSFET和IGBT)是现代通用的电力半导体器件,主要应用于新能源、机车牵引、智能电网、高压变频器等领域。通过电力半导体器件对电能进行变换及控制,节能效果可达10%-40%。在全球气候变暖的背景下,栅控型功率器件应用技术是被公认的实现全球能效和二氧化碳减排目标的最佳综合性方法之一。
现有技术中的栅控型功率器件在加工过程中,空穴电流流经重掺杂N型区下方,被发射极吸收。由于发射极和重掺杂N型区始终处于零电位,因此重掺杂N型区下方的P型区(P型区包括P型井和重掺杂P型区)会存在掺杂电阻,结合空穴电流,会导致重掺杂N型区与P型区之间存在电位差。当空穴电流增加时,特别是器件关断时,该电位差可能会大于0.7V,导致P/N节开启,器件闩锁,从而热击穿,引起器件失效。因此,现有技术对重掺杂P型区进行了改进,常规手段是通过发射极接触孔进行硼注入工艺。但是,由于发射极接触孔与栅极两层之间的光刻工艺对位存在偏差,为了确保重掺杂P型区不会影响器件的其他电学性能,通常重掺杂P型区和栅极之间必须保持较大的间距。为了改善器件的安全工作区性能,通常需要加强重掺杂P型区的掺杂浓度,但是由于重掺杂P型区和栅极之间间距较大,随着器件电流能力需求的增大,加强重掺杂P型区掺杂浓度的难度也越来越大。因此,如何缩小重掺杂P型区和栅极之间的间距则是现有技术中存在的难题。
发明内容
发明目的:本发明的目的是提供一种改进栅控型功率器件安全工作区性能的自对准工艺,能够通过控制衬垫结构的宽度来控制重掺杂P型区和栅极之间的间距,从而缩小重掺杂P型区和栅极之间的间距。
技术方案:本发明所述的改进栅控型功率器件安全工作区性能的自对准工艺,在进行重掺杂P型注入之前,在栅极端部向发射极接触孔的方向形成衬垫结构,然后以该衬垫结构作为阻挡进行重掺杂P型注入,重掺杂P型注入之后,去除衬垫结构。
进一步,所述重掺杂P型注入之后,通过刻蚀的方式去除衬垫结构。
进一步,所述刻蚀的方式采用热磷酸湿法刻蚀和氢氟酸湿法刻蚀。
进一步,所述形成衬垫结构之前,进行以下操作:先进行栅极的沉积和刻蚀,然后进行氧化层、氮化层的沉积。
进一步,所述衬垫结构通过各向异性刻蚀形成。
有益效果:本发明公开了一种改进栅控型功率器件安全工作区性能的自对准工艺,与现有技术相比,具有如下的有益效果:
1)本发明能够通过调节氮化层沉积的时间、气体流量和压力等工艺参数来调节衬垫结构的宽度,从而能够将重掺杂P型区和栅极之间距离缩短至1um之内,远小于发射极接触孔和栅极之间的1.5um~2.0um的间距,从而能够大幅提高栅控型功率器件的安全工作区性能;
2)本发明通过衬垫结构进行阻挡,不再需要光刻胶阻挡就能实现重掺杂P型注入的自对准,从根本上消除了发射极接触孔与栅极两层之间的光刻工艺对位存在的偏差对器件的影响;
3)本发明工艺简单,有利于器件性能一致性的提高。
附图说明
图1为现有技术中栅控型功率器件的结构示意图;
图2为本发明具体实施方式中衬垫结构的示意图;
图3为本发明具体实施方式中栅控型功率器件的结构示意图;
图4为本发明具体实施方式中完成了栅极沉积和刻蚀步骤之后器件的截面图;
图5为本发明具体实施方式中作为衬垫结构膜层的氧化层和氮化层沉积的截面图;
图6为本发明具体实施方式中各向异性刻蚀形成衬垫结构之后的截面图;
图7为本发明具体实施方式中利用衬垫结构作为阻挡层,实现重掺杂P型注入的示意图。
具体实施方式
现有技术中栅控型功率器件的结构如图1所示,包括N型衬底41、栅极11、发射极接触孔21、收集极31、P型井51、重掺杂N型区61以及重掺杂P型区71。重掺杂P型区71与栅极11之间的区域为区域81。
现有技术中的栅控型功率器件在加工过程中,空穴电流流经重掺杂N型区61下方,被发射极吸收。由于发射极和重掺杂N型区61始终处于零电位,因此重掺杂N型区61下方的P型区(P型区包括P型井51和重掺杂P型区71)会存在掺杂电阻,从而导致重掺杂N型区61与P型区之间存在电位差。当空穴电流增加时,特别是器件关断时,该电位差可能会大于0.7V,导致P/N节开启,器件闩锁,从而热击穿,引起器件失效。因此,现有技术对重掺杂P型区71进行了改进,常规手段是通过发射极接触孔21进行硼注入工艺。但是,由于发射极接触孔21与栅极11两层之间的光刻工艺对位存在偏差,为了确保重掺杂P型区71不会影响器件的其他电学性能,通常重掺杂P型区71和栅极11之间必须保持较大的间距,也即区域81的宽度必须较大。为了改善器件的安全工作区性能,通常需要加强重掺杂P型区71的掺杂浓度,但是由于重掺杂P型区71和栅极11之间间距较大,随着器件电流能力需求的增大,加强重掺杂P型区71掺杂浓度的难度也越来越大。因此,如何缩小重掺杂P型区71和栅极11之间的间距则是现有技术中存在的难题。
为了解决现有技术中存在的难题,本具体实施方式公开了一种改进栅控型功率器件安全工作区性能的自对准工艺,包括以下步骤:
1)进行栅极的沉积和刻蚀,形成的结构如图4所示,包括栅极12、栅氧化层121和硅衬底102;
2)进行氧化层、氮化层的沉积,形成的结构如图5所示,包括栅极12、栅氧化层121、衬垫结构氧化层921、衬垫结构氮化层922和硅衬底102;
3)在栅极12端部向发射极接触孔22的方向通过各向异性刻蚀形成衬垫结构92,如图6所示,图6中示出了衬垫结构氧化层921和衬垫结构氮化层922;衬垫结构92如图2所示;
4)以衬垫结构92作为阻挡进行重掺杂P型注入,如图7所示;
5)重掺杂P型注入之后,通过热磷酸湿法刻蚀和氢氟酸湿法刻蚀的方式去除衬垫结构92,然后进行常规的后续工艺。
图3为得到的栅控型功率器件的结构示意图,包括N型衬底42、栅极12、发射极接触孔22、收集极32、P型井52、重掺杂N型区62以及重掺杂P型区72。其中,重掺杂P型区72与栅极12之间的区域为区域82。可见,区域82比现有技术得到的区域81的宽度要宽。图1-图3是示意图,只画出了一半的结构。

Claims (5)

1.改进栅控型功率器件安全工作区性能的自对准工艺,其特征在于:在进行重掺杂P型注入之前,在栅极端部向发射极接触孔的方向形成衬垫结构,然后以该衬垫结构作为阻挡进行重掺杂P型注入,重掺杂P型注入之后,去除衬垫结构。
2.根据权利要求1所述的改进栅控型功率器件安全工作区性能的自对准工艺,其特征在于:所述重掺杂P型注入之后,通过刻蚀的方式去除衬垫结构。
3.根据权利要求2所述的改进栅控型功率器件安全工作区性能的自对准工艺,其特征在于:所述刻蚀的方式采用热磷酸湿法刻蚀和氢氟酸湿法刻蚀。
4.根据权利要求1所述的改进栅控型功率器件安全工作区性能的自对准工艺,其特征在于:所述形成衬垫结构之前,进行以下操作:先进行栅极的沉积和刻蚀,然后进行氧化层、氮化层的沉积。
5.根据权利要求1所述的改进栅控型功率器件安全工作区性能的自对准工艺,其特征在于:所述衬垫结构通过各向异性刻蚀形成。
CN201811201838.1A 2018-10-16 2018-10-16 改进栅控型功率器件安全工作区性能的自对准工艺 Pending CN109494254A (zh)

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