CN109411527A - 一种采用降低表面电场技术的n型ldmos - Google Patents
一种采用降低表面电场技术的n型ldmos Download PDFInfo
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Abstract
本发明公开了一种采用降低表面电场技术的N型LDMOS，包括p型衬底层，所述p型衬底层上端面为深N阱层，所述深N阱层内部包含深p阱层、n阱层、p型掺杂区、第一漂流环和第二漂流环，所述深p阱层包含p阱层，p+掺杂层和第一n+掺杂层，所述n阱层内包括第二n+掺杂层，所述第一n+掺杂层和p+掺杂层构成器件源极，所述第二n+掺杂层构成器件的漏极，所述深n阱上端面由下至上分别为二氧化硅隔离层和多晶硅栅极与多晶硅场板层；器件直接采用表面二氧化硅层隔离。本发明通过降低表面电场从而使击穿点从表面转移到体内击穿，提高击穿电压。采用场板技术和漂流环技术，达到分散电场的作用，弱化电场，从而达到提高击穿电压和降低导通电阻的效果。
Description
技术领域
本发明涉及半导体功率器件技术领域，具体涉及一种采用降低表面电场技术的N型LDMOS。
背景技术
传统的高压横向扩散金属氧化物半导体场效应管(LDMOS)的表面电场强度非常大，从而导致击穿电压非常容易在表面击穿，而且击穿电压也非常低，达不到高击穿电压的效果，为我们的研究带来了困难，后来有人提出了降低表面电场技术(RESURF)对于LDMOS的发展有了革命性的改变，使LDMOS击穿电压得到了非常大的提升。刚开始单型降低表面电场技术(SINGLE RESURF)，虽然提高了击穿电压，但是却带来了负面的影响，使得导通电阻增大。为了解决此问题本发明采用双型降低表面电场技术(DOUBLE RESURF),此项技术利用增大漂移区耗尽层宽度，在提高击穿电压的同时，降低了导通电阻。
虽然RESURF技术在一定程度上提高了击穿电压，但是离我们的目标还是有一定的距离，所以此时采用场板技术，场板技术起到了分散电场的作用，使得电场线密度在曲率比较大的地方降低，不容易在曲率大的地方提前击穿，使漏端的耐压程度提高，提高击穿电压。
此外随着半导体行业的发展，对于器件的性能提出了新的挑战，为了满足现实生活的发展需求，提出了漂流环技术，此项技术与DOUBLE RESURF相呼应扩大了漂移区的耗尽层宽度，使得漂移区全部耗尽，提高击穿电压，降低比导通电阻，提高了器件的工作效率。
发明内容
为了解决现有技术中存在的问题，本发明提供一种采用降低表面电场技术的N型LDMOS，解决现有技术中N型LDMOS的耐压值低、比导通电阻高的问题。
本发明的技术方案是：一种采用降低表面电场技术的N型LDMOS，包括p型衬底层，所述p型衬底层上端面为深N阱层，所述深N阱层内部包含深p阱层、n阱层、p型掺杂区、第一漂流环和第二漂流环，所述深p阱层包含p阱层，p+掺杂层和第一n+掺杂层，所述n阱层内包括第二n+掺杂层，所述第一n+掺杂层和p+掺杂层构成器件源极，所述第二n+掺杂层构成器件的漏极，所述深n阱上端面由下至上分别为二氧化硅隔离层和多晶硅栅极与多晶硅场板层；器件直接采用表面二氧化硅层隔离。
所述p型衬底层是在单晶硅中通过注入硼离子所形成的。
所述深n阱层采用离子注入，注入大量的磷离子形成。
所述深p阱层和p型掺杂区是通过注入不同浓度和能量的硼离子实现的，通过注入离子的能量不同来调节注入所需的深度。
本发明的有益效果为：
1、本发明提出一种采用降低表面电场技术的双阱N型LDMOS，通过降低表面电场从而使击穿点从表面转移到体内击穿，提高击穿电压。
2、本发明采用场板技术和漂流环技术，达到分散电场的作用，弱化电场，从而达到提高击穿电压和降低导通电阻的效果。
3、本发明利用双型降低表面电场技术(DOUBLE RESURF LDMOS)，此技术使漂移区耗尽区变的更宽，降低表面电场，从而使漏区耐压达到最大，提高击穿电压的同时降低导通电阻。可以在不增加工艺制造难度的基础上提高器件性能，达到降低制造成本的目的。
附图说明
图1本发明一种采用降低表面电场技术的N型LDMOS结构示意图；
图中：1.p型衬底层；2.深n阱层；3.深p阱层；4.p型掺杂区；5.第一漂流环；6.第二漂流环；7.n阱层；8.p阱层；9.第一n+参杂层；10.p+参杂层；11.第二n+参杂层；12.第一二氧化硅隔离层；13.多晶硅场板；14.多晶硅栅极；15.第二二氧化硅隔离层。
具体实施方式
下面结合附图对本发明作进一步详细说明。
如图1所示本发明一种采用降低表面电场技术的N型LDMOS，包括p型衬底层1，所述p型沉底层1是在单晶硅中通过注入硼离子所形成的，p型衬底层1上端面为深n阱层2，所述深n阱层2采用离子注入，注入大量的磷离子形成，所述深n阱层2内包含深p阱层3、p型掺杂区4、第一漂流环5、第二漂流环6和n阱层7，所述深p阱层3和p型掺杂区4是通过注入不同浓度和能量的硼离子实现的，通过注入离子的能量不同来调节注入所需的深度，所述深p阱层3包括p阱层8，所述p阱层8的作用是为了降低寄生电阻，从而使导通电阻降低，所述p阱层8包含第一n+参杂层9和p+参杂层10，所述第一n+参杂层9和p+参杂层10是为了在源极形成欧姆接触而设计的，所述n阱层7上端面是第二n+参杂层11，所述第二n+参杂层11是为在漏极形成欧姆接触而设计的，所述p型参杂区4上端面铺有第一二氧化硅隔离层12，所述第一二氧化硅隔离层12的作用是为了隔离栅极与漏极，防止栅极与漏极短路，所述第一二氧化硅隔离层12上端面平铺多晶硅场板13，所述平铺的多晶硅场板13是为了分散曲率大处的电场，防止预击穿，从而提高击穿电压，所述多晶硅场板13左边是多晶硅栅极14，所述第一n+参杂层9和p+参杂层10左边是第二二氧化硅隔离层15，其作用是隔离源极与漏极，防止源极与漏极短路。
本实例所涉及的一种采用降低表面电场技术的N型LDMOS，栅极击穿电压达到至少600V，单位长度比导通小于50mΩ/mm，单位面积栅电容约1.7fF/um2，阈值电压不高于3V，工作温度为-40℃～125℃。
本实例在p型衬底生(上)实现，但在应用发明过程中，可以在n型衬底体系上实现相似结构，尽管已示出并描述了根据发明的基本原理和精神的情况下，可以对这些实例作(做)出改变，本发明的范围由权力要求书及其等同物限定。
Claims (4)
1.一种采用降低表面电场技术的N型LDMOS，其特征在于，包括p型衬底层，所述p型衬底层上端面为深N阱层，所述深N阱层内部包含深p阱层、n阱层、p型掺杂区、第一漂流环和第二漂流环，所述深p阱层包含p阱层，p+掺杂层和第一n+掺杂层，所述n阱层内包括第二n+掺杂层，所述第一n+掺杂层和p+掺杂层构成器件源极，所述第二n+掺杂层构成器件的漏极，所述深n阱上端面由下至上分别为二氧化硅隔离层和多晶硅栅极与多晶硅场板层；器件直接采用表面二氧化硅层隔离。
2.根据权利要求1所述采用降低表面电场技术的N型LDMOS，其特征在于，所述p型衬底层是在单晶硅中通过注入硼离子所形成的。
3.根据权利要求1所述采用降低表面电场技术的N型LDMOS，其特征在于，所述深n阱层采用离子注入，注入大量的磷离子形成。
4.根据权利要求1所述采用降低表面电场技术的N型LDMOS，其特征在于，所述深p阱层和p型掺杂区是通过注入不同浓度和能量的硼离子实现的，通过注入离子的能量不同来调节注入所需的深度。
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| CN112349764A (zh) * | 2019-08-08 | 2021-02-09 | 天津大学 | 一种具有场限环结构的resurf ldmos器件 |
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| CN112349764A (zh) * | 2019-08-08 | 2021-02-09 | 天津大学 | 一种具有场限环结构的resurf ldmos器件 |
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Application publication date: 20190301 |