CN109390345A - The method for manufacturing 3D memory device - Google Patents
The method for manufacturing 3D memory device Download PDFInfo
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- CN109390345A CN109390345A CN201811130063.3A CN201811130063A CN109390345A CN 109390345 A CN109390345 A CN 109390345A CN 201811130063 A CN201811130063 A CN 201811130063A CN 109390345 A CN109390345 A CN 109390345A
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- laminate structure
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
Disclose a kind of method for manufacturing 3D memory device.Manufacture 3D memory device method include: it is rectangular at former insulating laminate structure on substrate, former insulating laminate structure includes the multiple sacrificial layers and multiple interlayer insulating films being alternately stacked；Form multiple channel columns through the former insulating laminate structure；Form separation layer in the former insulating laminate structure, separation layer is through the former insulating laminate structure and annular in shape, so that constituting insulating laminate structure by the circular former insulating laminate structure of the separation layer；Metal layer is used to replace the sacrificial layer in former insulating laminate structure on the outside of the separation layer to form rhythmic structure of the fence；And form the conductive channel for running through the insulating laminate structure, wherein at least part of the lateral wall of the separation layer is smooth surface.The 3D memory device uses the separation layer of smooth surface, so that avoiding forming hole in separation layer leads to short circuit between grid conductor and conductive channel, the yield and reliability of 3D memory device can be improved.
Description
Technical field
The present invention relates to memory technology fields, more particularly, to the method for manufacture 3D memory device.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor realizes the interconnection of memory cell string using the conductive channel through laminated construction.3D memory device is if necessary in realization
The connection of layer structure and understructure, it is necessary to design an insulating regions, for insulating regions by separation layer around forming, conduction is logical
Road is located in the insulating regions, and via being isolated between separation layer and grid conductor and channel layer.It is formed in separation layer
Hole will will affect the yield and reliability of 3D memory device.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of methods of improved manufacture 3D memory device, wherein every
Absciss layer separates rhythmic structure of the fence and insulating laminate structure, and at least part of the lateral wall of separation layer is smooth surface, with
Improve the yield and reliability of 3D memory device.
According to an aspect of the present invention, provide it is a kind of manufacture 3D memory device method, comprising: on substrate it is rectangular at
Former insulating laminate structure, the original insulating laminate structure includes the multiple sacrificial layers and multiple interlayer insulating films being alternately stacked；Shape
At multiple channel columns through the former insulating laminate structure；Form separation layer in the former insulating laminate structure, it is described every
Absciss layer is through the former insulating laminate structure and annular in shape, so that the former insulating laminate structure structure circular by the separation layer
At insulating laminate structure；Metal layer is used to replace the sacrificial layer in former insulating laminate structure on the outside of the separation layer to form grid
Laminated construction；And form the conductive channel for running through the insulating laminate structure, wherein the lateral wall of the separation layer is at least
A part is smooth surface.
Preferably, the separation layer is being to include selected from annulus, elliptical ring and race perpendicular to the cross section on stacking direction
Any one of road ring.
Preferably, the material of the separation layer includes megohmite insulant.
Preferably, the separation layer has uniform thickness along circumferential direction.
Preferably, the step of being replaced using metal layer includes: by sacrificial in the etching removal former insulating laminate structure
Domestic animal layer is to form cavity；And using the separation layer as deposition barrier layer, deposited metal layer fills the cavity to be formed
The grid conductor.
Preferably, the rhythmic structure of the fence includes core space and the stepped region for surrounding the core space；The method is also wrapped
It includes: forming multiple false channel columns of at least part lateral wall of the neighbouring separation layer, the vacation channel column passes through the grid
The core space of laminated construction.
Preferably, at least some of the multiple false channel column false the distance between channel column and the separation layer compares institute
It is smaller to state at least some false the distance between channel columns and the channel column.
Preferably, multiple described in multiple metal layers in the rhythmic structure of the fence and the insulating laminate structure
Sacrificial layer corresponds, and each metal layer is located on the same floor with the corresponding sacrificial layer.
Preferably, the conductive channel includes the array of multiple conductive column compositions.
Preferably, further includes: form cmos circuit in the semiconductor substrate, wherein the conductive channel is from described
Semiconductor substrate upwardly extends, and reaches top surface through the insulating laminate structure, the conductive channel provides the CMOS
Being electrically connected between circuit and external circuit.
The method of manufacture 3D memory device according to an embodiment of the present invention, the 3D memory device use the isolation of smooth surface
Layer, etching can prevent subsequent metal layer from filling between caused conductive channel and metal layer to avoid hole is formed in separation layer
The problem of short circuit, so as to improve the yield and reliability of 3D memory device.
In the prior art, 3D memory device often uses a kind of separation layer of rectangle, and rectangle separation layer surrounds and forms square
The insulating regions of shape, four angles of the separation layer of the insulating regions of this rectangle hole easy to form during etching, lead
Subsequent metal layer is caused to be filled into built-in electrical insulation region.Compared with prior art, the 3D memory device of this embodiment of the present invention is adopted
With the separation layer of smooth surface, will not occur four angles of rectangle separation layer because of etch stop or undercut in etching process
The problem of middle formation hole, so as to improve the yield and reliability of 3D memory device.
Further, in the 3D memory device, due to the separation layer using smooth surface, the thickness of separation layer is
Uniformly, be conducive to the filling of subsequent insulating layer, to improve the yield and reliability of 3D memory device.
Further, in the 3D memory device, using the separation layer of annular, the area that annular design accounts for is set less than rectangle
The area accounted for is counted, so the word line resistance of annular design is smaller, to improve the performance of 3D memory device.
It further, further include the multiple false channel columns for passing through laminated construction around separation layer in the 3D memory device,
And at least part false the distance between channel and separation layer is smaller than with the distance between channel column.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 shows the perspective views of 3D memory device according to an embodiment of the present invention.
Fig. 3 a to 3g shows the sectional view in each stage of the 3D memory device manufacturing method of the embodiment of the present invention.
The sectional view of the 3D memory device of the prior art and the embodiment of the present invention is shown respectively in Fig. 4 a and 4b.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
The inventors discovered that the cross sectional shape of separation layer has apparent shadow to yield and reliability in 3D memory device
It rings.In design, separation layer with by the conductive channel and peripheral region in insulating regions grid conductor and channel column be separated by
From.However, 3D memory device in the prior art often uses cross sectional shape for the separation layer of rectangle, four of this separation layer
Angle hole easy to form during etching, causes subsequent metal layer to be filled into built-in electrical insulation region.And in insulating regions
Conductive channel and enter the metal layers of insulating regions and link together and cause short circuit, dropped so as to cause the yield of 3D memory device
Low and less reliable.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line (Bit-Line, BL), and second end is connected to
Source electrode line (Source Line, SL).Memory cell string 100 includes the multiple crystalline substances being connected in series between the first end and a second end
Body pipe, comprising: first choice transistor Q1, memory transistor M1 to M4 and the second selection transistor Q2.First choice crystal
The grid of pipe Q1 is connected to string selection line (Selection Gate for Drain, SGD), the grid of the second selection transistor Q2
It is connected to the ground selection line (Selection Gate for Source, SGS).The grid of memory transistor M1 to M4 is separately connected
To the respective word of wordline (Word-Line) WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include gate conductor layer 109b, storage
Transistor M1 to M4 respectively includes gate conductor layer 109a.Crystalline substance in gate conductor layer 109a and 109b and memory cell string 100
The stacking order of body pipe is consistent, is separated each other using interlayer insulating film between adjacent gate conductor layer, to form gate stack
Structure.Further, memory cell string 100 includes channel column 110.Channel column 110 is adjacent with rhythmic structure of the fence or runs through grid
Laminated construction.Tunneling medium layer is accompanied between the middle section of channel column 110, gate conductor layer 109a and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110, grid
Gate dielectric layer 114 is accompanied between pole conductor layer 109b and channel layer 111, to form selection transistor Q1 and Q2.
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and gate dielectric layer 114
It is made of respectively oxide, such as silica, charge storage layer 113 is by the insulating layer group comprising quantum dot or nanocrystal
At, such as the silicon nitride of the particle comprising metal or semiconductor, gate conductor layer 109a and 109b be made of metal, such as
Tungsten.Channel layer 111 is used to provide control selection transistor and control the channel region of transistor, the doping type of channel layer 111 and choosing
It is identical with the control type of transistor to select transistor.For example, selection transistor and control transistor for N-type, channel layer 111
It can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In channel column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the implementation of substitution
Example in, can use step independent of one another, be respectively formed selection transistor Q1 and Q2 semiconductor layer and gate dielectric layer and
The semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In channel column 110, the semiconductor layer of selection transistor Q1 and Q2
It is electrically connected to each other with the semiconductor layer of memory transistor M1 to M4.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling effect
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line SGS is biased to greatly
About zero volts, so that the selection transistor Q2 for corresponding to ground selection line SGS forms hole, string selection line SGD is biased to high electricity
VDD is pressed, so that corresponding to the selection transistor Q1 conducting of string selection line SGD.Further, bit line BL2 is grounded, and wordline WL2 is inclined
It is placed in program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2
Word line voltage be higher than tunneling voltage, therefore, the electronics of the channel region of memory transistor M2 is arrived via tunneling medium layer 112
Up to charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 shows the perspective views of 3D memory device.For the sake of clarity, it is not shown in Fig. 2 each in 3D memory device
A insulating layer.
The 3D memory device shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage unit
String 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that this hair
Bright without being limited thereto, 3D memory device may include any number of memory cell strings, for example, 1024, in each memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
In 3D memory device, memory cell string respectively includes respective channel column 110 and public grid conductor
109.Grid conductor 109 is consistent with the stacking order of transistor in memory cell string 100, between adjacent gate conductor layer that
This is separated using interlayer insulating film, to form rhythmic structure of the fence.Interlayer insulating film is being not shown in the figure.
The internal structure of channel column 110 is as shown in Figure 1 b, is no longer described in detail herein.In the centre of channel column 110
Channel layer 111, tunneling medium layer 112, charge storage layer 113 and grid inside part, grid conductor 109 and channel column 110 are situated between
Matter layer 114 together, forms memory transistor M1 to M4.At the both ends of channel column 110, inside grid conductor 109 and channel column 110
Channel layer 111 and gate dielectric layer 114 together, formed selection transistor Q1 and Q2.
Channel column 110 runs through rhythmic structure of the fence, and is arranged in array, the first end of multiple channel columns 110 of same row
It is commonly connected to same bit line, second end is commonly connected to substrate 101, and second end forms common source via substrate 100 and connects.
In this embodiment, 3D memory device includes the insulating regions surrounded by the inner sidewall of annular isolation layer 121, at this
Different from rhythmic structure of the fence in region, which still maintains insulating laminate structure, wherein multiple sacrificial layers and multiple layers
Between insulating layer be alternately stacked.In insulating regions, conductive channel 123 is, for example, the array of multiple conductive columns composition, respectively from the
The semiconductor substrate 101 of one array architecture upwardly extends, and through the insulating laminate structure of the first array structure, reaches the first array
The top of structure.
Further, for example including cmos circuit in the substrate semiconductor substrate 101 of 3D memory device.It is logical using conduction
Road 123 provides being electrically connected between cmos circuit and external circuit.
Fig. 3 a to 3g shows the sectional view in each stage of the 3D memory device manufacturing method of the embodiment of the present invention.Described section
Face figure is intercepted along the AA line in Fig. 2, and the slice location of sectional view passes through isolated area 121.
This method starts from the first array structure L01 that insulating laminate structure is formed in semiconductor substrate 101, such as
Shown in Fig. 3 a.
First array structure L01 includes semiconductor substrate 101 and insulating laminate structure thereon.The insulating laminate structure packet
Include the multiple interlayer insulating films 108 and multiple sacrificial layers 122 being alternately stacked.In this embodiment, semiconductor substrate 101 is, for example,
Monocrystalline substrate, interlayer insulating film 108 are for example made of silica, and sacrificial layer 122 is for example made of silicon nitride.Preferred real
It applies in example, interlayer insulating film 108 is, for example, vacuum layer.
As described below, sacrificial layer 122 will be replaced as grid conductor, and grid conductor is further attached to wordline.For shape
At the conductive channel for reaching wordline from grid conductor, multiple sacrificial layers 122 are for example patterned step-like, that is, each sacrificial layer
122 marginal portion provides electrical connection area relative to the sacrificial layer exposure of top.In the patterning step of multiple sacrificial layers 122
Later, insulating laminate structure can be covered using insulating layer.In fig. 3 a by the interlayer insulating film between multiple sacrificial layers 122
108 integrally show with the interlayer insulating film for covering insulating laminate structure.However, the invention is not limited thereto, it can be using multiple only
Vertical deposition step is formed between multiple sacrificial layers 122 and its interlayer insulating film of top.
For the ease of being programmed operation to the storage unit in 3D memory device, formed in semiconductor substrate 101 more
A well region and cmos circuit (not shown) for driving selection transistor and memory transistor.The multiple well region for example wraps
It includes deep N-well 102, the high pressure p-well 103 in deep N-well 102 and the adjacent high pressure N trap 105 of high pressure p-well 103, be located at high pressure
P+ doped region 104 in p-well 103, the N+ doped region 106 in high pressure N trap 105.In this embodiment, high pressure p-well 103 is made
For the public source zone of channel column, high pressure N trap 105 is for the precharge to public source zone, P+ doped region 104 and N+ doped region 106
Respectively as contact zone to reduce contact resistance.Public source zone of the high pressure p-well 103 as multiple channel columns, therefore be located at exhausted
The lower section of edge laminated construction.
Further, corresponding with intermediate region (the core region) of insulating laminate structure in the first array structure L01
In the A01 of first area, the channel column 110 for running through insulating laminate structure is formed, in the stepped area (stair- of insulating laminate structure
Step region) in corresponding second area A02, the false channel column 140 for running through insulating laminate structure is formed, as shown in Figure 3b.
The lower part of channel column 110 includes semiconductor layer 116.Further, channel column 110 includes that half is extended to from upper part
The channel layer 111 of conductor layer 116.As shown, channel column 110 includes being sequentially stacked on ditch in the middle section of channel column 110
Tunneling medium layer 112, charge storage layer 113 and block media layer 114 in channel layer 111, at the both ends of channel column 110, channel
Column 110 includes the block media layer 114 being stacked on channel layer 111 or semiconductor layer 116.The lower end of channel column 110 with partly lead
High pressure p-well 103 in body substrate 101 is in contact.In final 3D memory device, the upper end of channel column 110 is connected with bit line
It connects, to form effective storage unit.The structure of the channel column 110 is, for example, ONOP (oxidenitride oxide-
Polysilicon).
The internal structure of false channel column 140 and channel column 110 can be identical or different, and at least across rhythmic structure of the fence
In at least part grid conductor.In final 3D memory device, false channel column 140 is not connected with bit line, thus
It is provided solely for mechanical support effect, without being used to form selection transistor and memory transistor.Therefore, false channel column 140 does not have
To form effective storage unit.
Further, the ring-shaped groove 120 for running through the first array structure L01 is formed, as shown in Figure 3c.Wherein, annular ditch
The thickness of slot along circumferential direction is uniformly, to be conducive to the uniform filling of subsequent separation layer.It, can when forming ring-shaped groove 120
To use anisotropic etching, for example, by using dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, laser
Ablation.For example, by control etching period, so that the surface for being etched in semiconductor substrate 101 nearby stops.
Further, separation layer 121 is formed in ring-shaped groove 120, as shown in Figure 3d.
Separation layer 121 is upwardly extended from the semiconductor substrate 101 of the first array structure L01, runs through the first array structure L01
Insulating laminate structure reach the first array structure top.Separation layer 121 runs through former insulating laminate structure, and annular in shape, makes
The circular former insulating laminate structure of layer 121 must be isolated and constitute insulating laminate structure.In this embodiment, separation layer 121 is outer
At least part of side wall is smooth surface.Further, in the plan view perpendicular to stacking direction, separation layer 121 is
The inner sidewall of annular, separation layer 121 surrounds insulating laminate structure, forms insulating regions A03, the lateral wall and original of separation layer 121
Insulating laminate structure is adjacent.Further, the annular of separation layer 121 includes any in annulus, elliptical ring and racetrack torus
Kind.In this embodiment, separation layer 121 includes the insulating layer different from the etching characteristic of sacrificial layer 122, and sacrificial layer 122 is for example
It is made of silicon nitride, separation layer 121 is for example made of silica.
Further, grid line gap 151 (referring to fig. 2) is formed in the insulating laminate structure of the first array structure L01, adopted
Use multiple interlayer insulating films 108 and separation layer 121 as etching stopping layer, it is former absolutely by etching removal via grid line gap 151
Sacrificial layer 122 in edge lamination is to form cavity, using separation layer 121 as deposition barrier layer, and using metal layer filling
Cavity is to form grid conductor 109.After forming grid conductor 109, insulating regions A03 made of being surrounded in separation layer 121
Inside still maintains insulating laminate structure, wherein multiple sacrificial layers 122 and multiple interlayer insulating films 108 are alternately stacked.?
Outside insulating regions A03, sacrificial layer 122 is replaced into grid conductor 109, wherein multiple grid conductors 109 and multiple interlayers are exhausted
Edge layer 108 is alternately stacked, so that multiple channel columns 110 and false channel column 140 run through rhythmic structure of the fence, as shown in Figure 3 e.
When forming grid line gap 151, anisotropic etching can be used, is lost for example, by using dry etching, such as ion beam milling
Quarter, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in semiconductor lining
The surface at bottom 101 nearby stops.
In this embodiment, grid conductor 109 is divided into a plurality of grid line by grid line gap 151.For this purpose, grid line gap 151
Through the insulating laminate structure of the first array structure L01.
It is folded using isotropic etching removal insulation using grid line gap 151 as etchant channel when forming cavity
Sacrificial layer 122 in layer structure is to form cavity.Isotropic etching can be using wet etching or the gas phase erosion of selectivity
It carves.Use etching solution as etchant in wet etching, wherein in the etch solution by semiconductor structure submergence.In gas
Mutually use etching gas as etchant in etching, wherein semiconductor structure is exposed in etching gas.
What interlayer insulating film 108 and sacrificial layer 122 in insulating laminate structure were made of silica and silicon nitride respectively
Under situation, in wet etching can using phosphoric acid solution as etchant, in gas phase etching can use C4F8, C4F6,
One of CH2F2 and O2 or a variety of.In an etching step, etchant is full of grid line gap 151.It is sacrificial in insulating laminate structure
The end of domestic animal layer 122 is exposed in the opening in grid line gap 151, and therefore, sacrificial layer 122 touches etchant.Etchant is by grid
The opening of linear slit gap 151 is gradually to the etched inside sacrificial layer 122 of insulating laminate structure.Due to the selectivity of etchant, the erosion
It carves and removes sacrificial layer 122 relative to the interlayer insulating film 108 in insulating laminate structure.
When forming grid conductor 109, using grid line gap 151 as deposit channel, using atomic layer deposition
(ALD), metal layer is filled in grid line gap 151 and cavity.
In this embodiment, metal layer is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, hexafluoro
Change tungsten WF6, the reducing gas of use is, for example, silane SiH4 or diborane B2H6.In the atomic layer deposition the step of, six are utilized
The chemisorption of the reaction product of tungsten fluoride WF6 and silane SiH4 obtains tungsten material and realizes deposition process.
In the first array structure L01, selection transistor and memory transistor are formd.It is with the first array structure L01
Example, in the middle section of channel column 110, channel layer 111, tunneling medium layer 112 inside grid conductor 109 and channel column 110,
Charge storage layer 113 and block media layer 114 together, form memory transistor.At the both ends of channel column 110, grid conductor 109
With inside channel column 110 channel layer 111 (or semiconductor layer 116) and block media layer 114 together, formed selection transistor.
Further, multiple conductive channels 123 are formed in insulating regions A03, and the CMOS electricity in semiconductor substrate is provided
Being electrically connected between road and external circuit, as illustrated in figure 3f.
Inside insulating regions A03, conductive channel 123 is, for example, the array of multiple conductive column compositions, respectively from first gust
The semiconductor substrate 101 of array structure upwardly extends, and through the insulating laminate structure of the first array structure, reaches the first array structure
Top.
In this embodiment, conductive channel 123 is located in insulating regions A03.It in alternate embodiments, can be in grid line
Conductive channel is formed in gap 151, or conductive channel is formed in rhythmic structure of the fence.For example, conductive channel and channel column phase
Neighbour, and conductive column and insulating layer are formed in the access opening similar with channel hole.The conductive channel runs through the first array structure
Rhythmic structure of the fence, and separated between conductive channel and neighbouring grid conductor by insulating layer.
In this embodiment, conductive channel 123 provides being electrically connected between cmos circuit and external circuit.In the reality of substitution
Example is applied, conductive channel can also provide being electrically connected between the public source zone 103 and external circuit of the first array structure L01.?
In the alternative embodiment, conductive channel prolongs upwards from the public source zone 103 in the semiconductor substrate 101 of the first array structure
It stretches, through the rhythmic structure of the fence of the first array structure, reaches the top of the first array structure.
In this embodiment, the conductive column in conductive channel is for example made of Ti/TiN or W, and insulation layers are such as by silica
Composition.
In this embodiment, channel column 110 further includes the insulating layer 115 as core, channel layer 111, tunneling medium layer
112, charge storage layer 113 and block media layer 114 form the laminated construction for surrounding core.In alternate embodiments, channel
Insulating layer 115 can be saved in column 110.
Further, multiple conductive channels are formed on the rhythmic structure of the fence of the first array structure L01, as shown in figure 3g.
Multiple conductive channels in the 3D memory device are respectively included as the conductive column 131 of core and as separation layer
Insulating layer 132, the insulating layer 132 is for conductive column 131 and the conductive material of surrounding to be separated from each other.It is the multiple conductive logical
Road is for example including conductive channel SL1, HV1.Conductive channel SL1 and HV1 respectively with the P+ doped region in the first array structure L01
104 and N+ doped region 106 is in contact, thus provide the first array structure L01 public source zone and high pressure N trap and external circuit it
Between electrical connection.
The sectional view of the 3D memory device of the prior art and the embodiment of the present invention, the sectional view is shown respectively in Fig. 4 a and 4b
It is intercepted along perpendicular to stacking direction.
As shown in fig. 4 a, separation layer 121 is rectangle in the cross sectional shape perpendicular to stacking direction.Forming grid conductor
During 109, it is used as etching stopping layer using multiple interlayer insulating films 108 and separation layer 121, it is logical via grid line gap 151
The sacrificial layer 122 in former insulating laminate outside overetch removal insulating regions A03 is filled out with forming cavity and deposited metal layer
Cavity is filled to form grid conductor 109, and wherein separation layer 121 is as deposition barrier layer, as shown in Figure 3 e.In above process,
End eclipse occurs during etching sacrificial layer 122 and carves (under etch) for four angles of separation layer 121, as a result in separation layer
Hole is formed on 121 side wall, subsequent metal layer is caused to enter built-in electrical insulation region, to will lead to and grid conductor 109
It is shorted between the conductive channel 123 in insulating regions.
As shown in Figure 4 b, 3D memory device provided in an embodiment of the present invention uses the separation layer 121 of smooth surface.Separation layer
121 be annular perpendicular to the cross sectional shape on stacking direction, and eliminates the protrusion shape of corner.Therefore, etched
Cheng Zhong, separation layer 121 are not in etch stopping in advance or undercut to prevent metal layer from entering insulating regions to reach
With the purpose of plain conductor short circuit, the yield and reliability of 3D memory device are improved.
Further, in 3D memory device provided in an embodiment of the present invention, due to the separation layer using smooth surface
121, therefore the thickness of separation layer 121 is uniformly, to be conducive to the uniform filling of subsequent insulating layer, to improve 3D memory device
Yield and reliability.
Further, in 3D memory device provided in an embodiment of the present invention, using the separation layer 121 of smooth surface, ring
The area that shape design accounts for is less than the area that rectangular design accounts for, so the word line resistance of annular design is smaller, to improve 3D storage
The performance of device.
It further, further include passing through lamination around separation layer 121 in 3D memory device provided in an embodiment of the present invention
Multiple false channel columns 140 of structure, and false the distance between channel 140 and separation layer 121 ratio of at least part and channel column
The distance between 110 is smaller.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (10)
1. a kind of method for manufacturing 3D memory device, comprising:
It is rectangular at former insulating laminate structure on substrate, the original insulating laminate structure include the multiple sacrificial layers being alternately stacked and
Multiple interlayer insulating films；
Form multiple channel columns through the former insulating laminate structure；
Separation layer is formed in the former insulating laminate structure, the separation layer is through the former insulating laminate structure and is in ring
Shape, so that constituting insulating laminate structure by the circular former insulating laminate structure of the separation layer；
Grid conductor is used to replace the sacrificial layer in former insulating laminate structure on the outside of the separation layer to form rhythmic structure of the fence；
And
The conductive channel for running through the insulating laminate structure is formed,
Wherein, at least part of the lateral wall of the separation layer is smooth surface.
2. according to the method described in claim 1, wherein, the separation layer is being to include perpendicular to the cross section on stacking direction
Selected from any one of annulus, elliptical ring and racetrack torus.
3. according to the method described in claim 1, wherein, the material for forming the separation layer includes megohmite insulant.
4. according to the method described in claim 1, wherein, the separation layer has uniform thickness along circumferential direction.
5. according to the method described in claim 1, wherein, the step of being replaced using metal layer, includes:
By the sacrificial layer in the etching removal former insulating laminate structure to form cavity；And
Using the separation layer as deposition barrier layer, deposited metal layer fills the cavity to form the grid conductor.
6. according to the method described in claim 1, the rhythmic structure of the fence includes core space and the step for surrounding the core space
Area,
The method also includes: form multiple false channel columns of at least part lateral wall of the neighbouring separation layer, the vacation
Channel column passes through the core space of the rhythmic structure of the fence.
7. according to the method described in claim 6, wherein, the false channel column of at least some of the multiple vacation channel column with it is described
The distance between separation layer is smaller than at least some false the distance between the channel columns and the channel column.
8. multiple metal layers and the insulation according to the method described in claim 1, wherein, in the rhythmic structure of the fence
Multiple sacrificial layers in laminated construction correspond, and each metal layer is located at same with the corresponding sacrificial layer
Layer.
9. according to the method described in claim 1, wherein, the conductive channel includes the array of multiple conductive column compositions.
10. the manufacturing method according to claim 1, further includes: cmos circuit is formed in the semiconductor substrate,
Wherein, the conductive channel is upwardly extended from the semiconductor substrate, reaches top table through the insulating laminate structure
Face, the conductive channel provide being electrically connected between the cmos circuit and external circuit.
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