CN109390307A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
- Publication number
- CN109390307A CN109390307A CN201711192001.0A CN201711192001A CN109390307A CN 109390307 A CN109390307 A CN 109390307A CN 201711192001 A CN201711192001 A CN 201711192001A CN 109390307 A CN109390307 A CN 109390307A
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- substrate
- electric conductor
- passivation layer
- semiconductor device
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Abstract
本揭露关于半导体装置和其制造方法。本发明的一些实施例揭露一种半导体装置,其包含衬底、电导体及钝化层。所述电导体中的每一者包含穿过所述衬底的第一部分,及位于所述衬底的表面上方且连接到所述第一部分的第二部分。所述钝化层位于所述衬底的所述表面上方,其中所述钝化层部分地覆盖所述电导体中的每一者的所述第二部分的边缘。
Description
技术领域
本揭露关于半导体装置和其制造方法。
背景技术
在集成电路的封装中,半导体裸片可通过接合而进行堆叠,且可接合到其它封装组件,例如中介层及封装衬底。所得封装称为三维集成电路(3DIC)。然而,晶片破裂及应力问题是3DIC中的挑战。
发明内容
本发明的一个实施例是关于一种半导体装置,其包括:衬底,其包含第一表面;多个第一电导体,其中所述多个第一电导体中的每一者包括穿过所述衬底的第一部分,及位于所述衬底的所述第一表面上方且连接到所述第一部分的第二部分;及钝化层,其位于所述衬底的所述第一表面上方,其中所述钝化层部分地覆盖所述多个第一电导体中的每一者的所述第二部分的边缘。
本发明的另一个实施例是关于一种半导体装置,其包括:衬底,其包含第一表面;电导体,其位于所述衬底的所述第一表面上方;及钝化层,其位于所述衬底的所述第一表面上方,其中所述钝化层包含与所述电导体的边缘接触的第一部分,及连接到所述第一部分且与所述电导体的所述边缘隔开的第二部分,且所述钝化层的所述第一部分具有弯曲表面。
本发明的另一个实施例是关于一种制造半导体装置的方法,其包括:接收衬底;在所述衬底的表面上方形成电导体;在所述衬底的所述表面上方选择性地施配光可固化材料;及对所述光可固化材料进行辐照以在所述衬底的所述表面上方形成钝化层,其中所述钝化层部分地覆盖所述电导体的边缘。
附图说明
依据与附图一起阅读的以下详细描述最佳地理解本揭露的实施例的方面。应注意,根据工业中的标准实践,各种结构未必按比例绘制。实际上,为论述清晰起见,可任意地增加或减小各种结构的尺寸。
图1是图解说明根据本揭露的一或多个实施例的各种方面的制造半导体装置的方法的流程图。
图2A、图2B、图2C、图2D、图2E、图2F及图2G是根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一者处的示意图。
图3A及图3B是根据本揭露的一或多个实施例的半导体装置的示意图。
图4A及图4B是根据本揭露的一或多个实施例的半导体装置的示意图。
图5A、图5B、图5C及图5D是根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一者处的示意图。
图6A、图6B及图6C是根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一者处的示意图。
图7A及图7B是根据本揭露的一或多个实施例的半导体装置的示意图。
图8A及图8B是根据本揭露的一或多个实施例的半导体装置的示意图。
具体实施方式
以下揭露提供用于实施所提供标的物的不同构件的许多不同实施例或实例。下文描述元件及布置的特定实例以简化本揭露实施例。当然,这些仅为实例且并非打算为限制性的。举例来说,在描述中第一构件在第二构件上方或所述第二构件上形成可包含其中第一构件与第二构件直接接触地形成的实施例且还可包含其中额外构件可形成于第一构件与第二构件之间使得第一构件与第二构件可不直接接触的实施例。另外,本揭露实施例可在各种实例中重复参考编号及/或字母。此重复是出于简单及清晰目的且并非本质上指示所论述的各种实施例及/或配置之间的关系。
此外,可在本文中为易于描述而使用空间相对术语(例如“下方”、“下面”、“下部”、“上面”、“上部”、“上”等等)来描述一个元件或构件与另一元件或构件的关系,如各图中所图解说明。所述空间相对术语打算囊括在使用或操作中的装置的除图中所描绘定向之外的不同定向。设备可以其它方式定向(旋转90度或以其它定向)且可因此同样地理解本文中所使用的空间相对描述语。
如本文中所使用,例如“第一”、“第二”及“第三”等术语描述各种元件、组件、区域、层及/或区段,这些元件、组件、区域、层及/或区段不应由这些术语限制。这些术语可仅用于将一个元件、组件、区域、层或区段与另一元件、组件、区域、层或区段进行区分。例如“第一”、“第二”及“第三”等术语在用于本文中时并不暗指序列或次序,除非上下文明确指示。
如本文中所使用,术语“大约”、“大体上”、“实质”及“约”用于描述并计及小的变化。当结合事件或情况使用时,所述术语可指其中所述事件或情况精确地发生的实例以及其中所述事件或情况接近近似地发生的实例。举例来说,当结合数值使用时,所述术语可指小于或等于那个数值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%或者小于或等于±0.05%)的变化范围。举例来说,如果两个数值之间的差小于或等于所述值的平均值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%或者小于或等于±0.05%),那么所述值可被视为“大体上”相同或相等的。举例来说,“大体上”平行可指相对于0°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或者小于或等于±0.05°)的角度变化范围。举例来说,“大体上”垂直可指相对于90°的小于或等于±10°(例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或者小于或等于±0.05°)的角度变化范围。
还可包含其它构件及过程。举例来说,可包含测试结构以帮助对3D封装或3DIC装置进行验证测试。举例来说,测试结构可包含形成于重布层中或衬底上的测试垫,所述衬底允许对3D封装或3DIC的测试、对探针及/或探针卡的使用等等。可对中间结构以及最终结构执行验证测试。另外,本文中所揭示的结构及方法可结合并入对已知良好裸片的中间验证以增加合格率且降低成本的测试方法来使用。
在本揭露的一些实施例中,提供一种半导体装置,所述半导体装置包含覆盖衬底的表面且封围电导体的边缘的钝化层。所述钝化层帮助增强电导体的稳健性,且减轻衬底与电导体之间的应力以便减小破裂的风险。
图1是根据本揭露的一或多个实施例的图解说明各种方面的制造半导体装置的方法的流程图。方法100以操作110开始,在操作110中,接收衬底。方法以操作120继续进行,在操作120中,在衬底的表面上方形成电导体。方法以操作130继续进行,在操作130中,在衬底的表面上方选择性地施配光可固化材料。方法以操作140继续,在操作140中,对光可固化材料进行辐照以在衬底的表面上方形成钝化层,其中钝化层部分地覆盖电导体的边缘。
方法100仅为实例,且并不打算限制本揭露实施例超出权利要求书中所明确陈述的内容。可在方法100之前、期间及之后提供额外操作,且可针对方法的额外实施例而替换、消除或来回移动所描述的一些操作。
图2A、图2B、图2C、图2D、图2E、图2F及图2G是根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一者处的示意图,其中图2A、图2B、图2C、图2D、图2E及图2F是示意性部分经放大横截面图,且图2G是示意性横截面图。应注意,一些实施例的方法可为晶片层级方法。如图2A中所描绘,接收衬底10。在一些实施例中,衬底10可包含晶片、半导体衬底、中介层、封装衬底等等。衬底10包含一表面(例如,第一表面10A)及另一表面(例如,与第一表面10A相对的第二表面10B)。在一些实施例中,衬底10包含穿透衬底10的一或多个通孔10H。在一些实施例中,通孔10H可从衬底10的第一表面10A形成。在一些实施例中,通孔10H可从衬底10的第二表面10B形成。在一些实施例中,通孔10H可通过以下操作而形成:使衬底10的第一表面10A或第二表面10B中的一者凹陷而不穿透衬底10,且接着从第一表面10A或第二表面10B中的另一者将衬底10薄化。在一些实施例中,衬底10是具有呈微米级的厚度的薄衬底。在一些实施例中,衬底10的厚度大体上介于从约5微米到约15微米的范围内(例如约10微米),但不限于此。在一些实施例中,通孔10H可通过各向同性蚀刻、各向异性蚀刻、其组合或其它适合操作而形成。在一些实施例中,通孔10H的侧壁可大体上垂直于第一表面10A或第二表面10B。在一些实施例中,通孔10H的侧壁可相对于第一表面10A或第二表面10B而倾斜。在一些实施例中,接近于第二表面10B的通孔10H的尺寸比接近于第一表面10A的通孔10H的尺寸大。在一些实施例中,接近于第一表面10A的通孔10H的尺寸比接近于第二表面10B的通孔10H的尺寸大。
如图2B中所描绘,在衬底10的第一表面10A上方形成一或多个电导体(例如,第一电导体20)。在一些实施例中,第一电导体20可包含但不限于导电凸块,例如可控塌陷芯片连接凸块(C4凸块)等等。在一些实施例中,第一电导体20可包含第一部分21及连接到第一部分21的第二部分22。在一些实施例中,第一部分21大体上形成于通孔10H中,且第二部分22形成于衬底10的第一表面10A上方及通孔10H外部。第一电导体20可包含例如金属或合金等导电材料,但不限于其。在一些实施例中,第一电导体20的材料可包含但不限于铜、其合金等等。第一电导体20可通过电镀、沉积或其它适合操作而形成。在一些实施例中,第一电导体20的第一部分21及第二部分22可由相同材料形成,但不限于此。在一些实施例中,第一电导体20的第一部分21及第二部分22可单独地形成。在一些实施例中,第一部分21可从衬底10的第二表面10B形成于通孔10H中,而第二部分22可在形成第一部分21之后形成于衬底10的第一表面10A上方。在一些实施例中,第一电导体20的第一部分21及第二部分22可从衬底10的第一表面10A形成。在一些实施例中,第一电导体20的第一部分21包含第一宽度W1,且第一电导体20的第二部分22包含比第一宽度W1宽的第二宽度W2。在一些实施例中,第二部分22的高度Ha大于第一部分21的高度,但不限于此。通过实例方式,第二部分22的高度Ha大体上介于从约10微米到约50微米的范围内,且第一部分21的高度Hb大体上介于从约5微米到约20微米的范围内(例如约10微米),但不限于此。
在一些实施例中,导电凸块26可形成于第一电导体20的第二部分22上方。导电凸块26可经配置以电连接到封装衬底或其它电子装置。在一些实施例中,导电凸块26由具有比第一电导体20的熔点低的熔点的导电材料形成。在一些实施例中,导电凸块26的材料可包含但不限于锡(Sn)、其合金等等。
在一些实施例中,在衬底10的第一表面10A上方形成钝化层。在一些实施例中,钝化层可通过图2C及图2D中所图解说明的操作而形成,但不限于此。如图2C中所描绘,在衬底10的第一表面10A上方选择性地施配光可固化材料27。在一些实施例中,光可固化材料27包含具有光敏特性的聚合材料。在一些实施例中,用于光可固化材料27的聚合材料可包含但不限于环氧树脂、丙烯酸树脂、聚酰亚胺(PI)、聚苯并唑(PBO)等等。在一些实施例中,可通过印刷等等而穿过喷嘴28选择性地施配光可固化材料27。在一些实施例中,光可固化材料27在被施配的同时由光束29(例如UV束或其它磁波)进行辐照。在一些实施例中,辐照帮助减小光可固化材料27的流动性且使光可固化材料27凝固。
如图2D中所描绘,钝化层30可形成于衬底10的第一表面10A上方,从而在光可固化材料27被固化及凝固之后部分地覆盖第一电导体20的边缘。在一些实施例中,钝化层30部分地覆盖第一电导体20的第二部分22的边缘22E。在一些实施例中,钝化层30并不放置于第一电导体20的第一部分21的边缘21E与通孔10H的侧壁之间。在一些实施例中,钝化层30包含与第一电导体20的第二部分22的边缘22E接触的第一部分31,及与第二部分22的边缘22E隔开的第二部分32,所述第二部分32覆盖衬底10的第一表面10A且连接到第一部分31。在一些实施例中,钝化层30的第一部分31至少部分地覆盖边缘22E且部分地暴露第一电导体20的第二部分22的边缘22E。在一些实施例中,钝化层30的第一部分31可包含环绕第二部分22的边缘22E的圈形(即,环形)结构,且第二部分32连接到第一部分31并覆盖衬底10的第一表面10A。在一些实施例中,钝化层30的第一部分31的第一高度H1比第一电导体20的第二部分22的高度Ha低,如图2D中所展示。在一些替代实施例中,钝化层30的第一部分31的第一高度H1可大体上等于第一电导体20的第二部分22的高度Ha,如图2E中所展示。在一些实施例中,第一部分31的第一高度H1约为第二部分22的高度Ha的一半或小于第二部分22的高度Ha的一半,但不限于此。在一些实施例中,钝化层30的第一部分31的第一高度H1比钝化层30的第二部分32的第二高度H2大。在一些实施例中,第一高度H1与第二高度H2的比率大于1且大体上小于约15、大体上大于约1.5且大体上小于约15,或大体上大于约1.5且大体上小于约8,但不限于此。在一些实施例中,第一部分31的第一高度H1大体上介于从约5微米到约50微米的范围内、大体上介于从约5微米到约40微米的范围内或大体上介于从约5微米到约30微米的范围内,但不限于此。在一些实施例中,第二部分32的第二高度H2大体上介于从约2微米到约15微米的范围内,但不限于此。
在一些实施例中,举例来说在衬底10为较薄的情况下,钝化层30的第二部分32帮助保护衬底10免遭破裂。在一些实施例中,钝化层30的具有较高高度H1的第一部分31帮助增强第一电导体20的稳健性,且帮助减轻衬底10与第一电导体20之间的应力。
在一些实施例中,光可固化材料27的材料为亲水性的,此由于毛细管现象而帮助光可固化材料27覆盖第一电导体20的第二部分22的边缘22E。在此情形中,可在无需额外光刻操作的情况下形成具有不同轮廓的钝化层30。在一些实施例中,光可固化材料27可经选择性地施配以避免第一电导体20上的残留物,且可省略额外除渣处理(例如等离子体处理)。在一些实施例中,钝化层30的由亲水性材料形成的第一部分31可具有弯曲表面31S。通过实例方式,弯曲表面30S可包含凹形表面,如图2F中所描绘。
如图2G中所描绘,其它组件或层可在形成第一电导体20及钝化层30之前或之后形成于衬底的第二表面10B上方。在一些实施例中,电路层40形成于衬底10的第二表面10B上方且电连接到第一电导体20。在一些实施例中,电路层40可包含但不限于重布层(RDL)、导电柱状物(post)、导电柱、其组合等等。在一些实施例中,至少一个半导体裸片50形成于电路层40上方。在一些实施例中,至少一个半导体裸片50可包含主动半导体裸片、被动半导体裸片或其组合。通过实例方式,至少一个半导体裸片50可包含系统单芯片(SOC)裸片、存储器裸片等等。在一些实施例中,第二电导体42可形成于至少一个半导体裸片50与电路层40之间,且电连接到至少一个半导体裸片50及电路层40。在一些实施例中,第二电导体42可包含导电凸块、导电球、导电膏等等。在一些实施例中,底胶层44可形成于衬底10的第二表面10B上方、介于至少一个半导体裸片50与电路层40之间且围绕第二电导体42。在一些实施例中,底胶层44经配置以保护并固定至少一个半导体裸片50及第二电导体42。在一些实施例中,囊封剂46可形成于衬底10的第二表面10B上方。在一些实施例中,囊封剂46可横向封围至少一个半导体裸片50及底胶层44。在一些实施例中,囊封剂46可进一步覆盖至少一个半导体裸片50的上部表面。在一些实施例中,囊封剂46的材料可包含但不限于模塑料,例如环氧树脂等等。在一些实施例中,半导体装置1可为晶片上覆芯片(CoW)装置,但不限于此。在一些实施例中,可执行单粒化操作(例如切割操作)以形成半导体装置1。在一些实施例中,半导体装置1可通过第一电导体20电连接到封装衬底以形成衬底上覆晶片上覆芯片(chip-on-wafer-on-substrate)(CoWoS)封装。
在本揭露的一些实施例中,具有较厚第一部分31的钝化层30密封第一电导体20的第二部分22的边缘22E,且因此帮助增强第一电导体20的稳健性。具有覆盖第二部分22的边缘22E的第一部分31及覆盖衬底10的第一表面10A的第二部分32的钝化层30还可帮助补偿或减轻衬底10与第一电导体20之间的应力,且因此可帮助减轻衬底10的翘曲。在一些实施例中,钝化层30可通过选择性地施配而由光可固化材料27形成。光可固化材料27可为亲水性材料,其可由于毛细管现象而爬升到第一电导体20的第二部分22的边缘22E。在此情形中,可在无需额外光刻操作的情况下形成具有不同轮廓的钝化层30。在一些实施例中,光可固化材料27可经选择性地施配以避免第一电导体20上的残留物,且可省略额外除渣处理。
本揭露的半导体装置及其制造方法不限于上文所提及的实施例,而是可具有其它不同实施例。为简化描述且为方便进行本揭露的实施例中的每一者之间的比较,以相同编号来标记以下实施例中的每一者中的相同组件。为了更容易地比较实施例之间的差异,以下描述将详述不同实施例当中的不同点且将不多余地描述相同构件。
图3A及图3B是根据本揭露的一或多个实施例的半导体装置的示意图,其中图3A是示意性横截面图,且图3B是示意性部分经放大横截面图。如图3A及图3B中所描绘,不同于图2E的半导体装置1,半导体装置2可进一步包含在形成第一电导体20的第二部分22之前形成于衬底10的第一表面10A上方的绝缘层24。在一些实施例中,绝缘层24可包含通过低温操作而形成的聚合材料。在一些实施例中,绝缘层24的材料可包含但不限于聚酰亚胺。在一些实施例中,绝缘层24的厚度大体上介于从约0.5微米到约15微米的范围内(例如约4微米),但不限于此。在一些实施例中,第一电导体20的第二部分22形成于绝缘层24上方,且电连接到第一部分21。在一些实施例中,钝化层30形成于绝缘层24上方,从而部分地覆盖第一电导体20的边缘。在一些实施例中,钝化层30可以与图2C中所揭示类似的方式形成,但不限于此。在一些实施例中,钝化层30包含具有第一高度H1且与第一电导体20的第二部分22的边缘22E接触的第一部分31,及具有第二高度H2且与第一电导体20的第二部分22的边缘22E隔开并连接到第一部分31的第二部分32。
图4A及图4B是根据本揭露的一或多个实施例的半导体装置的示意图,其中图4A是示意性横截面图,且图4B是示意性部分经放大横截面图。如图4A及图4B中所描绘,不同于图3A及图3B的半导体装置2,半导体装置3的绝缘层24可在形成第一电导体20的第一部分21及第二部分22之前形成于衬底10的第一表面10A上方。在一些实施例中,第一电导体20的第一部分21形成于衬底10中,且绝缘层24延伸于衬底10与第一电导体20的第一部分21的边缘21E之间。在一些实施例中,第一电导体20的第二部分22形成于绝缘层24上方,且电连接到第一部分21。在一些实施例中,钝化层30形成于绝缘层24上方,从而部分地覆盖第一电导体20的边缘。在一些实施例中,钝化层30包含具有第一高度H1且与第一电导体20的第二部分22的边缘22E接触的第一部分31,及具有第二高度H2且与第一电导体20的第二部分22的边缘22E隔开并连接到第一部分31的第二部分32。
图5A、图5B、图5C及图5D是根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一者处的示意图,其中图5A、图5B及图5C是示意性横截面图,且图5D是示意性部分经放大横截面图。如图5A中所描绘,接收衬底10。在一些实施例中,电路层40形成于衬底10的第二表面10B上方。在一些实施例中,介电层41(图5D中所展示)可形成于衬底10的第二表面10B与电路层40之间。在一些实施例中,至少一个半导体裸片50形成于电路层40上方。在一些实施例中,第二电导体42可形成于至少一个半导体裸片50与电路层40之间,且电连接到至少一个半导体裸片50及电路层40。在一些实施例中,底胶层44可形成于衬底10的第二表面10B上方、介于至少一个半导体裸片50与电路层40之间且围绕第二电导体42。在一些实施例中,囊封剂46可形成于衬底10的第二表面10B上方。
在一些实施例中,第一电导体20可形成于衬底10的第一表面10A上方。在一些实施例中,第一电导体20可包含第一部分21及连接到第一部分21的第二部分22。在一些实施例中,第一部分21大体上形成于通孔10H中,且第二部分22形成于衬底10的第一表面10A上方及通孔10H外部。在一些实施例中,第一部分21及第二部分22可由相同导电材料形成。在一些实施例中,第一电导体20的材料可包含但不限于锡、其合金等等。在一些实施例中,第二部分22的宽度比第一部分21的宽度宽。
如图5B中所描绘,钝化层30形成于衬底10的第一表面10A上方,从而部分地覆盖第一电导体20的边缘。在一些实施例中,钝化层30可以与图2C中所揭示类似的方式形成,但不限于此。在一些实施例中,钝化层30包含具有第一高度H1(图5D中所展示)且与第一电导体20的第二部分22的边缘22E接触的第一部分31,及具有第二高度H2(图5D中所展示)且与第一电导体20的第二部分22的边缘22E隔开并连接到第一部分31的第二部分32。在一些实施例中,钝化层30可环绕第一电导体20的第二部分22的边缘22E。在一些实施例中,绝缘层24(图5D中所展示)可在形成钝化层30之前形成。在一些实施例中,钝化层30的第二部分32帮助保护衬底10免遭破裂。在一些实施例中,钝化层30的具有较高高度H1的第一部分31帮助增强第一电导体20的稳健性,且帮助减轻衬底10与第一电导体20之间的应力。在一些实施例中,第一电导体20的第二部分22可包含由钝化层30横向覆盖的第一子部分221,及从钝化层30横向暴露的第二子部分222。
如图5C及图5D中所展示,在形成钝化层30之后对第一电导体20执行回焊操作以形成半导体装置4。在一些实施例中,第一电导体20的第一部分21在回焊操作期间由衬底10约束,且因此具有与在回焊操作之前的宽度大体上相同的第一宽度W1。在一些实施例中,第一电导体20的第二部分22的第一子部分221在回焊操作期间由钝化层30的第一部分31约束,且因此具有与在回焊操作之前的宽度大体上相同的第二宽度W2。在一些实施例中,第一电导体20的第二部分22的第二子部分222从钝化层30的第一部分31暴露,借此在回焊操作之后横向延伸,且因此具有第三宽度W3。在回焊操作之后,第二宽度W2比第一宽度W1宽、第三宽度W3比第二宽度W2宽,且第二子部分222横向突出以与钝化层30部分地重叠。
图6A、图6B及图6C是根据本揭露的一或多个实施例的制造半导体装置的各种操作中的一者处的示意图,其中图6A及图6B是示意性横截面图,且图6C是示意性部分经放大横截面图。如图6A中所描绘,不同于图5C及图5D的半导体装置4,在形成钝化层30之前对第一电导体20执行回焊操作。由于第一电导体20的第二部分22在不具有约束的情况下被回焊,因此第一电导体20的第二部分22经延伸以具有大体上球形状。
如图6B及图6C中所描绘,钝化层30形成于衬底10的第一表面10A上方,从而部分地覆盖第一电导体20的边缘以形成半导体装置5。在一些实施例中,钝化层30可以与图2C中所揭示类似的方式形成,但不限于此。在一些实施例中,钝化层30包含具有第一高度H1且与第一电导体20的第二部分22的边缘22E的一部分接触的第一部分31,及具有第二高度H2且与第一电导体20的第二部分22的边缘22E隔开并连接到第一部分31的第二部分32。在一些实施例中,第一电导体20的第二部分22的第二宽度W2比第一电导体20的第一部分21的第一宽度W1宽。
图7A及图7B是根据本揭露的一或多个实施例的半导体装置的示意图,其中图7A是示意性横截面图,且图7B是示意性部分经放大横截面图。如图7A及图7B中所描绘,不同于图2E的半导体装置1,半导体装置6的钝化层30至少部分地覆盖第二部分22的边缘22E,但暴露衬底10的第一表面10A。在一些实施例中,钝化层30可包含环绕第二部分22的边缘22E的圈形结构。钝化层30可具有低于或等于第一电导体20的第二部分22的高度Ha的高度H。在一些实施例中,具有圈形结构的钝化层30可应用于本揭露的其它实施例。
图8A及图8B是根据本揭露的一或多个实施例的半导体装置的示意图,其中图8A是示意性横截面图,且图8B是示意性部分经放大横截面图。如图8A及图8B中所描绘,半导体装置7包含衬底10、邻近于衬底10的第一表面10A的第一电导体20及位于衬底10的第一表面10A上方的钝化层30。在一些实施例中,第一电导体20中的每一者包含穿过衬底10的第一部分21及位于衬底10的第一表面10A上方且连接到第一部分21的第二部分22。在一些实施例中,第一电导体20的第一部分21包含第一宽度W1,且第一电导体20的第二部分22包含比第一宽度W1宽的第二宽度W2。在一些实施例中,钝化层30包含覆盖第一部分21的边缘21E的第一部分33,及介于第二部分22的表面22B与衬底10的第一表面10A之间的第二部分34。在一些实施例中,半导体装置7可进一步包含放置于衬底10的第二表面10B上方的电路层40、至少一个半导体裸片50、第二电导体42、底胶层44及囊封剂46。
在一些实施例中,钝化层30的第二部分34具有大体上大于约10微米的高度H。在一些实施例中,第二部分34的高度H大体上介于从约10微米到约40微米的范围内,或大体上介于从约10微米到约15微米的范围内,但不限于此。在一些实施例中,钝化层30可包含聚合钝化层,且可以与图2C中所揭示类似的方式形成,但不限于此。具有较厚厚度的第二部分34可帮助提供缓冲器且减轻衬底10与第一电导体20之间的应力,以便减小衬底10的破裂及第一电导体20的脱层的风险。
在本揭露的一些实施例中,具有覆盖电导体的边缘的较厚部分的钝化层帮助增强电导体的稳健性,且帮助补偿或减轻衬底与电导体之间的应力。在本揭露的一些实施例中,电导体与衬底之间的钝化层帮助提供缓冲器且减轻衬底与电导体之间的应力。在本揭露的一些实施例中,钝化层可通过选择性地施配而由亲水性光可固化材料形成,且可爬升到电导体的边缘。
在一个示范性方面中,一种半导体装置包含衬底、第一电导体及钝化层。所述衬底包含第一表面。所述第一电导体中的每一者包括穿过所述衬底的第一部分,及位于所述衬底的所述第一表面上方且连接到所述第一部分的第二部分。所述钝化层位于所述衬底的所述第一表面上方,其中所述钝化层部分地覆盖所述第一电导体中的每一者的所述第二部分的边缘。
在另一方面中,一种半导体装置包含衬底、电导体及钝化层。所述衬底包含第一表面。所述电导体位于所述衬底的所述第一表面上方。所述钝化层位于所述衬底的所述第一表面上方。所述钝化层包含与所述电导体的边缘接触的第一部分,及连接到所述第一部分且与所述电导体的所述边缘隔开的第二部分。所述钝化层的所述第一部分具有弯曲表面。
在又一方面中,提供一种用于制造半导体装置的方法。接收衬底。在所述衬底的表面上方形成电导体。在所述衬底的所述表面上方选择性地施配光可固化材料。对所述光可固化材料进行辐照以在所述衬底的所述表面上方形成钝化层,其中所述钝化层部分地覆盖所述电导体的边缘。
前述内容概述数个实施例的构件,使得所属领域的技术人员可较好地理解本揭露实施例的方面。所属领域的技术人员应了解,其可容易地使用本揭露实施例作为设计或修改用于实施与本文中介绍的实施例相同的目的及/或实现与所述实施例相同的优点的其它过程及结构的基础。所属领域的技术人员还应认识到,此类等效构造并不背离本揭露实施例的精神及范围,且其可在不背离本揭露实施例的精神及范围的情况下在本文中做出各种改变、替换及更改。
Claims (1)
1.一种半导体装置,其包括:
衬底,其包含第一表面;
多个第一电导体,其中所述多个第一电导体中的每一者包括穿过所述衬底的第一部分,及位于所述衬底的所述第一表面上方且连接到所述第一部分的第二部分;及
钝化层,其位于所述衬底的所述第一表面上方,其中所述钝化层部分地覆盖所述多个第一电导体中的每一者的所述第二部分的边缘。
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TWI741090B (zh) | 2021-10-01 |
TW201911497A (zh) | 2019-03-16 |
CN109390307B (zh) | 2023-01-10 |
US20230146652A1 (en) | 2023-05-11 |
US11605579B2 (en) | 2023-03-14 |
US20190051589A1 (en) | 2019-02-14 |
US10535591B2 (en) | 2020-01-14 |
US20200152560A1 (en) | 2020-05-14 |
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