CN109359082A - A kind of real-time monitoring system of usb data based on FPGA and method - Google Patents
A kind of real-time monitoring system of usb data based on FPGA and method Download PDFInfo
- Publication number
- CN109359082A CN109359082A CN201811082851.XA CN201811082851A CN109359082A CN 109359082 A CN109359082 A CN 109359082A CN 201811082851 A CN201811082851 A CN 201811082851A CN 109359082 A CN109359082 A CN 109359082A
- Authority
- CN
- China
- Prior art keywords
- usb
- data
- module
- ulpi
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012544 monitoring process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000012545 processing Methods 0.000 claims abstract description 61
- 238000004891 communication Methods 0.000 claims abstract description 42
- 230000005540 biological transmission Effects 0.000 claims abstract description 36
- 230000006870 function Effects 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 4
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052749 magnesium Inorganic materials 0.000 claims description 3
- 239000011777 magnesium Substances 0.000 claims description 3
- 238000012546 transfer Methods 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000003384 imaging method Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 241001269238 Data Species 0.000 description 2
- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000003362 replicative effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Abstract
The present invention relates to a kind of real-time monitoring system of usb data based on FPGA and methods, belong to electronics and field of communication technology.The present invention includes fpga chip, USB transceiver module I, USB transceiver module II, DDR3 SDRAM memory；Fpga chip includes: ULPI data transmit-receive module I, ULPI data transmit-receive module II, ULPI control module I, ULPI control module II, data temporary storage module and FPGA signal processing and Coordination module；The present invention crosses FPGA and does transfer, can not be unpacked, stored, forwarded to the data on usb bus after accessing USB transmission line by PC machine, realization is monitored and acquired in real time without intrusive usb data from data plane.
Description
Technical field
The present invention relates to a kind of real-time monitoring system of usb data based on FPGA and methods, belong to electronics and the communication technology
Field.
Background technique
FPGA (Field-Programmable Gate Array), full name is field programmable gate array.It is conduct
One of field specific integrated circuit (ASIC) semi-custom circuit and occur, not only solved the deficiency of custom circuit, but gram
The limited disadvantage of original programming device gate circuit number is taken.The electricity completed with hardware description language (Verilog or VHDL)
Road design can be quickly burnt on FPGA and be tested by simply comprehensive and layout, be the technology of present IC verifying
Mainstream.FPGA can quick finished product, the mistake and cheaper cost that can be modified in correction program.Meanwhile FPGA energy
It is enough to realize very more logic functions, since internal structure is flexible and changeable, the logic unit that is included, programmable interconnector
Any logic function can may be implemented in specific application with I/O unit by user program, meet various design need
It asks.
USB (Universal Serial Bus), full name is universal serial bus, is nineteen ninety-five Microsoft, Compaq
A kind of newer PC serial communication protocol formulated with companies' joints such as IBM.USB device is fairly simple, facilitates interaction, price ratio
It is less expensive, and connected as a kind of serial ports, multiple be used in combination may be implemented.USB interface has become now many numbers
The standard configuration interface of equipment (such as PC machine, test and measuring instrument, camera, mobile phone and all kinds of embedded boards).
It is all point-to-point transmission but during USB transmission.Although now with Portable mobile computer,
Carrying and use at any time can be eaily carried out, it is contemplated that some special working environments and job costs etc. are asked
Topic, if we are inconvenient, or do not allow to monitor the data on transmission line in real time by PC machine, and
Forwarding and pretreatment are being carried out to the data of real-time monitoring, we need other equipment just to carry out the transfer of data and pre-
Processing.So there is the real-time monitoring circuit of usb data based on FPGA.
Summary of the invention
The technical problem to be solved by the present invention is the present invention provides a kind of real-time monitoring system of the usb data based on FPGA
And method, for using FPGA as core chips, auxiliary to monitor the data on usb bus with USB processing chip, completion in real time
And acquisition.
The technical scheme is that: a kind of real-time monitoring system of usb data based on FPGA, including fpga chip 1, USB
Transceiver module I 2, USB transceiver module II 3, DDR3SDRAM memory 4；
The fpga chip 1 includes: ULPI data transmit-receive module I 6, ULPI data transmit-receive module II 7, ULPI control module
I 8, ULPI control module II 9, data temporary storage module 10 and FPGA signal processing and Coordination module 12；
The fpga chip 1 connects USB transceiver module I 2, USB transceiver module II 3, DDR3SDRAM memory 4；
USB transceiver module I 2, USB transceiver module II 3 are connected to fpga chip 1, USB transceiver module I by different I/O mouths
2 pass through ULPI data transmit-receive module I 6, ULPI control module I 8 and FPGA signal processing and Coordination module 12；FPGA signal processing
It is connect by data temporary storage module 10 with DDR3SDRAM memory 4 with Coordination module 12, FPGA signal processing and Coordination module 12
It is connect by ULPI data transmit-receive module II 7, ULPI control module II 9 with USB transceiver module II 3.
The fpga chip 1 further includes data forwarding module 11, back-end circuit 5；Data forwarding module 11 and back-end circuit 5
Connection, FPGA signal processing and Coordination module 12 are connect with data forwarding module 11 to be read out of DDR3SDRAM memory 4 for handle
The data taken are sent to back-end circuit 5 by data forwarding module 11, and back-end circuit 5 is determined by its communication protocol or its interface
The type and communication protocol classification of connector.
The back-end circuit 5 can either carry out the mould of lucky algorithm process using Real-time image display circuit to image
Block.
After the USB transceiver module I 2 receives data, the data letter for meeting ULPI agreement is translated by USB3320 chip
Number, cooperate with ULPI control module I 8 and ULPI data transmit-receive module I 6 to be sent to FPGA signal processing and Coordination module 12, ULPI
I 6 signals revivifications received of data transmit-receive module at original signal, then by FPGA signal processing and Coordination module 12 duplication and
The data portion of forwarding, duplication is stored into DDR3SDRAM memory 4 by data temporary storage module 10, another passes through again
ULPI data transmit-receive module II 7 translates into ULPI signal and is sent to USB transceiver module II 3, is then forwarded to PC later.
Mode of the USB transceiver module I 2 when the equipment with both ends is connect is by ULPI control module I 8 can
Choosing；When the equipment that USB transceiver module I 2 connects is host equipment, USB is received by ULPI control module I 8
The work of device module I 2 is sent out to be arranged under equipment mode；When the equipment that USB transceiver module I 2 connects is the USB device of standard
When, USB transceiver module I 2 works under OTG mode, i.e. 2 hosted of USB transceiver module I.
The data that the USB transceiver module I 2 receives by the FPGA signal processing in fpga chip 1 and coordinate mould
Block 12 preferentially guarantees that data can be then forwarded to PC machine, first by passing to USB transceiver module II 3 after fpga chip 1 with reduction
The data transmission link of USB；Next is only the temporary and forwarding to data are listened to；The flow direction of usb data judges that data are real-time
The work that monitoring and unloading and usb communication are established is completed by FPGA signal processing and Coordination module 12.
Core chips used in the fpga chip 1 is the XC6SLX16- of Xilinx company Spartan6 series
FTG256 chip；DDR3SDRAM memory is the MT41J128M16HA-15E 256MB DDR3 storage chip of magnesium light company；Institute
It is identical to state USB transceiver module I 2, II 3 structure of USB transceiver module, wherein including USB3320 chip and USB interface.
A kind of real-time monitor method of usb data based on FPGA, USB transceiver module I 2, which is connected to, can be read equipment, root
According to the type that equipment can be read, USB transceiver module I 2 is set as to base by ULPI control module I 8 by different mode
The communication on both sides is realized in usb protocol；
According to USB communication protocol, after USB transceiver module I 2 receives the data transmitted, by USB transceiver module I 2
The data packet of USB is carried out to translate into the signal for meeting ULPI agreement, then is sent in fpga chip 1 by ULPI agreement
FPGA signal processing and Coordination module 12 are kept in and are forwarded；The data portion of duplication is stored by data temporary storage module 10
In DDR3SDRAM memory 4, another passes through ULPI data transmit-receive module II 7 again and translates into ULPI signal and be sent to USB receipts
Device module II 3 is sent out, is then forwarded to PC later, to restore the data transmission link of USB, temporary data pass through data forwarding mould again
Block 11 is sent to back-end circuit 5.
The equipment that can be read includes USB flash disk or PC；It is USB flash disk when equipment can be read, is received and dispatched according to USB communication protocol and USB
USB transceiver module I 2 is set as host mode by ULPI control module I 8 by the function of device module I 2, and equipment can be read
USB flash disk is used as from equipment and works, and the communication on both sides is realized based on usb protocol；
When it is PC that equipment, which can be read, according to the function of USB communication protocol and USB transceiver module I 2, controlled by ULPI
USB transceiver module I 2 is set as equipment mode by module I 8 processed, and equipment PC can be read as host work, is assisted based on USB
View realizes the communication on both sides.
The working principle of the invention is:
The USB transceiver module I 2, USB transceiver module II 3 include that chip USB3320, peripheral circuit and USB connect
Mouthful.Due to the power supply of this invention used development board power supply interface and USB transceiver module I 2, USB transceiver module II 3
Pin mismatches, so being powered after drawing power pins by constant voltage dc source.USB transceiver module I 2, USB transmitting-receiving
Crystal oscillation clock circuit in device module II 3 provides the clock signal of 25MHz for the module；Switch STMPS2151STR control to
The VBUS power supply of Micro Type B USB interface offer+5V.USB3320 is a piece of ULPI transceiving chip, will pass through the number of the chip
It is converted according between progress differential signal and the signal for meeting ULPI communication protocol.It, can according to the difference of the device type connected
Select work in different modes (host mode or USB device mode).ULPI transmits chip USB3320 and fpga chip
Data transmission between 1 is realized by data line D0~D7 that bit wide is 8；
Data are converted the data that bit wide is 8 by the ULPI transmission chip USB3320 of USB transceiver module I 2；Then
Fpga chip 1 is sent to by D0~D7 of the USB3320 chip in USB transceiver module I 2；In USB transceiver module II 3
USB3320 chip receive the ULPI signal from fpga chip 1 by 8 bit data bus of D0~D7, handle as difference letter
The equipment for being sent to connection from USB interface again after number；
Data are converted the data that bit wide is 8 by the ULPI transmission chip USB3320 of USB transceiver module II 3；Then
Fpga chip 1 is sent to by D0~D7 of the USB3320 chip in USB transceiver module II 3；In USB transceiver module I 2
USB3320 chip receive the ULPI signal from fpga chip 1 by 8 bit data bus of D0~D7, handle as difference letter
The equipment for being sent to connection from USB interface again after number；
In addition, single USB transceiver module includes two USB interfaces, A type mother's mouth, a Micro Type B is connect
Mouthful, wherein only being connected under equipment mode to the VBUS driving power of Micro Type B interface offer+5V so A type mother's mouth is used as
Other hosts, Micro Type B mouth, which is used as under host mode, connects other from equipment.In the present invention in use, fixed USB transceiver
Module II 3 is connected solely to host, i.e., USB transceiver module II 3 work are under equipment (Device) mode；USB transceiver
Module I 2 is different according to the equipment of connection, can choose work in host mode or under equipment mode.Therefore, of the invention
Secure effective data flow are as follows: the connection between PC and fpga chip 1 is completed by USB transceiver module II 3.So design
Complexity of the invention can be reduced.
The fpga chip 1 is: the low cost of Xilinx company production, low-power consumption FPGA chip Spartan-6 series
XC6SLX16-FTG256；Collocation FPGA peripheral circuit, including power supply circuit and clock circuit；With the opening for core of fpga chip 1
On to be also equipped with other accessories include DDR3SDRAM memory 4, key circuit and flowing water circuit for lamp, key circuit includes key
For being resetted, whether flowing water circuit for lamp works normally for cue circuit.Two 2 × 32Pin pins of fpga chip point
Be not connected to Bank0 the and Bank1 corresponding pin of fpga chip, the other end respectively with USB transceiver module I 2, USB transceiver
Module II 3 is connected, and DDR3SDRAM memory 4 is connected to the Bank3 corresponding pin of fpga chip 1；In FPGA peripheral circuit when
Clock circuit passes through pin SYS_CLK after power-up and provides the clock signal of 50MHz, power-supplying circuit master to fpga chip 1
+ the 5V ,+3.3V and+1.5V voltage needed is provided to fpga chip 1 and DDR3SDRAM memory 4.When system electrification is initial
Change and complete, and after being connected to USB transceiver module I 2 and receiving data request signal, requested data are received and dispatched from USB
Device module I 2 flows into；Data are when passing through fpga chip 1, via ULPI data transmit-receive module I 6, ULPI control module I 8
After be reduced into initial data and flow into FPGA signal processing and Coordination module 12.To restore usb bus transmission line, FPGA signal
Processing and Coordination module 12 preferentially send ULPI data transmit-receive module II 7 for the data from USB transceiver module I 2,
Under the cooperation of ULPI control module II 9, USB transceiver module II 3 will be sent to according to ULPI agreement after data encoding, then again
It is sent to PC machine.FPGA signal processing and Coordination module 12 replicate the data flowed into from USB transceiver module I 2, send
It to data temporary storage module 10 and stores into DDR3SDRAM memory 4, and transferring data forwarding module 11 when needed will
The data for monitoring acquisition are sent to back-end circuit 5.
The course of work of the present invention are as follows:
After powering on, ULPI control module I 8, ULPI control module II 9 first control USB transceiver module I 2 respectively and USB is received
Hair device module II 3 is initialized, and then ULPI data transmit-receive module I 6, ULPI data transmit-receive module II 7 control USB receipts respectively
Hair device module I 2, device enumeration device type from USB transceiver module II 3 to connection or send oneself device type letter
Breath, establishes connection after shaking hands；Then data request command is sent by the host that USB transceiver module II 3 connects, at FPGA signal
After reason and Coordination module 12 receive the order, then controls USB transceiver module I 2 and send request of data to the equipment connected
Order；After the equipment returned data that USB transceiver module I 2 connects, in FPGA signal processing and Coordination module 12, then number
USB transceiver module II 3 is sent to according to along the direction for returning to PC machine；And while being sent to PC machine, it is temporary to replicate a data
Into DDR3SDRAM memory 4；Finally, being read in DDR3SDRAM memory 4 temporarily by FPGA signal processing and Coordination module 12
The data deposited are sent to back-end circuit 5 by data forwarding module 11.
The ULPI data transmit-receive module I 6 and ULPI data transmit-receive module II 7 are by operating on fpga chip
Verilog code realizes corresponding function.The module according to the ULPI transport protocol of USB2.0, by USB transceiver module I 2,
The bit wide that USB transceiver module II 3 transmits is reduced into initial data type for 8 data-signals, and in FPGA
When chip sends data to USB transceiver module I 2, USB transceiver module II 3, data are translated into symbol from initial data
The data for closing ULPI agreement, then send.
The ULPI control module I 8 and ULPI control module II 9 are equally the Verilog by operating on fpga chip 1
Program is realized.The module passes through tetra- signals realizations pair of NTX, DIR, STP and CLK according to the ULPI transport protocol of USB2.0
The control of USB3320 chip, the data transfer sequence in control bus and judge whether bus is occupied.
According to ULPI agreement, ULPI data transmit-receive module I 6, ULPI control module I 8 form an end of link I (also referred to as
The end Link 1), ULPI data transmit-receive module II 7, ULPI control module II 9 also form (the also referred to as end Link of end of link II
2)；
USB transceiver module I 2, USB transceiver module II 3 are collectively referred to as ULPI transceiver end, the also referred to as end PHY (ULPI
Transceiver)。
Signal DIR keeps high level, does not have when ULPI transceiver end sends data by data/address bus to end of link
Low level is maintained for when there are data, and whether monitored link end has data to send to ULPI transceiver end；Signal CLK is
The Clock Signal pin of USB3320 chip can export the clock signal of 60MHz, which can also be referred in piece into
It exercising and uses, the present invention is the clock signal of synchronous fpga chip 1 and USB3320 chip, while being provided using FPGA development board
The clock signal of 50MHz；After data are received by ULPI transceiver end, driving signal NTX is represented NTX at a high potential
ULPI transceiver end has been received data, and it is total in next clock cycle the data to be sent next time to be put into data
On line, data are sent when waiting next clock transition；STP signal represents the stopping of communication, and STP is transmitted in no data
When be each clock cycle to send a stop signal, if there is data are transmitted on the data bus, then being transmitted in data
After next cycle, last position of the data of a cycle transmission in signal STP holding, and enter each clock week
Phase states primary circulation.
So the data that USB transceiver module I 2 and USB transceiver module II 3 are sent to by fpga chip 1 are controlled, it is main
It will be by judging signal NTX, signal DIR and signal STP.Each group of ULPI data transmit-receive module and ULPI control module (ULPI
Data transmit-receive module I 6, ULPI control module I 8 are one group, and ULPI data transmit-receive module II 7, ULPI control module II 9 are one
Group) principle that cooperates is as follows: firstly, being initialized after device power, USB transceiver module I 2 and USB transceiver module
II 3 send handshake packet to the equipment (or host) of connection respectively, enumerate device type, establish connection.When we need from FPGA
When a transmission data of the chip 1 into USB transceiver module I 2 or USB transceiver module II 3, i.e., received from end of link to ULPI
When sending out device end transmission data, it is necessary first to judge whether STP signal keeps the signal of a cycle, work as if it is, representing
Preceding time data are transmitted without progress；There is no feelings of the data transmission just there is no ULPI transceiver end to end of link transmission data
Condition, so driving DIR signal is high level；NTX signal is drawn high, according to ULPI agreement, the data to be transmitted is started to be put into
It in bus, and is sent in next clock cycle, continues to that data are sent completely position；After data are sent completely, STP is protected
The signal of the last a data of the data of a cycle transmission is held, each signal restores the level when transmission of no data.
Likewise, continuing two queried STP signal when we need to send data to end of link from ULPI transceiver end
After not jumping after a clock cycle, judge that no data transmission is carrying out；Holding signal DIR is low level, represents end of link
Data are transmitted to ULPI transceiver end；Then NTX signal period property is drawn high, and the data that will be transmitted are put on data/address bus,
Next clock cycle is waited to send；After equal pending datas are transmitted, signal STP maintains the last one clock cycle to send
The level of last signal of the data gone out drags down signal DIR and signal NTX, the data transfer ends.Flow chart can refer to
Fig. 2.
After the signal that the data temporary storage module 10 is responsible for reception FPGA signal processing and Coordination module 12 transmits, association
DDR3SDRAM memory 4 is adjusted, there are in DDR3SDRAM memory 4 for the data that needs are stored；And when needing to forward
It reads out again, handles and be sent to data forwarding module 11 for FPGA signal processing and Coordination module 12.For DDR3SDRAM
The control and configuration of 4 chip of memory can generate DDR3SDRAM storage by the Core Generator that Xilinx is provided
The MCB IP CORE of device 4, then partial code parameter therein is modified to realize.
The data forwarding module 11 is responsible for after receiving the signal from FPGA signal processing and Coordination module 12, rear
Terminal circuit 5 is ready in the case where receiving data, and terminal circuit 5 forwards the data of primitive form backward.In view of back-end circuit 5
The difference of interface either communication protocol, common interface may be USB either gigabit Ethernet, if not requiring transmission speed
Degree can also use UART interface etc., and there is no the communications that insertion one can be adapted to various agreements or port by the present invention
IP kernel and circuit temporarily consider to send data to the back-end using gigabit Ethernet, but this module is not limited in gigabit ether
Net does transmission interface.
The FPGA signal processing and Coordination module 12 are the Verilog program operated on fpga chip, are responsible for judgement
Data flow replicates valid data, coordination and controls the work of other modules.In the present invention, FPGA signal processing and coordination
Module 12 will realize detailed functions below:
1. coordinating clock, because of USB transceiver module I 2, the work clock of USB transceiver module II 3 and fpga chip 1
Work clock it is different, it is contemplated that monitor and the data correctness of acquisition, when the work of FPGA signal processing and Coordination module 12
If clock frequency at least USB transceiver module I 2,2 times of II 3 working clock frequency of USB transceiver module；And in order to guarantee
The work clock of fpga chip 1 with the work clock of USB transceiver module I 2, USB transceiver module II 3 be it is synchronous, i.e.,
FPGA signal processing and the work clock of Coordination module 12 jump 2 times, USB transceiver module I 2, USB transceiver module II 3
Work clock jumps 1 time；Meanwhile also to coordinate the work clock of fpga chip 1 Yu DDR3SDRAM memory 4；
2. duplication sends data, according to the judgement in direction and valid data, the data that will be flowed into from USB transceiver module I 2
In valid data replicated, in two parts of data, portion be sent to USB transceiver module II 3 and complete to the data of PC send out
It send, it is temporary that another data is sent to DDR3SDRAM memory 4；
3. the flow direction of data is judged, because the fixed USB transceiver module II 3 of the present invention connects PC, from judging data
Flow direction in terms of can directly save the duplication of the data received to USB transceiver module II 3, to reduce the number of duplication
According to mitigate chip operating pressure；
4. judge valid data, the data that USB transceiver module II 3 receives also be not all it is useful, of the invention
In data reproduction process, the signals such as the shaking hands of USB interface, device enumeration do not need duplication, realize the foundation of communication,
So according to the judgement of the type to data, so that it may remove to the signal for establishing communication；
5. replicating effective Data Concurrent gives temporary storage module, as mentioned above, after judging valid data, by former data
While being sent to USB transceiver module II 3, data are replicated portion and are sent to DDR3SDRAM memory 4 and are kept in；
6. the reading data of DDR3SDRAM memory 4 is come out and is sent to data under the premise of back-end circuit is ready
Forwarding module 11 is completed the transmission of initial data terminal circuit 5 backward from DDR3SDRAM memory 4.
The back-end circuit 5 is the data processing electricity being connected on fpga chip 1 being connected with data forwarding module 11
Road handles the present invention from the data that USB line road is monitored.The methods of processing are simultaneously not fixed, according to reality
Demand to data is handled in real time.Such as certain image datas that carry out real-time display, then back-end circuit can
To be designed as Real-time image display circuit；Or it is used to lucky algorithm and image data is handled, it is necessary to rear end electricity
There is the module etc. that lucky algorithm can be carried out to image in road.Interface used in back-end circuit is fitted in order to expand simultaneously
It answering, the present invention is not distinctly claimed communication protocol used in back-end circuit, it can be cable interface, USB interface etc., according to
Actual use situation is being arranged in pairs or groups.
The beneficial effects of the present invention are:
1, in the case where PC inconvenient to use or other signal analyzer devices, it is to be understood that on a usb bus
What data are specifically, and to carry out analyzing to its data and when temporary forwarding, so that it may by the solution of the present invention.
2, the present invention does transfer by FPGA, can not be by PC machine, after accessing USB transmission line, on usb bus
Data are unpacked, are stored, are forwarded, and realization is monitored and acquired in real time without intrusive usb data from data plane；
3, the present invention can be sent to temporary data in other equipment by back-end circuit and further be divided
Analysis and use；
4, the present invention other than equipment is easy to use, and it is lower than the equipment cost of the similar functions such as protocol analyzer very
It is more；After being designed to a mature equipment, it can even more increase portability and practicability；
5, present system has a variety of advantages such as portability, low cost, versatility be good, can send out under appropriate circumstances
Wave effect more better than PC machine.
Detailed description of the invention
Fig. 1 is the principle of the present invention block diagram；
Fig. 2 is the flow chart of the data transmission between ULPI transceiver end and end of link of the invention；Wherein, data are transmitted
It is divided into and is transmitted from end of link to ULPI transceiver end and transmit two kinds of situations from ULPI transceiver end to end of link, according to transmission side
To difference, the state of signal DIR is different.
Each label in Fig. 1: 1-FPGA chip, 2-USB transceiver module I, 3-USB transceiver module II, 4-DDR3SDRAM
Memory, 5- back-end circuit, 6-ULPI data transmit-receive module I, 7-ULPI data transmit-receive module II, 8-ULPI control module I, 9-
ULPI control module II, 10- data temporary storage module, 11- data forwarding module, 12-FPGA signal processing and Coordination module.
Specific embodiment
In the following with reference to the drawings and specific embodiments, the invention will be further described.
Embodiment 1: as shown in Figs. 1-2, a kind of real-time monitoring system of usb data based on FPGA, including fpga chip 1,
USB transceiver module I 2, USB transceiver module II 3, DDR3SDRAM memory 4；
The fpga chip 1 includes: ULPI data transmit-receive module I 6, ULPI data transmit-receive module II 7, ULPI control module
I 8, ULPI control module II 9, data temporary storage module 10 and FPGA signal processing and Coordination module 12；
The fpga chip 1 connects USB transceiver module I 2, USB transceiver module II 3, DDR3SDRAM memory 4；
USB transceiver module I 2, USB transceiver module II 3 are connected to fpga chip 1, USB transceiver module I by different I/O mouths
2 pass through ULPI data transmit-receive module I 6, ULPI control module I 8 and FPGA signal processing and Coordination module 12；FPGA signal processing
It is connect by data temporary storage module 10 with DDR3SDRAM memory 4 with Coordination module 12, FPGA signal processing and Coordination module 12
It is connect by ULPI data transmit-receive module II 7, ULPI control module II 9 with USB transceiver module II 3.
The fpga chip 1 further includes data forwarding module 11, back-end circuit 5；Data forwarding module 11 and back-end circuit 5
Connection, FPGA signal processing and Coordination module 12 are connect with data forwarding module 11 to be read out of DDR3SDRAM memory 4 for handle
The data taken are sent to back-end circuit 5 by data forwarding module 11, and back-end circuit 5 is determined by its communication protocol or its interface
The type and communication protocol classification of connector.
The back-end circuit 5 can either carry out the mould of lucky algorithm process using Real-time image display circuit to image
Block.
After the USB transceiver module I 2 receives data, the data letter for meeting ULPI agreement is translated by USB3320 chip
Number, cooperate with ULPI control module I 8 and ULPI data transmit-receive module I 6 to be sent to FPGA signal processing and Coordination module 12, ULPI
I 6 signals revivifications received of data transmit-receive module at original signal, then by FPGA signal processing and Coordination module 12 duplication and
The data portion of forwarding, duplication is stored into DDR3SDRAM memory 4 by data temporary storage module 10, another passes through again
ULPI data transmit-receive module II 7 translates into ULPI signal and is sent to USB transceiver module II 3, is then forwarded to PC later.
Mode of the USB transceiver module I 2 when the equipment with both ends is connect is by ULPI control module I 8 can
Choosing；When the equipment that USB transceiver module I 2 connects is host equipment, USB is received by ULPI control module I 8
The work of device module I 2 is sent out to be arranged under equipment mode；When the equipment that USB transceiver module I 2 connects is the USB device of standard
When, USB transceiver module I 2 works under OTG mode, i.e. 2 hosted of USB transceiver module I.
The data that the USB transceiver module I 2 receives by the FPGA signal processing in fpga chip 1 and coordinate mould
Block 12 preferentially guarantees that data can be then forwarded to PC machine, first by passing to USB transceiver module II 3 after fpga chip 1 with reduction
The data transmission link of USB；Next is only the temporary and forwarding to data are listened to；The flow direction of usb data judges that data are real-time
The work that monitoring and unloading and usb communication are established is completed by FPGA signal processing and Coordination module 12.
Core chips used in the fpga chip 1 is the XC6SLX16- of Xilinx company Spartan6 series
FTG256 chip；DDR3SDRAM memory is the MT41J128M16HA-15E 256MB DDR3 storage chip of magnesium light company；Institute
It is identical to state USB transceiver module I 2, II 3 structure of USB transceiver module, wherein including USB3320 chip and USB interface.
A kind of real-time monitor method of usb data based on FPGA, USB transceiver module I 2, which is connected to, can be read equipment, root
According to the type that equipment can be read, USB transceiver module I 2 is set as to base by ULPI control module I 8 by different mode
The communication on both sides is realized in usb protocol；
According to USB communication protocol, after USB transceiver module I 2 receives the data transmitted, by USB transceiver module I 2
The data packet of USB is carried out to translate into the signal for meeting ULPI agreement, then is sent in fpga chip 1 by ULPI agreement
FPGA signal processing and Coordination module 12 are kept in and are forwarded；The data portion of duplication is stored by data temporary storage module 10
In DDR3SDRAM memory 4, another passes through ULPI data transmit-receive module II 7 again and translates into ULPI signal and be sent to USB receipts
Device module II 3 is sent out, is then forwarded to PC later, to restore the data transmission link of USB, temporary data pass through data forwarding mould again
Block 11 is sent to back-end circuit 5.
The equipment that can be read includes USB flash disk or PC；It is USB flash disk when equipment can be read, is received and dispatched according to USB communication protocol and USB
USB transceiver module I 2 is set as host mode by ULPI control module I 8 by the function of device module I 2, and equipment can be read
USB flash disk is used as from equipment and works, and the communication on both sides is realized based on usb protocol；
When it is PC that equipment, which can be read, according to the function of USB communication protocol and USB transceiver module I 2, controlled by ULPI
USB transceiver module I 2 is set as equipment mode by module I 8 processed, and equipment PC can be read as host work, is assisted based on USB
View realizes the communication on both sides.
Further, in this example, the connection type of circuit and peripheral equipment is as follows: back-end circuit 5 is processing in real time
Display circuit, USB transceiver module I 2 are connected to a USB flash disk, and USB transceiver module II 3 is connected to PC.The function of realization is:
After USB flash disk is connected to USB transceiver module I 2, the PC being connected in USB transceiver module II 3 can be enable to read on USB flash disk
Image data, while the real-time processing display circuit of rear end can complete in real time to the processing of image after, show to biography
The result images after the completion of image procossing in defeated.
USB transceiver module II 3, which is done from equipment, is connected to PC, works under equipment mode, and USB transceiver module I 2 connects
It connecing USB flash disk, works under host mode, i.e., USB transceiver module II 3 is connect using the A type interface of USB transceiver module with PC,
USB transceiver module I 2 is connect using the Micro Type B interface of USB transceiver module with USB flash disk.As corresponding to USB flash disk plug
Interface is A type interface, so needing adapter to complete this work.
According to the communication protocol of USB 2.0, USB transceiver module I 2 and USB flash disk establish communication connection, USB transceiver module
II 3 and PC establishes communication connection, and completes the determination of device enumeration and transmission speed.Start data transmission, the request of data of PC
Data flow into FPGA signal processing and Coordination module 12 via ULPI data transmit-receive module II 7 from USB transceiver module II 3,
The order of request data is forwarded directly to USB transceiver module I 2 by FPGA signal processing and Coordination module 12, then is passed through USB and received
Hair device module I 2 is transferred to after USB flash disk, the request of USB flash disk response data, starts to send the image data in USB flash disk to fpga chip 1.It returns
The data returned first reach USB transceiver module I 2, then reach fpga chip 1.FPGA signal processing and Coordination module 12 judge
Image data is to carry out the duplication of data after the valid data that USB transceiver module I 2 flows into, while former data to USB
Transceiver module II 3 is sent, then is sent from USB transceiver module II 3 to PC, and the data for completing former usb bus transmit work.It is multiple
The data of system send to DDR3SDRAM memory 4 and complete to keep in.
After rear end handles display circuit access in real time, according to the request of data of back-end circuit 5, FPGA signal processing and coordination
Module 12 transfers the raw image data kept in DDR3SDRAM memory 4, and it is real-time to be sent to rear end from data forwarding module 11
Display circuit is handled, and completes processing in real time and display.
In this invention, image data is in the principle by data transmission between ULPI transceiver end and fpga chip 1
It is as follows:
ULPI transceiver end, ULPI data transmit-receive are belonged to for USB transceiver module I 2 and USB transceiver module II 3
Module I 6, ULPI control module I 8 also belong to end of link I, and ULPI data transmit-receive module II 7, ULPI control module II 9 belong to chain
Terminal II.
After establishing communication connection, USB flash disk receives request of data, starts to send data to USB transceiver module I 2, then
Under the work of USB3320, the data for being converted to ULPI agreement are sent to fpga chip 1.USB transceiver module is inquired first
STP signal two of I 2 and ULPI control module I 8 more than the period maintain the original state, and determine that no data are transmitted in bus, open
Begin transmission data.ULPI control module I 8 has detected that data are sent out from ULPI transceiver end USB transceiver module I 2 to end of link I
It send, draws high DIR signal, the data transmitted from 8 position datawires are returned according to protocol assembly by ULPI data transmit-receive module I 6
Raw image data.Etc. after the data transfer ends, STP keeps last level of image data, USB flash disk to fpga chip 1
Be transmitted.It is transmitted from fpga chip 1 to the data of PC, detects and have data to be transferred to ULPI transceiver from end of link II
Hold USB transceiver module II 3, inquiry bus do not have it is occupied after, first drag down or keep DIR signal for low level, original graph
As data are put into 8 bit data bus, according to clock cycle and NXT signal, it is sent to USB3320 chip.Again by USB3320 core
Piece completes the data of checking the mark that usb protocol is translated into from ULPI protocol data, is sent to PC.The signal of entire data transmission stream journey is sentenced
It is disconnected to finish.
Embodiment 2: as shown in Figs. 1-2, a kind of real-time monitoring system of usb data based on FPGA and method, including this reality
It is same as Example 1 to apply example, wherein further:
In this example, back-end circuit 5 is the lucky imaging system in real time of the astronomy based on FPGA, USB transceiver module I 2
It is connected to a CCD camera.The function of realization is that the PC being connected in USB transceiver module II 3 can be enable to receive
The astronomical image of CCD camera shooting, while the real-time processing circuit of rear end can be in real time to the past image of transmission with luckily
Imaging algorithm is pocessed, and finally obtains result.
USB transceiver module II 3, which is done from equipment, is connected to PC, works under equipment mode, i.e. USB transceiver module II
3 connect PC using A type interface；USB transceiver module I 2 connects CCD camera, works under host mode, uses USB transceiver
The Micro Type B interface of 2 module of module I connects.
The data request data of PC flows into fpga chip 1 from USB transceiver module II 3, then passes through USB transceiver module I 2
It is transferred to after CCD camera, the data of return first reach USB transceiver module I 2.From USB transceiver module I 2
USB3320 chip is sent to ULPI data transmit-receive module I 6, and after data complete packing and unpacking, fpga chip 1 receives astronomy
After image data, via data temporary storage module 10, keep in DDR3SDRAM memory 4；Meanwhile image data is received by USB
Hair device module II 3 is sending back PC machine.This embodiment, which integrates, can be realized before not transmitting generation interference to former data
It puts, lucky imaging algorithm processing in real time is realized to astronomical image, and can be with the high resolution graphics of real-time display astronomy target
Picture.ULPI control module I 8 and ULPI data transmit-receive module I 6, ULPI control module II 9 and II 7 points of ULPI data transmit-receive module
The data transmit-receive of other coordinated control USB transceiver module I 2 and USB transceiver module II 3；FPGA signal processing and Coordination module
12 processing data duplications and forwarding.
After the real-time lucky imaging system access of astronomy of the rear end based on FPGA, according to the request of data of back-end circuit, FPGA
Signal processing and Coordination module 12 transfer the raw image data kept in DDR3SDRAM memory 4, from data forwarding circuit 11
It is sent to astronomy of the rear end based on FPGA lucky imaging system in real time, completes the high-definition picture to astronomical target in the system
It is real-time processing after, pass through display equipment complete display.
In this invention, astronomical high-definition picture is passed by data between ULPI transceiver end and fpga chip 1
Defeated principle is as follows:
ULPI transceiver end, ULPI data transmit-receive are belonged to for USB transceiver module I 2 and USB transceiver module II 3
Module I 6, ULPI control module I 8 also belong to end of link I, and ULPI data transmit-receive module II 7, ULPI control module II 9 belong to chain
Terminal II.
After establishing communication connection, CCD camera receives request of data, starts to send data to USB transceiver module I 2,
Then under the work of the USB3320 in USB transceiver module I 2, the data for being converted to ULPI agreement are sent to fpga chip 1.
STP signal two for inquiring USB transceiver module I 2 and ULPI control module I 8 first more than the period maintain the original state, and determine
There is no data to transmit in bus, starts to transmit data.ULPI control module I 8 has detected data from ULPI transceiver end USB
Transceiver module I 2 is sent to end of link I, draws high DIR signal, by ULPI data transmit-receive module I 6 under the transmission of 8 position datawires
The data come return original astronomical high-definition picture according to protocol assembly.Etc. after the data transfer ends, STP keeps image data
Last level, CCD camera is transmitted to fpga chip 1.It is transmitted from fpga chip 1 to the data of PC, detection
To having data to be transferred to ULPI transceiver end USB transceiver module II 3 from end of link II, inquiry bus do not have it is occupied after,
First dragging down or keep DIR signal is low level, astronomy high resolution image data is put into 8 bit data bus, according to clock
Period and NXT signal are sent to the USB3320 chip of USB transceiver module II 3.It completes to assist from ULPI by USB3320 chip again
Data translation is discussed into the differential data of usb protocol, is sent to PC.The signal judgement of entire data transmission stream journey finishes.
Specific embodiments of the present invention are explained in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned realities
Example is applied, it within the knowledge of a person skilled in the art, can also be without departing from the purpose of the present invention
Various changes can be made.
Claims (9)
1. a kind of real-time monitoring system of usb data based on FPGA, it is characterised in that: including fpga chip (1), USB transceiver
Module I (2), USB transceiver module II (3), DDR3SDRAM memory (4)；
The fpga chip (1) includes: ULPI data transmit-receive module I (6), ULPI data transmit-receive module II (7), ULPI control mould
Block I (8), ULPI control module II (9), data temporary storage module (10) and FPGA signal processing and Coordination module (12)；
The fpga chip (1) connects USB transceiver module I (2), USB transceiver module II (3), DDR3SDRAM memory
(4)；USB transceiver module I (2), USB transceiver module II (3) are connected to fpga chip (1), USB by different I/O mouths
Transceiver module I (2) is by ULPI data transmit-receive module I (6), ULPI control module I (8) and FPGA signal processing and coordinates mould
Block (12)；FPGA signal processing and Coordination module (12) are connected by data temporary storage module (10) and DDR3SDRAM memory (4)
It connects, FPGA signal processing and Coordination module (12) pass through ULPI data transmit-receive module II (7), ULPI control module II (9) and USB
Transceiver module II (3) connection.
2. the real-time monitoring system of a kind of usb data based on FPGA according to claim 1, it is characterised in that: described
Fpga chip (1) further includes data forwarding module (11), back-end circuit (5)；Data forwarding module (11) and back-end circuit (5) are even
It connects, FPGA signal processing and Coordination module (12) connect with data forwarding module (11) and be used for handle from DDR3SDRAM memory (4)
The data of interior reading are sent to back-end circuit (5) by data forwarding module (11), back-end circuit (5) by its communication protocol or its
Interface determines the type and communication protocol classification of connector.
3. the real-time monitoring system of a kind of usb data based on FPGA according to claim 2, it is characterised in that: after described
Terminal circuit (5) can either carry out the module of lucky algorithm process using Real-time image display circuit to image.
4. the real-time monitoring system of a kind of usb data based on FPGA according to claim 1, it is characterised in that: the USB
After transceiver module I (2) receives data, the data-signal for meeting ULPI agreement, collaboration ULPI control are translated by USB3320 chip
Module I (8) processed and ULPI data transmit-receive module I (6) are sent to FPGA signal processing and Coordination module (12), ULPI data transmit-receive
Module I (6) at original signal, then by FPGA signal processing and Coordination module (12) replicates the signals revivification received and turn
The data portion of hair, duplication is stored into DDR3SDRAM memory (4) by data temporary storage module (10), another passes through again
ULPI data transmit-receive module II (7) translates into ULPI signal and is sent to USB transceiver module II (3), is then forwarded to PC later.
5. the real-time monitoring system of a kind of usb data based on FPGA according to claim 1, it is characterised in that: the USB
Mode of the transceiver module I (2) when the equipment with both ends is connect is optional by ULPI control module I (8)；Work as USB
When the equipment of transceiver module I (2) connection is host equipment, by ULPI control module I (8) USB transceiver mould
Block I (2) work is arranged under equipment mode；When USB transceiver module I (2) connection equipment be standard USB device when
It waits, USB transceiver module I (2) works under OTG mode, i.e. USB transceiver module I (2) hosted.
6. the real-time monitoring system of a kind of usb data based on FPGA according to claim 1, it is characterised in that: the USB
The data that transceiver module I (2) receives, it is preferential by FPGA signal processing in fpga chip (1) and Coordination module (12)
Guarantee to pass to USB transceiver module II (3) after data can pass through fpga chip (1) first, PC machine is then forwarded to, to restore USB
Data transmission link；Next is only the temporary and forwarding to data are listened to；The flow direction of usb data judges that data are supervised in real time
Listening with the work of unloading and usb communication foundation is completed by FPGA signal processing and Coordination module (12).
7. the real-time monitoring system of a kind of usb data based on FPGA according to claim 1, it is characterised in that: described
Core chips used in fpga chip (1) is the XC6SLX16-FTG256 chip of Xilinx company Spartan6 series；
DDR3SDRAM memory is the MT41J128M16HA-15E 256MB DDR3 storage chip of magnesium light company；The USB transceiver
Module I (2), USB transceiver module II (3) structure are identical, wherein including USB3320 chip and USB interface.
8. a kind of real-time monitor method of usb data based on FPGA, it is characterised in that: USB transceiver module I (2) is connected to can
Equipment is read to be set as not USB transceiver module I (2) by ULPI control module I (8) according to the type that equipment can be read
Same mode is to the communication based on usb protocol realization both sides；
According to USB communication protocol, after USB transceiver module I (2) receives the data transmitted, by USB transceiver module I (2)
The data packet of USB is carried out to translate into the signal for meeting ULPI agreement, then is sent in fpga chip (1) by ULPI agreement
FPGA signal processing and Coordination module (12) are kept in and are forwarded；The data portion of duplication is stored up by data temporary storage module (10)
It is stored in DDR3SDRAM memory (4), another passes through ULPI data transmit-receive module II (7) again, and to translate into ULPI signal concurrent
USB transceiver module II (3) is given, is then forwarded to PC later, to restore the data transmission link of USB, temporary data are led to again
It crosses data forwarding module (11) and is sent to back-end circuit (5).
9. the real-time monitor method of the usb data according to claim 8 based on FPGA, it is characterised in that: described to can be read
Equipment includes USB flash disk or PC；It is USB flash disk when equipment can be read, according to the function of USB communication protocol and USB transceiver module I (2), leads to
It crosses ULPI control module I (8) and USB transceiver module I (2) is set as host mode, and equipment USB flash disk can be read and be used as from equipment
The communication on both sides is realized in work based on usb protocol；
When it is PC that equipment, which can be read, according to the function of USB communication protocol and USB transceiver module I (2), controlled by ULPI
USB transceiver module I (2) is set as equipment mode by module I (8), and equipment PC can be read as host work, is based on USB
The communication on protocol realization both sides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811082851.XA CN109359082B (en) | 2018-09-17 | 2018-09-17 | USB data real-time monitoring system and method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811082851.XA CN109359082B (en) | 2018-09-17 | 2018-09-17 | USB data real-time monitoring system and method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109359082A true CN109359082A (en) | 2019-02-19 |
| CN109359082B CN109359082B (en) | 2022-04-12 |
Family
ID=65350939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811082851.XA Active CN109359082B (en) | 2018-09-17 | 2018-09-17 | USB data real-time monitoring system and method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109359082B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111294520A (en) * | 2020-03-16 | 2020-06-16 | 昆明理工大学 | Real-time lucky imaging method and system based on FPGA |
| CN116647247A (en) * | 2022-11-04 | 2023-08-25 | 成都立思方信息技术有限公司 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990012941A (en) * | 1997-07-31 | 1999-02-25 | 윤종용 | Hot Plug PCC Bus with Single Chip |
| CN201168423Y (en) * | 2008-03-07 | 2008-12-24 | 张赛倩 | Hand-hold games machine with multiple master/slave Ethernet network interfaces |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
| CN104899167A (en) * | 2014-03-05 | 2015-09-09 | 鞍钢股份有限公司 | Portable high-speed data acquisition method based on FPGA |
| US20160232122A1 (en) * | 2013-10-22 | 2016-08-11 | Allgo Embedded Systems Private Limited | Universal serial bus (usb) hub for switching downstream ports between host mode and slave mode |
| CN106021160A (en) * | 2016-05-16 | 2016-10-12 | 江苏沁恒股份有限公司 | USB signal monitoring apparatus and monitoring method |
-
2018
- 2018-09-17 CN CN201811082851.XA patent/CN109359082B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990012941A (en) * | 1997-07-31 | 1999-02-25 | 윤종용 | Hot Plug PCC Bus with Single Chip |
| CN201168423Y (en) * | 2008-03-07 | 2008-12-24 | 张赛倩 | Hand-hold games machine with multiple master/slave Ethernet network interfaces |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
| US20160232122A1 (en) * | 2013-10-22 | 2016-08-11 | Allgo Embedded Systems Private Limited | Universal serial bus (usb) hub for switching downstream ports between host mode and slave mode |
| CN104899167A (en) * | 2014-03-05 | 2015-09-09 | 鞍钢股份有限公司 | Portable high-speed data acquisition method based on FPGA |
| CN106021160A (en) * | 2016-05-16 | 2016-10-12 | 江苏沁恒股份有限公司 | USB signal monitoring apparatus and monitoring method |
Non-Patent Citations (1)
| Title |
|---|
| 吕志超: "基于ULPI协议的USB接口的FPGA实现", 《中国优秀硕士学位论文全文数据库》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111294520A (en) * | 2020-03-16 | 2020-06-16 | 昆明理工大学 | Real-time lucky imaging method and system based on FPGA |
| CN111294520B (en) * | 2020-03-16 | 2024-03-29 | 昆明理工大学 | FPGA-based real-time lucky imaging method and system |
| CN116647247A (en) * | 2022-11-04 | 2023-08-25 | 成都立思方信息技术有限公司 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
| CN116647247B (en) * | 2022-11-04 | 2024-01-26 | 成都立思方信息技术有限公司 | Signal transceiver and signal receiving and transmitting system suitable for flexible connection |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109359082B (en) | 2022-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11193973B2 (en) | Device, system and method to support communication of test, debug or trace information with an external input/output interface | |
| CN104838636B (en) | Ethernet on USB interface with full-duplex differential pair | |
| CN106815157A (en) | A kind of data acquisition module and data collecting system | |
| CN101901202B (en) | Circuit for cross clock domain accessing of AHB bus equipment to APB bus equipment | |
| CN103763549B (en) | A kind of Camera Link interface experiment based on FPGA and development system | |
| CN109558371A (en) | Serial connection between Management Controller and microcontroller | |
| CN209842611U (en) | Multi-communication interface data exchange board card | |
| CN105068955B (en) | A kind of local bus architecture and data interactive method | |
| CN109359082A (en) | A kind of real-time monitoring system of usb data based on FPGA and method | |
| CN105892359A (en) | Multi-DSP parallel processing system and method | |
| CN112256615B (en) | USB conversion interface device | |
| CN109358995A (en) | A kind of multifunctional testing backboard and test method | |
| CN217085747U (en) | Multi-interface communication device based on VPX bus | |
| WO2010060237A1 (en) | Network computer based on fpga | |
| CN106584862A (en) | 3D printing WIFI control system with built-in Web service and control method thereof | |
| CN202110533U (en) | Multi-interface software debugging tool | |
| CN219890472U (en) | Imaging simulation device for satellite load data source | |
| CN219268945U (en) | Image sensor evaluating switching device and evaluating system | |
| CN209460753U (en) | A kind of usb data real-time monitoring apparatus based on FPGA | |
| CN209964072U (en) | High-speed data switching card device based on FPGA | |
| CN206321974U (en) | CAN circuit control device based on CPLD | |
| EP4318253A1 (en) | Method and apparatus for extending i3c capability across multiple platforms and devices over usb-c connection | |
| CN115730541A (en) | Multifunctional verification and demonstration device for packaged chip | |
| CN105718411A (en) | Instrument-module universal interface assembly based on AXIe | |
| CN205680088U (en) | The transmitting device of clock-domain crossing data and asynchronous circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |