CN209460753U - A kind of usb data real-time monitoring apparatus based on FPGA - Google Patents
A kind of usb data real-time monitoring apparatus based on FPGA Download PDFInfo
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- CN209460753U CN209460753U CN201821518757.XU CN201821518757U CN209460753U CN 209460753 U CN209460753 U CN 209460753U CN 201821518757 U CN201821518757 U CN 201821518757U CN 209460753 U CN209460753 U CN 209460753U
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 16
- 238000004891 communication Methods 0.000 claims abstract description 11
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 238000000605 extraction Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
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- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
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- 238000012545 processing Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
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Abstract
The utility model relates to a kind of usb data real-time monitoring apparatus based on FPGA, belongs to electronics and field of communication technology.The utility model includes fpga chip, USB transceiver module I, USB transceiver module II, DDR3SDRAM memory, back-end circuit；The USB transceiver module I, II structure of USB transceiver module are identical, wherein including USB3320 chip and USB interface.The utility model can unpack the data on usb bus, stored, be forwarded not passing through PC machine after accessing USB transmission line, realize from monitoring in real time in data plane without intrusive usb data.This utility model system has a variety of advantages such as portability, low cost, versatility be good, can play effect more better than PC machine under appropriate circumstances.
Description
Technical field
The utility model relates to a kind of usb data real-time monitoring apparatus based on FPGA, belongs to electronics and the communication technology is led
Domain.
Background technique
FPGA (Field-Programmable Gate Array), full name is field programmable gate array.USB is one
External bus standard, for being connected and communicate with for specification computer and external equipment.It is the interfacing applied in the field PC.USB
The plug and play and warm connection function of interface holding equipment.Combine in companies such as nineteen ninety-five Microsoft, Compaq and IBM and makes
A kind of fixed newer PC serial communication protocol.USB device is fairly simple, facilitates interaction, less expensive, and as one
Kind serial ports connection, may be implemented multiple be used in combination.
It is all point-to-point transmission but in the transmission process of USB.Although now with Portable mobile computer,
It can eaily carry and use at any time.
But the desired working environment of portable notebook computer be not well positioned to meet it is some than relatively severe condition,
Either requirement, which does not need excessive investment, can complete the monitoring work to usb bus accordingly.Such requirement just excludes
We introduce the possibility of the instruments such as logic analyser.Just there is this usb data based on FPGA to supervise in real time in this case
Listen the demand of Acquisition Circuit.
Summary of the invention
Technical problem to be solved by the utility model is: the utility model does transfer by FPGA, nothing is macroscopically being realized
Intrusive usb data is monitored and is acquired in real time, and equipment is easy to use, at low cost, easy to carry, practical.
Technical solutions of the utility model are: a kind of usb data real-time monitoring apparatus based on FPGA, including fpga chip 1,
USB transceiver module I 2, USB transceiver module II 3, DDR3SDRAM memory 4, back-end circuit 5；The USB transceiver module
I 2, II 3 structure of USB transceiver module is identical, wherein including USB3320 chip and USB interface；
The fpga chip 1 respectively with the USB3320 chip phase in USB transceiver module I 2, USB transceiver module II 3
Connection, the signal flow of the signal wire NTX and DIR of USB3320 chip are to flow to fpga chip 1, signal wire from USB3320 chip
The flow direction of STP flows to USB3320 chip by fpga chip 1, and signal wire CLK is two-way signaling, and DATA is 8 position datawires；
DDR3SDRAM memory 4 is connected to the data temporary storage module of fpga chip 1；The data forwarding of back-end circuit 5 and fpga chip 1
Module is attached by other ports I/O of fpga chip 1；USB transceiver module I 2 is external to can be read equipment, USB transceiver
The external PC of module II 3；
Core chips used in the fpga chip 1 is the XC6SLX16- of Xilinx company Spartan6 series
FTG256 chip；DDR3SDRAM memory 4 is the MT41J128M16HA-15E 256MB DDR3 storage chip of magnesium light company.
The back-end circuit 5 can either carry out the mould of lucky algorithm process using Real-time image display circuit to image
Block.
The USB transceiver module I 2 is used to receive the external data that equipment is sent that can be read and then passes through it
USB3320 chip, which is translated into, to be met the data-signal of ULPI agreement and is transmitted to fpga chip 1 again；
The fpga chip 1 receives the data that USB transceiver module I 2 is sent and then replicates again temporary by data
Module storage is sent to back-end circuit 5 into DDR3SDRAM memory 4 and through data forwarding module unloading, and for USB
The data that transceiver module I 2 is sent are transmitted to USB transceiver module II 3；
The data temporary storage module is for data cached；
The DDR3SDRAM memory 4 is used to store the data of the duplication of fpga chip 1；
The back-end circuit 5 is used to receive the data after unloading and show the image procossing in either later period；
The USB transceiver module II 3 is used to receive the Data Concurrent that fpga chip 1 transmits to give and be attached thereto
PC。
The external equipment that can be read of the USB transceiver module I 2 uses USB flash disk or PC；It is USB flash disk when equipment can be read, passes through
USB transceiver module I 2 is set as host mode by fpga chip 1, and equipment USB flash disk can be read and be used as from equipment work, is based on
The communication on usb protocol realization both sides；
When it is PC that equipment, which can be read, USB transceiver module I 2 is set as by fpga chip 1 by equipment mode, and can
Equipment PC is read as host work, the communication on both sides is realized based on usb protocol.
It further include socket interface and necessary peripheral circuit；The necessary peripheral circuit includes power circuit, JTAG electricity
Road, two 32 × 2P, 2.54mm spacing row's needle interface；Two row's needle interfaces are coupled with the Bank0 and Bank1 of fpga chip
I/O pin, the extraction of Lai Shixian pin.
The USB transceiver module I 2 and the connection type of fpga chip are:
The entitled VBUS of the pin 22 of the USB3320 chip of USB transceiver module I 2, meets external signal USBA_VBUS；
The entitled DM of pin 19, meets external signal USBA_DM；The entitled DP of pin 18, meets external signal USBA_DP；Pin 23
Entitled ID, meet external signal USBA_ID；The entitled NXT of pin 2, meets external signal USBA_NTX；The title of pin 31
For DIR, external signal USBA_DIR is met；The entitled STP of pin 29, meets external signal USBA_STP；Pin 1 it is entitled
CLKOUT meets external signal USBA_CK；The entitled D0 of pin 3, meets external signal USBA_D0；The entitled D1 of pin 4, connects
External signal USBA_D1；The entitled D2 of pin 5, meets external signal USBA_D2；The entitled D3 of pin 6, connects external signal
USBA_D3；The entitled D4 of pin 7, meets external signal USBA_D4；The entitled D5 of pin 9, meets external signal USBA_D5；
The entitled D6 of pin 10, meets external signal USBA_D6；The entitled D7 of pin 13, meets external signal USBA_D7；
USB transceiver module II 3 and the pin connection type and USB transceiver module I 2 of fpga chip are completely the same, are
Difference outer signals, it is prefix that all signal name, which is changed to USBB_,.
The working principle of the utility model is:
The USB transceiver module I 2 receives the external data that equipment is sent that can be read and then passes through its USB3320
Chip, which is translated into, to be met the data-signal of ULPI agreement and is transmitted to fpga chip 1 again；Fpga chip 1 receives USB transceiver module I
Then 2 data sent replicate again is stored into DDR3SDRAM memory 4 by data temporary storage module and passes through data forwarding
Module unloading is sent to back-end circuit 5, and the data that USB transceiver module I 2 is sent are transmitted to USB transceiver module II 3；
The data cached DDR3SDRAM memory 4 that is then forwarded to of data temporary storage module stores the data that fpga chip 1 replicates；Back-end circuit 5
Receive unloading after data and show either the later period image procossing；USB transceiver module II 3 receives fpga chip 1
The Data Concurrent transmitted gives the PC being attached thereto.
USB transceiver module I 2, USB transceiver module II 3 are by respective USB interface, with extraneous equipment or master
Machine is communicated；DDR3SDRAM memory 4 is controlled by the data temporary storage module of fpga chip, and is realized and fpga chip 1
Data exchange and data it is temporary；Back-end circuit 5 is then connected to the idle interface of fpga chip, and fpga chip passes through the free time
The data to be forwarded are issued back-end circuit 5 by interface, back-end circuit 5 can be to data processing chip or circuit,
It can be display circuit etc..
The core chips of the fpga chip 1 be with a piece of XC6SLX16-FTG256 chip, DDR3 storage circuit of arranging in pairs or groups,
Development board based on socket interface and necessary peripheral circuit.Using fpga chip as core, storage, the data for completing DDR3 are temporary
Forwarding and backward the age South Road DAU send the function of temporal data.Peripheral circuit includes power circuit, jtag circuit, 2 32 ×
The circuits such as row's needle interface of 2P, 2.54mm spacing.The I/O of Bank0 and Bank1 that two row's needle interfaces are coupled with FPGA draw
Foot, the extraction of Lai Shixian pin.It include: ULPI data transmit-receive module, data temporary storage module, data forwarding mould in fpga chip
Block.There are two ULPI data transmit-receive modules, is responsible for the number for receiving USB transceiver module I 2, USB transceiver module II 3 is sent
The data in fpga chip 1 are sent according to or to USB transceiver module I 2, USB transceiver module II 3；Data temporary storage module is negative
Data after duty replicates fpga chip 1 keep in DDR3SDRAM memory 4；Data forwarding module is responsible for after forwarding data to
Terminal circuit 5；
The USB transceiver module I 2, USB transceiver module II 3 chief component be a piece of USB3320 chip and
USB interface, then mix suitable peripheral circuit.Signal wire NTX, DIR, STP, CLKOUT and data line D0 of chip USB3320
~D7 is connected by ULPI agreement with fpga chip.REFCLK and XO mouthfuls of connection outer clock circuits of signal wire provide frequency
Rate is the clock signal of 25MHz.For whole system, since usage quantity is chip USB3320 in the present invention
It is two, a piece of as the slave equipment communicated with PC machine, it is a piece of as the host communicated with other equipment.When as host work
USB interface and as equipment work USB interface signal wire require be different, for ease of distinguish two kinds of working conditions
Interface, USB transceiver module I 2, USB transceiver module II 3 respectively there are two different model USB interface.One model
Micro USB type mother's mouth, socket when being as host；Another A type mother's mouth, as the socket from equipment mode.Wherein
The ID of Micro USB socket terminates the ID pin 23 into USB3320.
The DDR3SDRAM memory 4 is a piece of MT41J128M16HA-15E 256MB DDR3 storage chip.Its work
Clock signal is provided by fpga chip 1.In addition to ensureing that chip works normally, other pins are connected to the total interface of DDR3 chip
On corresponding fpga chip interface.
In Fig. 1, completed by fpga chip 1 (fpga chip XC6SLX16-FTG256) to USB transceiver module I 2, USB
Data receiver, duplication and the forwarding of transceiver module II 3.Respective the 12 of USB transceiver module I 2, USB transceiver module II 3
A ULPI protocol port is all connected to the pin of the Bank0 and Bank1 of fpga chip 1, wherein NTX, DIR, STP and CLK are FPGA
Control and feedback signal line between USB3320, DATA are the data lines that a bit wide is 8.4 (core of DDR3SDRAM memory
Piece is MT41J128M16HA-15E) according to Datasheet, it is connected on fpga chip 1, is mentioned by data temporary storage module (Bank3)
For data exchange.Back-end circuit 5 is connected to other vacant ports of fpga chip, by data forwarding module to realize data
Forwarding.
USB3320 chip in USB transceiver module I 2, USB transceiver module II 3 is electric with the connection of fpga chip respectively
Road as shown in Fig. 2, the pin that every piece of USB3320 chip and fpga chip have data exchange is 13；It is connected with USB jack
Pin have 4.Other pins are all the pins for guaranteeing chip normal operation.Specific connection is as follows:
The entitled VBUS of the pin 22 of the USB3320 chip of USB transceiver module I 2, meets external signal USBA_VBUS；
The entitled DM of pin 19, meets external signal USBA_DM；The entitled DP of pin 18, meets external signal USBA_DP；Pin 23
Entitled ID, meet external signal USBA_ID；
The entitled NXT of pin 2, meets external signal USBA_NTX；The entitled DIR of pin 31, meets external signal USBA_
DIR；The entitled STP of pin 29, meets external signal USBA_STP；The entitled CLKOUT of pin 1, meets external signal USBA_
CK；The entitled D0 of pin 3, meets external signal USBA_D0；The entitled D1 of pin 4, meets external signal USBA_D1；Pin 5
Entitled D2, meet external signal USBA_D2；The entitled D3 of pin 6, meets external signal USBA_D3；Pin 7 it is entitled
D4 meets external signal USBA_D4；The entitled D5 of pin 9, meets external signal USBA_D5；The entitled D6 of pin 10 connects outer
Portion signal USBA_D6；The entitled D7 of pin 13, meets external signal USBA_D7.
The pin connection type and USB transceiver module I 2 of USB transceiver module II 3 are completely the same, in order to distinguish the external world
Signal, it is prefix that all signal names, which are changed to USBB_,.
Because fpga chip needs to connect two pieces of USB transceiver modules, and in order to reduce the pin to be drawn, institute to the greatest extent
It is connect on Fig. 3-two 32 × 2 sockets shown in Fig. 4 respectively with two USB transceiver modules.By figure it can also be seen that draw
ULPI agreement pin is connected to the title of the pin of FPGA.
Two common output ports of fpga chip are directly connected with two pieces of USB3320 respectively, when to guarantee to communicate
Clock signal is consistent；When communication, it is necessary to guarantee that the clock signal on both sides is consistent.USB transceiver can be passed through
Resetting (Reset) signal of module come make they work under the same clock signal.In addition, in order to reduce data line in high frequency
The power pins of interference under environment, each chip will add shunt capacitance.
In Fig. 5, the title for each pin that chip MT41J128M16HA-15E is connect with fpga chip has been marked out.And
And contain some peripheral circuits.Wherein, it can be correctly arranged to guarantee DDR3 chip in use, be needed DDR_
Tri- interfaces of CKE, DDR_RESETN and DDR_ODT all pull down resistors of one 4.7K Ω of parallel connection are to ground, and DDR_CS one in parallel
The pull down resistor of 100 Ω to ground.
The beneficial effects of the utility model are:
The utility model can solve the data on usb bus after accessing USB transmission line not passing through PC machine
Packet, storage, forwarding, are realized from monitoring in real time in data plane without intrusive usb data.This utility model system tool
There are a variety of advantages such as portability, low cost, versatility be good, effect more better than PC machine can be played under appropriate circumstances.
Detailed description of the invention
Fig. 1 is the utility model schematic block circuit diagram；
Fig. 2 is the utility model USB3320 chip and peripheral circuit diagram；
Fig. 3 is the schematic diagram that the utility model USB transceiver module I is connected to 32 × 2 jack of FPGA core core；
Fig. 4 is the schematic diagram that the utility model USB transceiver module II is connected to 32 × 2 jack of FPGA core core；
Fig. 5 is that the DDR3SDRAM memory of the utility model is connected to the pin name and peripheral circuit diagram of fpga chip.
Each label in Fig. 1: 1-FPGA chip, 2-USB transceiver module I, 3-USB transceiver module II, 4-DDR3SDRAM
Memory, 5- back-end circuit.
Specific embodiment
Utility model will be further explained below with reference to the attached drawings and specific embodiments.
Embodiment 1: as shown in Figs. 1-5, a kind of usb data real-time monitoring apparatus based on FPGA, including fpga chip 1,
USB transceiver module I 2, USB transceiver module II 3, DDR3SDRAM memory 4, back-end circuit 5；The USB transceiver module
I 2, II 3 structure of USB transceiver module is identical, wherein including USB3320 chip and USB interface；
The fpga chip 1 respectively with the USB3320 chip phase in USB transceiver module I 2, USB transceiver module II 3
Connection, the signal flow of the signal wire NTX and DIR of USB3320 chip are to flow to fpga chip 1, signal wire from USB3320 chip
The flow direction of STP flows to USB3320 chip by fpga chip 1, and signal wire CLK is two-way signaling, and DATA is 8 position datawires；
DDR3SDRAM memory 4 is connected to the data temporary storage module of fpga chip 1；The data forwarding of back-end circuit 5 and fpga chip 1
Module is attached by other ports I/O of fpga chip 1；USB transceiver module I 2 is external to can be read equipment, USB transceiver
The external PC of module II 3；
Core chips used in the fpga chip 1 is the XC6SLX16- of Xilinx company Spartan6 series
FTG256 chip；DDR3SDRAM memory 4 is the MT41J128M16HA-15E 256MB DDR3 storage chip of magnesium light company.
The back-end circuit 5 can either carry out the mould of lucky algorithm process using Real-time image display circuit to image
Block.
The USB transceiver module I 2 is used to receive the external data that equipment is sent that can be read and then passes through it
USB3320 chip, which is translated into, to be met the data-signal of ULPI agreement and is transmitted to fpga chip 1 again；
The fpga chip 1 receives the data that USB transceiver module I 2 is sent and then replicates again temporary by data
Module storage is sent to back-end circuit 5 into DDR3SDRAM memory 4 and through data forwarding module unloading, and for USB
The data that transceiver module I 2 is sent are transmitted to USB transceiver module II 3；
The data temporary storage module is for data cached；
The DDR3SDRAM memory 4 is used to store the data of the duplication of fpga chip 1；
The back-end circuit 5 is used to receive the data after unloading and show the image procossing in either later period；
The USB transceiver module II 3 is used to receive the Data Concurrent that fpga chip 1 transmits to give and be attached thereto
PC。
The external equipment that can be read of the USB transceiver module I 2 uses USB flash disk or PC；It is USB flash disk when equipment can be read, passes through
USB transceiver module I 2 is set as host mode by fpga chip 1, and equipment USB flash disk can be read and be used as from equipment work, is based on
The communication on usb protocol realization both sides；
When it is PC that equipment, which can be read, USB transceiver module I 2 is set as by fpga chip 1 by equipment mode, and can
Equipment PC is read as host work, the communication on both sides is realized based on usb protocol.
It further include socket interface and necessary peripheral circuit；The necessary peripheral circuit includes power circuit, JTAG electricity
Road, two 32 × 2P, 2.54mm spacing row's needle interface；Two row's needle interfaces are coupled with the Bank0 and Bank1 of fpga chip
I/O pin, the extraction of Lai Shixian pin.
The USB transceiver module I 2 and the connection type of fpga chip are:
The entitled VBUS of the pin 22 of the USB3320 chip of USB transceiver module I 2, meets external signal USBA_VBUS；
The entitled DM of pin 19, meets external signal USBA_DM；The entitled DP of pin 18, meets external signal USBA_DP；Pin 23
Entitled ID, meet external signal USBA_ID；The entitled NXT of pin 2, meets external signal USBA_NTX；The title of pin 31
For DIR, external signal USBA_DIR is met；The entitled STP of pin 29, meets external signal USBA_STP；Pin 1 it is entitled
CLKOUT meets external signal USBA_CK；The entitled D0 of pin 3, meets external signal USBA_D0；The entitled D1 of pin 4, connects
External signal USBA_D1；The entitled D2 of pin 5, meets external signal USBA_D2；The entitled D3 of pin 6, connects external signal
USBA_D3；The entitled D4 of pin 7, meets external signal USBA_D4；The entitled D5 of pin 9, meets external signal USBA_D5；
The entitled D6 of pin 10, meets external signal USBA_D6；The entitled D7 of pin 13, meets external signal USBA_D7；
USB transceiver module II 3 and the pin connection type and USB transceiver module I 2 of fpga chip are completely the same, are
Difference outer signals, it is prefix that all signal name, which is changed to USBB_,.
The fpga chip 1 passes through ULPI agreement by connecting with USB transceiver module I 2, USB transceiver module II 3
It realizes and the data of USB transceiver module I 2, USB transceiver module II 3 is transmitted.USB transceiver module I 2, USB transceiver mould
Block II 3 are communicated by the USB2.0 communication protocol of standard with external equipment or host.DDR3SDRAM memory 4 connects
Data temporary storage module to fpga chip 1Bank3 is communicated.Back-end circuit 5 passes through the data forwarding module on fpga chip 1
Give circuit later to send temporary data, enable back-end circuit receive USB always first on data.
The USB transceiver module I 2, USB transceiver module II 3 are to connect USB interface using USB3320 chip as core
And the module of peripheral circuit.The same design of the use of two modules, wherein the operating mode of USB transceiver module I 2 is optional,
USB transceiver module II 3 works under equipment mode.
The DDR3SDRAM memory 4 be MT41J128M16HA-15E chip, peripheral circuit include setting circuit and
Power supply circuit, effect are the valid data stored from the inflow of USB transceiver module I 2, and under the transfer of fpga chip 1
The reading data of storage is sent to back-end circuit 5 to fpga chip 1 and by data forwarding module；
After the back-end circuit 5 is connected to data forwarding module, after back-end circuit 5 receives the data of monitoring, by rear
Terminal circuit 5 realizes real-time display and processing.By the utility model, may be implemented to carry out the data on usb bus to monitor and
Acquisition, and pass through the processing of fpga chip 1, it can make to wait in the data listened to storage to DDR3SDRAM memory 4
Back-end circuit 5 is sent to by data forwarding module after the transfer of fpga chip 1, back-end circuit according to circumstances needs, then to data
It is handled or is shown in real time.
Specific embodiment of the utility model is explained in detail above in conjunction with attached drawing, but the utility model and unlimited
In above-described embodiment, within the knowledge of a person skilled in the art, the utility model can also not departed from
Various changes can be made under the premise of objective.
Claims (6)
1. a kind of usb data real-time monitoring apparatus based on FPGA, it is characterised in that: including fpga chip (1), USB transceiver
Module I (2), USB transceiver module II (3), DDR3 SDRAM memory (4), back-end circuit (5)；The USB transceiver module
I (2), USB transceiver module II (3) structure are identical, wherein including USB3320 chip and USB interface；
The fpga chip (1) respectively with the USB3320 chip in USB transceiver module I (2), USB transceiver module II (3)
It is connected, the signal flow of the signal wire NTX and DIR of USB3320 chip are to flow to fpga chip (1) from USB3320 chip, are believed
The flow direction of number line STP flows to USB3320 chip by fpga chip (1), and signal wire CLK is two-way signaling, and DATA is 8 data
Line；DDR3 SDRAM memory (4) is connected to the data temporary storage module of fpga chip (1)；Back-end circuit (5) and fpga chip
(1) data forwarding module is attached by the port I/O of fpga chip (1)；USB transceiver module I (2) external can be read sets
It is standby, the external PC of USB transceiver module II (3)；
The fpga chip (1) uses XC6SLX16-FTG256 chip；DDR3 SDRAM memory (4) uses
MT41J128M16HA-15E 256MB DDR3 storage chip.
2. the usb data real-time monitoring apparatus according to claim 1 based on FPGA, it is characterised in that: the rear end electricity
It road (5) either can be to the module that image is handled using Real-time image display circuit.
3. the usb data real-time monitoring apparatus according to claim 1 based on FPGA, it is characterised in that: the USB transmitting-receiving
Device module I (2) be used to receive it is external data that equipment is sent can be read and then pass through its USB3320 chip and translate into meet
The data-signal of ULPI agreement is transmitted to fpga chip (1) again；
The fpga chip (1) receives the data that USB transceiver module I (2) is sent and then replicates again temporary by data
Module storage is sent to back-end circuit (5) in DDR3 SDRAM memory (4) and through data forwarding module unloading, and is used for
The data that USB transceiver module I (2) is sent are transmitted to USB transceiver module II (3)；
The data temporary storage module is for data cached；
The DDR3 SDRAM memory (4) is used to store the data of fpga chip (1) duplication；
The back-end circuit (5) is used to receive the data after unloading and show the image procossing in either later period；
The USB transceiver module II (3) is used to receive Data Concurrent that fpga chip (1) transmits to give and be attached thereto
PC。
4. the usb data real-time monitoring apparatus according to claim 1 based on FPGA, it is characterised in that: the USB transmitting-receiving
The external equipment that can be read of device module I (2) uses USB flash disk or PC；It is USB flash disk when equipment can be read, by fpga chip (1) USB
Transceiver module I (2) is set as host mode, and equipment USB flash disk can be read and be used as from equipment work, realizes two based on usb protocol
The communication on side；
When it is PC that equipment, which can be read, USB transceiver module I (2) is set as by fpga chip (1) by equipment mode, and can
Equipment PC is read as host work, the communication on both sides is realized based on usb protocol.
5. the usb data real-time monitoring apparatus according to claim 1 based on FPGA, it is characterised in that: further include socket
Interface and necessary peripheral circuit；The necessary peripheral circuit include power circuit, jtag circuit, two 32 × 2P,
Row's needle interface of 2.54mm spacing；Two row's needle interfaces are coupled with the I/O pin of the Bank0 and Bank1 of fpga chip, come real
The extraction of existing pin.
6. the usb data real-time monitoring apparatus according to claim 1 based on FPGA, it is characterised in that: the USB transmitting-receiving
Device module I (2) and the connection type of fpga chip are:
The entitled VBUS of the pin 22 of the USB3320 chip of USB transceiver module I (2), meets external signal USBA_VBUS；Draw
The entitled DM of foot 19, meets external signal USBA_DM；The entitled DP of pin 18, meets external signal USBA_DP；Pin 23
Entitled ID meets external signal USBA_ID；The entitled NXT of pin 2, meets external signal USBA_NTX；Pin 31 it is entitled
DIR meets external signal USBA_DIR；The entitled STP of pin 29, meets external signal USBA_STP；Pin 1 it is entitled
CLKOUT meets external signal USBA_CK；The entitled D0 of pin 3, meets external signal USBA_D0；The entitled D1 of pin 4, connects
External signal USBA_D1；The entitled D2 of pin 5, meets external signal USBA_D2；The entitled D3 of pin 6, connects external signal
USBA_D3；The entitled D4 of pin 7, meets external signal USBA_D4；The entitled D5 of pin 9, meets external signal USBA_D5；
The entitled D6 of pin 10, meets external signal USBA_D6；The entitled D7 of pin 13, meets external signal USBA_D7；
USB transceiver module II (3) and the pin connection type and USB transceiver module I (2) of fpga chip are completely the same, are
Difference outer signals, it is prefix that all signal name, which is changed to USBB_,.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821518757.XU CN209460753U (en) | 2018-09-17 | 2018-09-17 | A kind of usb data real-time monitoring apparatus based on FPGA |
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| CN201821518757.XU CN209460753U (en) | 2018-09-17 | 2018-09-17 | A kind of usb data real-time monitoring apparatus based on FPGA |
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| CN209460753U true CN209460753U (en) | 2019-10-01 |
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| CN201821518757.XU Expired - Fee Related CN209460753U (en) | 2018-09-17 | 2018-09-17 | A kind of usb data real-time monitoring apparatus based on FPGA |
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| Country | Link |
|---|---|
| CN (1) | CN209460753U (en) |
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2018
- 2018-09-17 CN CN201821518757.XU patent/CN209460753U/en not_active Expired - Fee Related
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| GR01 | Patent grant | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20191001 Termination date: 20200917 |
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| CF01 | Termination of patent right due to non-payment of annual fee |