CN109302279B - Memristor chaotic circuit system with four-wing attractor rotating - Google Patents
Memristor chaotic circuit system with four-wing attractor rotating Download PDFInfo
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- CN109302279B CN109302279B CN201811512421.7A CN201811512421A CN109302279B CN 109302279 B CN109302279 B CN 109302279B CN 201811512421 A CN201811512421 A CN 201811512421A CN 109302279 B CN109302279 B CN 109302279B
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Abstract
The invention discloses a four-wing attractor rotating memristor chaotic model and a circuit. The output signals of the first, second and third channels are used as the input signal of the first channel; output signals of the first channel, the second channel, the third channel and the memristor are used as input signals of the second channel; the output signals of the second and third channels are used as the input signals of the third channel; the output signal of the first channel is used as the input signal of the fourth channel; and the output signal of the fourth channel is used as the input signal of the memristor. Due to the nonlinear characteristic and the memory characteristic of the memristor and the fact that the chaotic system corresponding to the four constructed paths has an infinite number of balance points, the dynamic behavior of the system is extremely rich. The rotary attractor generates a single-wing period, chaos and other states, provides a set of more special secret keys for secret communication, makes chaotic secret more difficult to break, and improves the safety of chaotic secret communication.
Description
Technical Field
The invention belongs to the technical field of chaotic systems, relates to a chaotic circuit system containing a memristor, and particularly relates to a chaotic circuit system with physical realizability and rich dynamic behaviors and based on a secondary nonlinear magnetic control memristor.
Background
The theory of chaos is the leading scientific theory that has been developed in recent decades, and it is the three most important scientific discoveries that are related to quantum mechanics and relativity and are called the twentieth century. Chaos is a kind of complex dynamic behavior possessed by a nonlinear dynamic system, which is the inherent randomness of a deterministic nonlinear system, that is, chaos is a random-like phenomenon occurring in the deterministic system, and has the following main characteristics: extreme sensitivity to initial conditions, bounded nature, ergodicity, internal randomness, fractal nature, non-periodic normality.
A memristor is a fourth basic two-terminal circuit element that follows a resistance, a capacitance, and an inductance. The chaotic signal generator has the nonlinear characteristic and the memory characteristic which can not be replaced by any combination of other three basic elements, and can easily generate chaotic oscillating signals. Therefore, the idea of applying a memristor to a chaotic circuit and conducting research has been receiving attention in the nonlinear field in recent years. Meanwhile, the appearance of the memristor provides a new thought and direction for the design and application of electronic circuits. The memristor has special memory characteristics and a nonlinear memristor, and a mathematical model corresponding to a chaotic circuit containing the memristor is usually an infinite balance point, so that the memristor chaotic circuit can generate complex dynamic behaviors, such as complex dynamic phenomena of extreme multi-stability, complex transient transfer and the like. In the known technology and research, research on an analog equivalent circuit of a secondary memristor is less, and a memristor chaotic circuit system which applies the memristor to a chaotic circuit and can generate coexisting attractor rotation and continuous chaotic phenomena is never provided, which is a disadvantage of the prior art. Therefore, the memristive chaotic circuit system which is simple and easy to realize and the attractor rotates is designed to be valuable and practical.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a memristor chaotic circuit system with a four-wing attractor rotating function.
1. A construction method of a memristor chaotic circuit system with a four-wing attractor rotating function is characterized by comprising the following steps:
(1) the mathematical model of the Liu & Chen chaotic system:
wherein x, y, z and u are state variables, and a, b and c are system parameters;
(2) the invention adopts a secondary nonlinear magnetic control memristor:
q(Φ)＝αΦ+βΦ 2 (ii)
wherein q (phi) represents a magnetic control memristor, phi represents magnetic flux, and alpha and beta are memristor control parameters larger than zero;
(3) when the formula (ii) is derived, the corresponding magnetic control memory conduction model is as follows:
wherein W (phi) represents magnetic control memory conductance, phi represents magnetic flux, and alpha and beta are memristor control parameters larger than zero;
(4) the magnetic control memristor is introduced into a Liu & Chen system to obtain a memristive chaotic circuit system with a four-wing attractor rotating structure, wherein the memristor chaotic circuit system comprises the following components:
wherein x, y, z, u are state variables, a is 4, b is 13, c is 1, d is 0.001, α is 0.3, β is 0.4, and is a memristive control parameter;
2. a four-wing attractor rotating memristor chaotic circuit system constructed based on a system (iv) is characterized by comprising a first channel circuit, a second channel circuit, a third channel circuit, a fourth channel circuit and a memristor simulation equivalent circuit:
the first channel circuit is composed of a multiplier A 1 Inverse integrator U 1 Inverter U 2 And a resistor R 1 And a resistor R 2 And a resistor R 9 And a resistor R 10 Capacitor C 1 And (4) forming. The output signal x of the first channel circuit is connected with a phase inverter U 2 The output signal-x is used as a multiplier A in the second channel circuit 2 A multiplier A 3 One input signal of the first channel circuit is applied to the second channel circuit, and the output signal-x is used as a multiplier A in the third channel circuit 4 The output signal-x is connected with a resistor R in a fourth channel circuit 8 As an input signal for the fourth channel circuit.
The second channel circuit is composed of an analog equivalent circuit of a memristor and a multiplier A 2 A multiplier A 3 Inverse integrator U 3 Inverter U 4 And a resistance R 3 Resistance R 4 Resistance R 5 And a resistor R 11 And a resistor R 12 Capacitor C 2 And (4) forming. The output signal y of the second channel circuit is connected with the multiplier A in the first channel circuit 1 Is applied to the first channel circuit, and the output signal y is connected with the resistor R in the second channel circuit 3 As a second channelThe input signal of the circuit is connected with the output signal y of the multiplier A in the third channel circuit 4 Is applied to the third channel circuit.
The third channel circuit is composed of a multiplier A 4 Inverse integrator U 5 And a resistance R 6 Resistance R 7 Capacitor C 3 And (4) forming. The output signal z of the third channel circuit is connected with the multiplier A in the first channel circuit 1 Is applied to the first channel circuit, and the output signal z is connected to the multiplier A in the second channel circuit 2 The input signal acts on the second channel circuit, and the output signal z passes through a resistor R connected with the third channel circuit 6 As an input signal for the third channel circuit.
The fourth channel circuit is composed of an inverse integrator U 6 And a resistor R 8 Capacitor C 4 And (4) forming. The output signal u of the fourth channel circuit is connected with the resistor R in the memristor simulation equivalent circuit 14 As an input signal to the memristor.
The memristor simulation equivalent circuit is composed of an inverting adder U 7 Inverter U 8 And a resistance R 13 And a resistor R 14 Resistance R 15 Resistance R 16 Resistance R 17 And (4) forming. The output signal W (u) of the memristor analog equivalent circuit is connected with a multiplier A in the second channel circuit 3 Is applied to the second channel circuit.
3. The memristor chaotic circuit system with the four-wing attractor rotating function is characterized in that: the inverse integrator U 1 Inverter U 2 Inverse integrator U 3 Inverter U 4 Inverse integrator U 5 Inverse integrator U 6 Using an operational amplifier UA741, a multiplier A 1 Multiplier A 2 Multiplier A 3 A multiplier A 4 A multiplier AD633JN is used.
The operational amplifier U 1 Pin 2 of the circuit is connected with an operational amplifier U through a resistor R1 2 Pin 6 of (2), through a resistor R 2 Concatenated multiplierA 1 Pin 7 through a capacitor C 1 Connecting operational amplifier U 1 Pin 6 of (2); no. 6 pin passes through resistance R 9 Connecting operational amplifier U 2 Pin 2 through a capacitor C 1 Connecting operational amplifier U 1 The 2 nd pin of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 2 Pin 2 through a resistor R 9 Connecting operational amplifier U 1 Pin 6 of (2), through a resistor R 10 Connecting operational amplifier U 2 Pin 6 of (2); no. 6 pin passes through resistance R 10 Connecting operational amplifier U 2 Pin 2 through resistor R 1 Connecting operational amplifier U 1 Pin 2 of the multiplexer A 2 Pin 1 of the multiplexer A 3 Pin 1 of the multiplexer A 1 Pin 1 of (2), through a resistor R 8 Connecting operational amplifier U 6 Pin 2 of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 3 Pin 2 through resistor R 3 Connecting operational amplifier U 4 Pin 6 of (2), through a resistor R 4 Concatenated multiplier A 2 Pin 7 of (2), through a resistor R 5 Concatenated multiplier A 3 Pin 7 through a capacitor C 2 Connecting the 6 th pin of the operational amplifier; the 6 th pin passes through a capacitor C 2 Connecting operational amplifier U 1 Pin 2 through resistor R 11 Connecting operational amplifier U 4 Pin 2 of the multiplexer A 1 Pin 1 of (2), through a resistor R 3 Connecting operational amplifier U 3 Pin 2 of the multiplexer A, directly connected thereto 4 Pin 2 of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 4 2 ndThe pins are connected with an operational amplifier U through resistors 3 Pin 6 of (2), through a resistor R 12 Connecting operational amplifier U 4 The 6 th pin of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the 1 st pin, the 5 th pin and the 8 th pin are suspended.
The operational amplifier U 5 Pin 2 through resistor R 6 Connecting operational amplifier U 5 Pin 6 of (2), through a resistor R 7 Connecting multiplier A 4 Pin 7 through a capacitor C 3 Connecting operational amplifier U 5 The 6 th pin of (1); no. 6 pin passes through resistance R 6 Connecting operational amplifier U 5 Pin 2 of the multiplexer A 1 Pin 3 of the multiplexer A 2 Pin 3 of (2); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 6 Pin 2 through a resistor R 8 Connecting operational amplifier U 2 Pin 6 of (2), via a capacitor C 4 Connecting operational amplifier U 6 Pin 6 of (2); the 6 th pin passes through a capacitor C 4 Connecting operational amplifier U 6 Pin 2 through resistor R 14 Connection U 7 Pin 2 of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the 1 st pin, the 5 th pin and the 8 th pin are suspended.
The operational amplifier U 7 Pin 2 through a resistor R 14 Connecting operational amplifier U 6 Pin 2 through resistor R 13 Connected with a DC power supply V 1 Through a resistor R 15 Connecting operational amplifier U 7 Pin 6 of (2); no. 6 pin passes through resistance R 15 Connecting operational amplifier U 7 Pin 2 through resistor R 16 Connecting operational amplifier U 8 The 2 nd pin of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
Said operationAmplifier U 8 Pin 2 through a resistor R 16 Connecting operational amplifier U 7 Pin 6 of (2), through a resistor R 17 Connecting operational amplifier U 8 Pin 6 of (2); the 6 th pin is directly connected with a multiplier A 3 Pin 3 of (2); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The multiplier A 1 Pin 1 of the operational amplifier is directly connected with an operational amplifier U 3 Pin 6 of (2); the 3 rd pin is directly connected with an operational amplifier U 5 Pin 6 of (2); no. 7 pin pass through resistor R 2 Connecting operational amplifier U 1 Pin 2 of (1); the No. 2 pin, the No. 4 pin and the No. 6 pin are grounded, the No. 5 pin is connected with a negative voltage source VEE, and the No. 8 pin is connected with a positive voltage source VCC.
The multiplier A 2 Pin 1 of the operational amplifier is directly connected with the operational amplifier U 2 Pin 6 of (2); the 3 rd pin is directly connected with an operational amplifier U 5 Pin 6 of (2); no. 7 pin pass through resistor R 4 Connecting operational amplifier U 3 Pin 2 of (1); the No. 2 pin, the No. 4 pin and the No. 6 pin are grounded, the No. 5 pin is connected with a negative voltage source VEE, and the No. 8 pin is connected with a positive voltage source VCC.
The multiplier A 3 Pin 1 of the operational amplifier is directly connected with the operational amplifier U 2 Pin 6 of (2); the 3 rd pin is directly connected with an operational amplifier U 8 Pin 6 of (2); pin 7 through resistor R 5 Connecting operational amplifier U 3 Pin 2 of (1); the No. 2 pin, the No. 4 pin and the No. 6 pin are grounded, the No. 5 pin is connected with a negative voltage source VEE, and the No. 8 pin is connected with a positive voltage source VCC.
The multiplier A 4 Pin 1 of the operational amplifier is directly connected with an operational amplifier U 2 The 6 th pin of (1); the 3 rd pin is directly connected with an operational amplifier U 3 Pin 6 of (2); no. 7 pin pass through resistor R 7 Connecting operational amplifier U 5 Pin 2 of (1); the No. 2 pin, the No. 4 pin and the No. 6 pin are grounded, the No. 5 pin is connected with a negative voltage source VEE, and the No. 8 pin is connected with a positive voltage source VCC.
4. Four-wing attraction constructed based on system (iv)The sub-rotating memristor chaotic circuit system is characterized in that: the resistor R in the first channel circuit 1 25k, resistance R 2 1k, resistance R 9 10k, resistance R 10 10k, capacitance C 1 0.01 uF; resistance R in second channel circuit 3 7.69k, resistance R 4 1k, resistance R 5 10k, resistance R 11 10k, resistance R 12 10k, capacitance C 2 0.01 uF; resistor R in third channel circuit 6 100k, resistance R 7 1k, capacitance C 3 0.01 uF; resistor R in fourth channel circuit 8 1000k, capacitance C 4 10 uF; memristor simulation equivalent circuit resistance R 13 10k, resistance R 14 0.375k, resistance R 15 3k, resistance R 16 10k, resistance R 17 10k d.c. voltage source V 1 Has a value of 1V, a value of +15V for the positive voltage source VCC, and a value of-15V for the negative voltage source VEE.
Has the advantages that: the invention utilizes elements to build four-channel circuits. Due to the nonlinear characteristic and the memory characteristic of the memristor and the infinite balance points of the circuit corresponding to the system mathematical model, the dynamic behavior corresponding to the chaotic system is more complex and richer. The chaotic system can generate countless complicated coexisting attractors, and the rotating attractors in the states of single-wing single cycle, single-wing double cycle, single-wing chaos, double-wing and the like provide a set of novel and special secret keys for secret communication, so that the chaos secret is more difficult to crack, the safety of the secret communication is improved, and the chaotic system provides technical reference for the application of the chaotic system in the secret communication.
Drawings
Fig. 1 is a schematic connection diagram of a memristive chaotic circuit with a four-wing attractor rotating according to an embodiment of the present invention.
Fig. 2 is a phase diagram of 4 single-wing single-cycle rotation coexisting attractors of a first channel circuit output signal x and a second channel circuit output signal y in circuit simulation provided by the embodiment of the invention.
Fig. 3 is a phase diagram of 4 single-wing dual-cycle rotation coexisting attractors of a first channel circuit output signal x and a second channel circuit output signal y in circuit simulation provided by the embodiment of the invention.
Fig. 4 is a phase diagram of 4 single-wing chaotic rotary coexisting attractors of a first channel circuit output signal x and a second channel circuit output signal y in circuit simulation provided by the embodiment of the invention.
Fig. 5 is a phase diagram of continuous chaos of an output signal y of a second channel circuit and an output signal z of a third channel circuit in circuit simulation provided in the embodiment of the present invention.
Fig. 6 is a phase diagram of continuous chaos of an output signal y of a second channel circuit and an output signal z of a third channel circuit in circuit simulation provided by the embodiment of the present invention.
Fig. 7 is a phase diagram of 1 single-wing single-cycle attractor of the first channel circuit output signal x and the second channel circuit output signal y in the physical circuit according to the embodiment of the present invention.
Fig. 8 is a phase diagram of 1 single-wing two-cycle attractor of the first channel circuit output signal x and the second channel circuit output signal y in the physical circuit according to the embodiment of the present invention.
Fig. 9 is a phase diagram of 1 single-wing chaotic attractor of a first channel circuit output signal x and a second channel circuit output signal y in a physical circuit according to an embodiment of the present invention.
Detailed Description
In order to make the purpose and technical solution of the present invention more clearly understood, the following detailed description is made with reference to the accompanying drawings and examples, and the application principle of the present invention is described in detail.
1. A construction method of a memristor chaotic circuit system with a four-wing attractor rotating function is characterized by comprising the following steps:
(1) a mathematical model based on a Liu & Chen chaotic system is as follows:
wherein x, y, z and u are state variables, and a, b and c are system parameters;
(2) the invention adopts a secondary nonlinear magnetic control memristor:
q(Φ)＝αΦ+βΦ 2 (ii)
wherein q (phi) is a magnetic control memristor, phi is a magnetic flux, and alpha and beta are memristor control parameters larger than zero;
(3) when the formula (ii) is derived, the corresponding magnetic control memory conduction model is as follows:
wherein W (phi) is magnetic control memory conductance, phi is magnetic flux, and alpha and beta are memristor control parameters larger than zero;
(4) the magnetic control memristor is introduced into a Liu & Chen system to obtain a memristor chaotic circuit system with a four-wing attractor rotating structure, wherein the memristor chaotic circuit system comprises the following components:
wherein x, y, z, u are state variables, a is 4, b is 13, c is 1, d is 0.001, α is 0.3, β is 0.4, and is a memristive control parameter;
2. a four-wing attractor rotating memristor chaotic circuit system is constructed based on a system (iv), and is characterized by comprising a first channel circuit, a second channel circuit, a third channel circuit, a fourth channel circuit and a memristor simulation equivalent circuit:
the first channel circuit is composed of a multiplier A 1 Inverse integrator U 1 An inverter U 2 And a resistor R 1 Resistance R 2 Resistance R 9 Resistance R 10 Capacitor C 1 And (4) forming. The output signal x of the first channel circuit is connected with a phase inverter U 2 The output signal-x is used as a multiplier A in the second channel circuit 2 A multiplier A 3 One input signal of the first channel circuit is applied to the second channel circuit, and the output signal-x is used as a multiplier A in the third channel circuit 4 One-way input signal function ofIn the third channel circuit, the output signal-x is connected with the resistor R in the fourth channel circuit 8 As an input signal for the fourth channel circuit.
The second channel circuit is formed by a memristor simulation equivalent circuit and a multiplier A 2 Multiplier A 3 Inverse integrator U 3 Inverter U 4 And a resistance R 3 Resistance R 4 Resistance R 5 Resistance R 11 Resistance R 12 Capacitor C 2 And (4) forming. The output signal y of the second channel circuit is connected with the multiplier A in the first channel circuit 1 Is applied to the first channel circuit, and the output signal y is connected to the resistor R in the second channel circuit 3 As an input signal for the second channel circuit, while the output signal y is connected to a multiplier A in the third channel circuit 4 Is applied to the third channel circuit.
The third channel circuit is composed of a multiplier A 4 Inverse integrator U 5 And a resistance R 6 Resistance R 7 Capacitor C 3 And (4) forming. The output signal z of the third channel circuit is connected with the multiplier A in the first channel circuit 1 Is applied to the first channel circuit, and the output signal z is connected to the multiplier A in the second channel circuit 2 Acts on the second channel circuit, and simultaneously the output signal z passes through a resistor R connected with the third channel circuit 6 As an input signal for the third channel circuit.
The fourth channel circuit is composed of an inverse integrator U 6 Resistance R 8 Capacitor C 4 And (4) forming. The output signal u of the fourth channel circuit is connected with the resistor R in the memristor simulation equivalent circuit 14 As an input signal to the memristor.
The memristor simulation equivalent circuit is composed of an inverse adder U 7 An inverter U 8 And a resistance R 13 Resistance R 14 And a resistor R 15 Resistance R 16 Resistance R 17 And (4) forming. The output signal W (u) of the memristor analog equivalent circuit is connected with multiplication in the second channel circuitDevice A 3 Is applied to the second channel circuit.
3. The memristor chaotic circuit system with the four-wing attractor rotating function is characterized in that: the inverse integrator U 1 Inverter U 2 Inverse integrator U 3 Inverter U 4 Inverse integrator U 5 Inverse integrator U 6 Using an operational amplifier UA741, a multiplier A 1 Multiplier A 2 Multiplier A 3 A multiplier A 4 A multiplier AD633JN is used.
The operational amplifier U 1 Pin 2 of the circuit is connected with an operational amplifier U through a resistor R1 2 Pin 6 of (2), through a resistor R 2 Connecting multiplier A 1 Pin 7 through a capacitor C 1 Connecting operational amplifier U 1 Pin 6 of (2); no. 6 pin passes through resistance R 9 Connecting operational amplifier U 2 Pin 2 through a capacitor C 1 Connecting operational amplifier U 1 Pin 2 of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the 1 st pin, the 5 th pin and the 8 th pin are suspended.
The operational amplifier U 2 Pin 2 through a resistor R 9 Connecting operational amplifier U 1 Pin 6 of (2), through a resistor R 10 Connecting operational amplifier U 2 The 6 th pin of (1); no. 6 pin passes through resistance R 10 Connecting operational amplifier U 2 Pin 2 of (2), through a resistor R 1 Connecting operational amplifier U 1 Pin 2 of the multiplexer A 2 Pin 1 of the multiplexer A 3 Pin 1 of the multiplexer A 1 Pin 1 of (2), through a resistor R 8 Connecting operational amplifier U 6 Pin 2 of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 3 Pin 2 through a resistor R 3 Connecting operational amplifier U 4 Pin 6 of (2), through a resistor R 4 Concatenated multiplicationDevice A 2 Pin 7 of (2), through a resistor R 5 Connecting multiplier A 3 Pin 7 through a capacitor C 2 Connecting the 6 th pin of the operational amplifier; the 6 th pin passes through a capacitor C 2 Connecting operational amplifier U 1 Pin 2 through resistor R 11 Connecting operational amplifier U 4 Pin 2 of the multiplexer A 1 Pin 1 of (2), through a resistor R 3 Connecting operational amplifier U 3 Pin 2 of the multiplexer A 4 Pin 2 of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 4 Pin 2 is connected with an operational amplifier U through a resistor 3 Pin 6 of (2), through a resistor R 12 Connecting operational amplifier U 4 Pin 6 of (2); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 5 Pin 2 through a resistor R 6 Connecting operational amplifier U 5 Pin 6 of (2), through a resistor R 7 Connecting multiplier A 4 Pin 7 through a capacitor C 3 Connecting operational amplifier U 5 Pin 6 of (2); no. 6 pin passes through resistance R 6 Connecting operational amplifier U 5 Pin 2 of the multiplexer A, directly connected thereto 1 Pin 3 of the multiplexer A 2 Pin 3 of (2); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 6 Pin 2 through a resistor R 8 Connecting operational amplifier U 2 Pin 6 of (2), via a capacitor C 4 Connecting operational amplifier U 6 Pin 6 of (2); the 6 th pin passes through a capacitor C 4 Connecting operational amplifier U 6 Pin 2 through resistor R 14 Connection U 7 The 2 nd pin of (1); pin 3 is grounded, pin 4 is connected to a negative voltage source VEE, and pin 7 is connectedA positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 7 Pin 2 through a resistor R 14 Connecting operational amplifier U 6 Pin 2 through resistor R 13 Connected with a DC power supply V 1 Through a resistor R 15 Connecting operational amplifier U 7 Pin 6 of (2); no. 6 pin passes through resistance R 15 Connecting operational amplifier U 7 Pin 2 through resistor R 16 Connecting operational amplifier U 8 Pin 2 of (1); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The operational amplifier U 8 Pin 2 through a resistor R 16 Connecting operational amplifier U 7 Pin 6 of (2), through a resistor R 17 Connecting operational amplifier U 8 Pin 6 of (2); the 6 th pin is directly connected with a multiplier A 3 Pin 3 of (2); the 3 rd pin is grounded, the 4 th pin is connected with a negative voltage source VEE, and the 7 th pin is connected with a positive voltage source VCC; the No. 1 pin, the No. 5 pin and the No. 8 pin are suspended.
The multiplier A 1 Pin 1 of the operational amplifier is directly connected with an operational amplifier U 3 Pin 6 of (2); the 3 rd pin is directly connected with an operational amplifier U 5 Pin 6 of (2); no. 7 pin pass through resistor R 2 Connecting operational amplifier U 1 Pin 2 of (1); the No. 2 pin, the No. 4 pin and the No. 6 pin are grounded, the No. 5 pin is connected with a negative voltage source VEE, and the No. 8 pin is connected with a positive voltage source VCC.
The multiplier A 2 Pin 1 of the operational amplifier is directly connected with an operational amplifier U 2 Pin 6 of (2); the 3 rd pin is directly connected with an operational amplifier U 5 Pin 6 of (2); no. 7 pin pass through resistor R 4 Connecting operational amplifier U 3 Pin 2 of (1); the No. 2 pin, the No. 4 pin and the No. 6 pin are grounded, the No. 5 pin is connected with a negative voltage source VEE, and the No. 8 pin is connected with a positive voltage source VCC.
The multiplier A 3 Pin 1 of the operational amplifier is directly connected with an operational amplifier U 2 The 6 th pin of (1); pin 3 direct connection operational amplifierU 8 Pin 6 of (2); pin 7 through resistor R 5 Connecting operational amplifier U 3 Pin 2 of (1); the No. 2 pin, the No. 4 pin and the No. 6 pin are grounded, the No. 5 pin is connected with a negative voltage source VEE, and the No. 8 pin is connected with a positive voltage source VCC.
The multiplier A 4 Pin 1 of the operational amplifier is directly connected with an operational amplifier U 2 Pin 6 of (2); the 3 rd pin is directly connected with an operational amplifier U 3 The 6 th pin of (1); pin 7 through resistor R 7 Connecting operational amplifier U 5 Pin 2 of (1); the No. 2 pin, the No. 4 pin and the No. 6 pin are grounded, the No. 5 pin is connected with a negative voltage source VEE, and the No. 8 pin is connected with a positive voltage source VCC.
4. The memristor chaotic circuit system with the four-wing attractor rotating function is characterized in that: the resistor R in the first channel circuit 1 25k, resistance R 2 1k, resistance R 9 10k, resistance R 10 10k, capacitance C 1 0.01 uF; resistance R in second channel circuit 3 7.69k, resistance R 4 1k, resistance R 5 10k, resistance R 11 10k, resistance R 12 10k, capacitance C 2 0.01 uF; resistor R in third channel circuit 6 100k, resistance R 7 1k, capacitance C 3 0.01 uF; resistor R in fourth channel circuit 8 1000k, capacitance C 4 10 uF; memristor simulation equivalent circuit resistance R 13 10k, resistance R 14 0.375k, resistance R 15 3k, resistance R 16 10k, resistance R 17 10k d.c. voltage source V 1 Has a value of 1V, a value of +15V for the positive voltage source VCC, and a value of-15V for the negative voltage source VEE.
5. The invention relates to a memristor chaotic circuit system with a four-wing attractor rotating function, which is realized by adopting a circuit, four channels of signals are obtained by combining four channels of circuits and a memristor simulation equivalent circuit, verification is carried out by adopting Multisim simulation software, and the four channels of signals are obtained by adjusting a capacitor C 4 The rotation tracks of the single-wing single-cycle, single-wing double-cycle and single-wing chaotic attractors on the x-y plane obtained from the initial values are shown in figures 2, 3 and 4, and the continuous chaos in different initial states are shown in figures 5 and 6. And an operational amplifier, basic elements such as a resistor and a capacitor are adopted to build a circuit on the bread board, and the single-wing attractor tracks shown in figures 7, 8 and 9 verify the correctness of the simulation experiment.
Claims (3)
1. A construction method of a memristor chaotic circuit system with a four-wing attractor rotating function is characterized by comprising the following steps:
(1) a model of Liu & Chen chaotic circuit system:
wherein x, y, z and u are state variables, and a, b and c are system parameters;
(2) the adopted secondary nonlinear magnetic control memristor is as follows:
q(Φ)＝αΦ+βΦ 2 (ii)
wherein q (phi) represents a magnetic control memristor, phi represents a magnetic flux, and alpha and beta are memristor control parameters larger than zero;
(3) when the formula (ii) is derived, the corresponding magnetic control memory conduction model is as follows:
wherein W (phi) represents magnetic control memory conductance, phi represents magnetic flux, and alpha and beta are memristor control parameters larger than zero;
(4) a memristor is introduced into a Liu & Chen circuit system to obtain a memristor chaotic circuit system with a four-wing attractor rotating structure, wherein the memristor chaotic circuit system comprises the following components:
wherein x, y, z, u are state variables, a is 4, b is 13, c is 1, d is 0.001, α is 0.3, β is 0.4, and is a memristive control parameter;
(5) a four-wing attractor rotating memristor chaotic circuit system is constructed based on a system (iv), wherein the system circuit comprises a first channel circuit, a second channel circuit, a third channel circuit, a fourth channel circuit and a memristor simulation equivalent circuit:
the first channel circuit is composed of a multiplier A 1 Inverse integrator U 1 Inverter U 2 And a resistor R 1 Resistance R 2 Resistance R 9 Resistance R 10 Capacitor C 1 Composition is carried out; through a resistance R 1 Are respectively connected with an inverse integrator U 1 And an inverter U 2 Through a resistor R 2 Are respectively connected with an inverse integrator U 1 And multiplier a 1 Through a resistor R 9 Are respectively connected with an inverse integrator U 1 And an inverter U 2 Through a resistor R 10 Are respectively connected with a phase inverter U 2 And an inverter U 2 Through a capacitor C 1 Are respectively connected with an inverse integrator U 1 And an inverting integrator U 1 An output terminal of (a); the output signal x of the first channel circuit is connected with a phase inverter U 2 The output signal-x is used as a multiplier A in the second channel circuit 2 Multiplier A 3 One input signal of the first channel circuit is applied to the second channel circuit, and the output signal-x is used as a multiplier A in the third channel circuit 4 The output signal-x is connected with a resistor R in a fourth channel circuit 8 As an input signal to the fourth channel circuit;
the second channel circuit is formed by a memristor simulation equivalent circuit and a multiplier A 2 A multiplier A 3 Inverse integrator U 3 An inverter U 4 And a resistance R 3 Resistance R 4 Resistance R 5 Resistance R 11 Resistance R 12 Capacitor C 2 Composition is carried out; through a resistance R 3 Are respectively connected with inverse integrationDevice U 3 And an inverting integrator U 3 Through a resistor R 4 Are respectively connected with an inverse integrator U 3 And multiplier A 2 Through a resistor R 5 Are respectively connected with an inverse integrator U 3 And multiplier a 3 Through a resistor R 11 Are respectively connected with an inverse integrator U 3 And an inverter U 4 Through a resistor R 12 Are respectively connected with a phase inverter U 4 And an inverter U 4 Through a capacitor C 2 Are respectively connected with an inverse integrator U 3 And an inverting integrator U 3 An output terminal of (a); the output signal y of the second channel circuit is connected with the multiplier A in the first channel circuit 1 Is applied to the first channel circuit, and the output signal y is connected with the resistor R in the second channel circuit 3 As an input signal for the second channel circuit, while the output signal y is connected to a multiplier A in the third channel circuit 4 An input signal of the third channel circuit is applied to the third channel circuit;
the third channel circuit is composed of a multiplier A 4 Inverse integrator U 5 And a resistance R 6 And a resistor R 7 Capacitor C 3 Forming; through a resistance R 6 Are respectively connected with an inverse integrator U 5 And an inverting integrator U 5 Through a resistor R 7 Are respectively connected with an inverse integrator U 5 And multiplier a 4 Through a capacitor C 3 Are respectively connected with an inverse integrator U 5 And an inverting integrator U 5 An output terminal of (a); the output signal z of the third channel circuit is connected with the multiplier A in the first channel circuit 1 Is applied to the first channel circuit, and the output signal z is connected to the multiplier A in the second channel circuit 2 The input signal acts on the second channel circuit, and the output signal z passes through a resistor R connected with the third channel circuit 6 As an input signal for the third channel circuit;
the fourth channel circuit is composed of an inverse integrator U 6 And a resistor R 8 Capacitor C 4 Composition is carried out; through a resistance R 8 Are respectively connected with an inverse integrator U 6 And an inverter U 2 Through a capacitor C 4 Are respectively connected with an inverse integrator U 6 And an inverting integrator U 6 An output terminal of (a); the output signal u of the fourth channel circuit is connected with the resistor R in the memristor simulation equivalent circuit 14 As an input signal to a memristor;
the memristor simulation equivalent circuit is composed of an inverting adder U 7 An inverter U 8 And a resistance R 13 Resistance R 14 And a resistor R 15 And a resistor R 16 Resistance R 17 A DC voltage source V1; through a resistance R 14 Are respectively connected with an inverse adder U 7 And an inverting integrator U 6 Through a resistor R 13 Are respectively connected with an inverse adder U 7 And the positive pole of a direct voltage source V1, via a resistor R 15 Are respectively connected with an inverse adder U 7 And an inverting adder U 7 Through the two ends of the resistor respectively R 16 Connecting the inverting adder U 7 And an inverter U 8 Through a resistor R 17 Are respectively connected with a phase inverter U 8 And an inverter U 8 An output terminal of (a); the output signal W (u) of the memristor analog equivalent circuit is connected with a multiplier A in the second channel circuit 3 Is applied to the second channel circuit.
2. The method for constructing the memristive chaotic circuit system with the four-wing attractor rotating function is characterized in that: the inverse integrator U 1 An inverter U 2 Inverse integrator U 3 An inverter U 4 Inverse integrator U 5 The inverting integrator U6 adopts an operational amplifier UA741 and a multiplier A 1 A multiplier A 2 Multiplier A 3 Multiplier A 4 A multiplier AD633JN is used.
3. The method for constructing the memristive chaotic circuit system with the four-wing attractor rotating function is characterized in that: the resistor R in the first channel circuit 1 25k, resistance R 2 1k, resistance R 9 10k, resistance R 10 10k, capacitance C 1 0.01 uF; resistance R in second channel circuit 3 7.69k, resistance R 4 1k, resistance R 5 10k, resistance R 11 10k, resistance R 12 10k, capacitance C 2 0.01 uF; resistor R in third channel circuit 6 100k, resistance R 7 1k, capacitance C 3 0.01 uF; resistor R in fourth channel circuit 8 1000k, capacitance C 4 10 uF; resistance R in analog equivalent circuit of memristor 13 10k, resistance R 14 0.375k, resistance R 15 3k, resistance R 16 10k, resistance R 17 The dc voltage source V1 has a value of 1V, 10 k.
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