CN108847922A - Time-lag chaotic circuit based on fractional order memristor - Google Patents
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Abstract
The invention discloses a time-lag chaotic circuit based on a fractional order memristor, which comprises a fractional order memristor and a fractional order capacitor C1 qSkew circuit, operational amplifier U1Operational amplifier U2And a resistance R. Operational amplifier U is connected to fractional order memristor negative pole1The negative end and one end of a resistor R, and the positive electrode of the fractional order memristor is connected with an operational amplifier U1Output terminal and operational amplifier U2Positive terminal, operational amplifier U1Positive terminal grounded operational amplifier U2The output end of the operational amplifier U is connected with the other end of the resistor R after being connected with the time delay circuit in series, and the operational amplifier U2The negative terminal is connected to an operational amplifier U2Output terminal, fractional order capacitorOperational amplifier U with two parallel ends1A negative terminal and an output terminal. According to the adjusting parameters, a double-vortex entrainment attractor and a single-vortex entrainment attractor can be generated, so that the double-vortex entrainment attractor and the single-vortex entrainment attractor become a time-lag chaotic circuit based on the fractional order memristor; the memristor circuit is in fractional order, so that the memristor circuit is more practical, simple in structure and easy to realize.
Description
Technical Field
The invention relates to the technical field of chaotic circuits, in particular to a time-lag chaotic circuit based on a fractional order memristor.
Background
The concept of a Memristor (Memristor), named after its dependence of resistance on the amount of electricity passed, was proposed by zeiss in 1971 to be considered the fourth basic circuit element, in addition to resistance, capacitance and inductance. The time memory characteristic of the resistor enables the resistor to have wide application prospects in a plurality of fields such as model analysis, basic circuit design, circuit device design, simulation of biological memory behavior and the like. A memristor is a circuit device which represents the relationship between magnetic flux and electric charge, has the dimension of resistance, but is different from the resistance, the resistance value of the memristor is determined by the electric charge flowing through the memristor, and the function of memorizing the electric charge is realized. In 2008, researchers of hewlett packard company made nano memristor devices for the first time, and lifted up the research heat tide of memristors. The appearance of the nanometer memristor is expected to realize a nonvolatile random access memory. Moreover, the integration level, the power consumption and the reading and writing speed of the random access memory based on the memristor are superior to those of the traditional random access memory. Furthermore, memristors are the best way to implement artificial neural network synapses in hardware. Due to the nonlinear property of the memristor, a chaotic circuit can be generated, so that the chaotic circuit has many applications in secret communication.
Chaos is a deterministic and random-like phenomenon in a nonlinear system, chaotic signals have characteristics of non-periodicity, noise-like and the like, signal design and generation mechanisms of the lung can be provided, and due to the self time-lag characteristics of the time-lag chaotic system, the time-lag chaotic system can generate an infinite-dimensional state space, so that the system has richer dynamic characteristics.
Disclosure of Invention
The purpose of the invention is as follows: aiming at the prior art, a time-lag chaotic circuit based on a fractional order memristor is provided, and a system signal of the time-lag chaotic circuit has stronger chaotic characteristics.
The technical scheme is as follows: a time lag chaotic circuit based on a fractional order memristor comprises a fractional order memristor MqA fractional order capacitor C1 qTime-lag circuit tau, operational amplifier U1Operational amplifier U2A resistance R; the fractional order memristor MqNegative pole connected operational amplifier U1Negative terminal and resistance R terminal, the fractional order memristor MqThe anode is connected with the operational amplifier U1Output terminal and the operational amplifier U2Positive terminal, the operational amplifier U1Positive terminal grounded, the operational amplifier U2The output end of the operational amplifier U is connected with the other end of the resistor R after being connected with the time delay circuit tau in series, and the operational amplifier U2The negative terminal is connected to an operational amplifier U2An output terminal, the fractional order capacitor C1 qThe two ends of the operational amplifier U are connected in parallel1A negative terminal and an output terminal.
Further, the fractional order memristor comprises a resistance R0～R4Operational amplifier U3～U5Analog multiplier M1Analog multiplier M2Fractional order capacitorResistance R1One end is connected with an operational amplifier U3Negative terminal, said resistance R1The other end is grounded, an operational amplifier U3Output end connecting resistor R0One terminal and an operational amplifier U3Positive terminal, the resistor R0The other end is connected with a fractional order capacitorOne terminal and operational amplifier U5Negative terminal, operational amplifier U5Positive terminal grounded, the operational amplifier U5The output end is connected with the fractional order capacitorThe other end and an analog multiplier M1Said analog multiplier M1The output end is connected to the analog multiplier M2Said analog multiplier M2Is connected to said operational amplifier U3Negative terminal, said analog multiplier M2Is connected with the resistor R2One end, the resistance R2The other end is connected with an operational amplifier U4Negative terminal and resistor R4One end, the operational amplifier U4The output end is connected with the resistor R4The other end and the resistor R3One terminal, resistance R3The other end is connected with the operational amplifier U4Positive terminal and the operational amplifier U3Negative terminal, operational amplifier U3The negative end is used as the anode of a fractional order memristor, and the operational amplifier U4The output end is used as the cathode of the fractional order memristor.
Further, the time-lag circuit τ includes a slide rheostat R14Sliding rheostat R15Resistance R7～R10Capacitor C7Capacitor C8Operational amplifier U6Operational amplifier U7(ii) a Sliding rheostat R14One end is connected with a capacitor C simultaneously8One terminal and operational amplifier U7The positive end of the air conditioner is provided with a fan,the capacitor C8The other end is grounded, and the slide rheostat R14The other end is connected with a resistor R10One end, the resistance R10The other end is simultaneously connected with the operational amplifier U7Negative terminal and resistor R9One end, the resistance R9The other end is connected with the operational amplifier U7Output terminal, resistor R8One end and sliding rheostat R15One end of the slide rheostat R15The other end is simultaneously connected with a capacitor C7One terminal and operational amplifier U6Positive terminal, the capacitor C7The other end is grounded, and the resistor R8The other end is simultaneously connected with the negative end of the operational amplifier and the resistor R7One end, the resistance R7The other end is connected with the operational amplifier U6And (4) an output end.
Further, the fractional order capacitorAnd fractional order capacitorThe device is composed of 3 resistors which are sequentially connected in series and a capacitor which is connected with each resistor in parallel.
Has the advantages that: the invention provides a time-lag chaotic circuit based on a fractional order memristor, which can accurately simulate a real active magnetic control memristor; the chaotic circuit can perform numerical simulation and circuit simulation, and can generate a double-vortex entrainment attractor and a single-vortex entrainment attractor according to the adjusting parameters.
The time-lag chaotic circuit based on the fractional order memristor is more practical due to the fractional order, has important significance for theoretical research and physical research, and is simple in structure and easy to realize. The output signal of the circuit has stronger chaotic characteristic, and the time-lag chaotic circuit based on the fractional order memristor is applied to image encryption and secret communication, so that the complexity of a secret key and the system resistance are enhanced.
Drawings
FIG. 1 is a schematic diagram of a time-lag chaotic circuit structure based on a fractional order memristor according to the present invention;
FIG. 2 is a phase diagram of a time-lag chaotic circuit based on a fractional order memristor, wherein (a) is a limit cycle x1(t)-x1(t-tau) -dimensional phase diagram, (b) is single-vortex x1(t) -x1 (t-tau) -dimensional phase diagram, and (c) is double-vortex x1(t)-x1(t- τ) dimensional phase diagram;
FIG. 3 is a bifurcation diagram of a time-lag chaotic circuit varying with a parameter a based on a fractional order memristor according to the present invention;
FIG. 4 is a maximum Lyapunov exponent diagram of a time-lag chaotic circuit varying with a parameter a based on a fractional order memristor according to the present invention;
FIG. 5 is a specific circuit diagram of a time-lag chaotic circuit based on a fractional order memristor according to the present invention;
FIG. 6 is a time-lag chaotic circuit Multisim circuit simulation using a fractional order memristor of the present invention, wherein (a) is a limit cycle phase diagram, and (b) is a time domain diagram when a limit cycle appears;
FIG. 7 is a time-lag chaotic circuit Multisim circuit simulation based on a fractional order memristor, wherein (a) is a single-vortex phase diagram, and (b) is a time domain diagram when a single vortex occurs;
fig. 8 is a time-lag chaotic circuit Multisim circuit simulation based on a fractional order memristor, wherein (a) is a double-vortex phase diagram, and (b) is a time domain diagram when double vortices occur.
Detailed Description
The invention is further explained below with reference to the drawings.
As shown in fig. 1, a memory based on fractional orderTime-lag chaotic circuit of resistor, including fractional order memristor MqFractional order capacitorTime-lag circuit tau, operational amplifier U1Operational amplifier U2And a resistance R. Fractional order memristor MqNegative pole connected operational amplifier U1Negative terminal and resistor R terminal, fractional order memristor MqThe anode is connected with an operational amplifier U1Output terminal and operational amplifier U2Positive terminal, operational amplifier U1Positive terminal grounded operational amplifier U2The output end of the operational amplifier U is connected with the other end of the resistor R after being connected with the time delay circuit tau in series, and the operational amplifier U2The negative terminal is connected to an operational amplifier U2Output terminal, fractional order capacitorThe two ends of the operational amplifier U are connected in parallel1A negative terminal and an output terminal.
As shown in FIG. 5, the fractional order memristor includes a resistance R0～R4Operational amplifier U3～U5Analog multiplier M1Analog multiplier M2Fractional order capacitorResistance R1One end is connected with an operational amplifier U3Negative terminal, resistance R1The other end is grounded, an operational amplifier U3Output end connecting resistor R0One terminal and an operational amplifier U3Positive terminal, resistor R0The other end is connected with a fractional order capacitorOne terminal and operational amplifier U5Negative terminal, operational amplifier U5Positive terminal grounded operational amplifier U5The output end is connected with a fractional order capacitorThe other end andanalog multiplier M1Two input terminals of, the analog multiplier M1The output end is connected to the analog multiplier M2An input of the analog multiplier M2Is connected to an operational amplifier U3Negative terminal, analog multiplier M2Is connected with the resistor R2One terminal, resistance R2The other end is connected with an operational amplifier U4Negative terminal and resistor R4One terminal, operational amplifier U4Output end connecting resistor R4The other end and a resistor R3One terminal, resistance R3The other end is connected with an operational amplifier U4Positive terminal and operational amplifier U3A negative terminal. Operational amplifier U3The negative end is used as the anode of the fractional order memristor, and an operational amplifier U4The output end is used as the cathode of the fractional order memristor.
The time-lag circuit tau includes a slide rheostat R14Sliding rheostat R15Resistance R7～R10Capacitor C7Capacitor C8Operational amplifier U6Operational amplifier U7. Sliding rheostat R14One end is connected with a capacitor C simultaneously8One terminal and operational amplifier U7Positive terminal, capacitor C8The other end is grounded, and the slide rheostat R14The other end is connected with a resistor R10One terminal, resistance R10The other end is simultaneously connected with an operational amplifier U7Negative terminal and resistor R9One terminal, resistance R9The other end is connected with an operational amplifier U7Output terminal, resistor R8One end and sliding rheostat R15One end, slide rheostat R15The other end is simultaneously connected with a capacitor C7One terminal and operational amplifier U6Positive terminal, capacitor C7The other end is grounded, and a resistor R8The other end is simultaneously connected with the negative end of the operational amplifier and the resistor R7One terminal, resistance R7The other end is connected with an operational amplifier U6And (4) an output end. Sliding rheostat R14And a resistor R10The common end of the time delay circuit is used as the input end of the time delay circuit tau and is connected with an operational amplifier U2Output terminal, operational amplifier U6The output end is used as a time delay circuit tauThe output end of the resistor is connected with a resistor R.
Fractional order capacitorComposed of three resistors R connected in series11、R12、R13And each resistor is connected with a capacitor C in parallel4、C5、C6And (4) forming. Fractional order capacitorComposed of three resistors R connected in series16、R5、R6And each resistor is connected with a capacitor C in parallel1、C2、C3And (4) forming.
The mathematical model of the fractional order memristor is as follows:
wherein, g1Is an analog multiplier M1Variable scale factor of (1), g2Is an analog multiplier M2X1 is the input voltage, x2 is the intermediate state voltage, f (x1, x2) memristor output voltage, t represents time,the superscript in (1) represents the q-order derivation.
By applying kirchhoff's circuit law, the kinetic equation of the fractional order memristor-based time-lag chaotic circuit of fig. 1 is:
wherein,x1τ＝x1(t- τ), τ is the delay.
Order toObtaining:
in order to verify the chaotic circuit realized based on the fractional order memristor, MATLAB software is utilized to carry out numerical simulation. The following is a memristor parameter table:
| circuit parameter | Value of | Circuit parameter | Value of |
| Resistance R4 | 2kΩ | Scale factor g1 | 0.1 |
| Resistance R0 | 8.2kΩ | Scale factor g2 | 1.3 |
| Resistance R1 | 750Ω | ||
| Resistance R2、R3 | 1.5kΩ，2kΩ |
By applying a prediction correction method to a kinetic equation of a time-lag chaotic circuit of the fractional order memristor, and obtaining a time-lag chaotic circuit limit loop x of the fractional order memristor when q of the fractional order selection is 0.91(t)-x1(t- τ) dimensional phase diagram, x1(t) is the input voltage at time t, as shown in FIG. 2 (a). FIG. 2(b) shows a single vortex x of a time-lag chaotic circuit of a fractional order memristor1(t)-x1(t- τ) dimensional phase diagram; it can be clearly seen in fig. 2(c) that the number of chaotic attractors is 2. A bifurcation graph (q is 0.9) of the fractional order memristive chaotic time-lag circuit along with the parameter a, as shown in fig. 3. It can be known from the figure that when the parameter a is before 1.55, the phase trajectory of the fractional order memristive chaotic time-lag circuit finally tends to be stable, and the contraction speed of the phase trajectory is faster along with the increase of the parameter a; when the order rises to 1.62, the circuit has Hopf bifurcation, which means that the balance point of the circuit is unstable, and the phase diagram is converted into a stable limit loop. With the rise of the parameter a again, the circuit gradually presents a single vortex tube attractor, and with the rise of the parameter, the attraction of the attractor is stronger and stronger; when the order rises to 1.68, the attractor of the circuit transitions from a single scroll to a double scroll attractor, as shown in fig. 2 (c).
For further analysis, the maximum lyapunov exponent (q ═ 0.9) of the fractional order memristive chaotic time-lag circuit as a function of the parameter a is shown in fig. 4. It can be known from the figure that when the parameter a is before 1.55, the phase trajectory of the fractional order memristive chaotic time-lag circuit finally tends to be stable, and as the parameter a increases, the fractional order memristive chaotic time-lag circuit enters a chaotic state.
Circuit simulation:
in order to further verify the feasibility of the simple memristor chaotic circuit, Multisim software is used for circuit simulation, and a circuit diagram for realizing the fractional order memristor time-lag chaotic circuit is shown in fig. 5.
When the order is selected to be 0.9 order, and when n is 3, parameters of the fractional order equivalent capacitance and resistance can be obtained. The equation for the transfer function H(s) for fractional order capacitance is:
wherein, C0As a unit parameter, let C01 μ F, sinceWill be represented by the formulaBy comparison, we obtained: r16＝R11＝62.84MΩ，R5＝R12＝250KΩ， R6＝R13＝2.5KΩ，C1＝C4＝1.232uF，C2＝C5＝1.835uF，C3＝C6＝1.1uF。
The chaotic circuit simulation is carried out by changing the parameter a, and experimental result graphs are shown in fig. 6, 7 and 8. When the order rises to 1.62, the phase diagram transitions to a stable limit cycle. With the rise of the parameter a again, the circuit gradually presents a single vortex tube attractor, and with the rise of the parameter, the attraction of the attractor is stronger and stronger; when the order is increased to 1.68, the attractor of the circuit is changed from a single vortex tube to a double vortex attractor, the result is completely consistent with the result of numerical simulation, and the correctness of theoretical analysis is verified.
The time-lag chaotic circuit based on the fractional order memristor can accurately simulate a real active magnetic control memristor. Through numerical simulation and circuit simulation, a double-vortex entrainment attractor and a single-vortex entrainment attractor can be generated according to adjusting parameters, so that the double-vortex entrainment attractor becomes a time-lag chaotic circuit based on the fractional order memristor. The memristor circuit is of fractional order, is more practical, has important significance for theoretical research and physical research, and is simple in structure and easy to implement. The output signal of the circuit has stronger chaotic characteristic, and the time-lag chaotic circuit based on the fractional order memristor is applied to image encryption and secret communication, so that the complexity of a secret key and the system resistance are enhanced.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (4)
1. A time-lag chaotic circuit based on a fractional order memristor is characterized by comprising a fractional order memristor MqFractional order capacitorTime-lag circuit tau, operational amplifier U1Operational amplifier U2A resistance R; the fractional order memristor MqNegative pole connected operational amplifier U1Negative terminal and resistance R terminal, the fractional order memristor MqThe anode is connected with the operational amplifier U1Output terminal and the operational amplifier U2Positive terminal, the operational amplifier U1Positive terminal grounded, the operational amplifier U2The output end of the operational amplifier U is connected with the other end of the resistor R after being connected with the time delay circuit tau in series, and the operational amplifier U2The negative terminal is connected to an operational amplifier U2An output terminal, the fractional order capacitorThe two ends of the operational amplifier U are connected in parallel1A negative terminal and an output terminal.
2. The fractional order memristor-based time-lag chaotic circuit according to claim 1, wherein the fractional order memristor comprises a resistance R0～R4Operational amplifier U3～U5Analog multiplier M1Analog multiplier M2Fractional order capacitorResistance R1One end is connected with an operational amplifier U3Negative terminal, said resistance R1The other end is grounded, an operational amplifier U3Output end connecting resistor R0One terminal and an operational amplifier U3Positive terminal, the resistor R0The other end is connected with a fractional order capacitorOne terminal and operational amplifier U5Negative terminal, operational amplifier U5Positive terminal grounded, the operational amplifier U5The output end is connected with the fractional order capacitorThe other end and an analog multiplier M1Said analog multiplier M1The output end is connected to the analog multiplier M2Said analog multiplier M2Is connected to said operational amplifierAmplifier U3Negative terminal, said analog multiplier M2Is connected with the resistor R2One end, the resistance R2The other end is connected with an operational amplifier U4Negative terminal and resistor R4One end, the operational amplifier U4The output end is connected with the resistor R4The other end and the resistor R3One terminal, resistance R3The other end is connected with the operational amplifier U4Positive terminal and the operational amplifier U3Negative terminal, operational amplifier U3The negative end is used as the anode of a fractional order memristor, and the operational amplifier U4The output end is used as the cathode of the fractional order memristor.
3. The fractional order memristor-based time-lag chaotic circuit according to claim 1 or 2, wherein the time-lag circuit τ comprises a sliding rheostat R14Sliding rheostat R15Resistance R7～R10Capacitor C7Capacitor C8Operational amplifier U6Operational amplifier U7(ii) a Sliding rheostat R14One end is connected with a capacitor C simultaneously8One terminal and operational amplifier U7Positive terminal, the capacitor C8The other end is grounded, and the slide rheostat R14The other end is connected with a resistor R10One end, the resistance R10The other end is simultaneously connected with the operational amplifier U7Negative terminal and resistor R9One end, the resistance R9The other end is connected with the operational amplifier U7Output terminal, resistor R8One end and sliding rheostat R15One end of the slide rheostat R15The other end is simultaneously connected with a capacitor C7One terminal and operational amplifier U6Positive terminal, the capacitor C7The other end is grounded, and the resistor R8The other end is simultaneously connected with the negative end of the operational amplifier and the resistor R7One end, the resistance R7The other end is connected with the operational amplifier U6And (4) an output end.
4. A process as claimed in claim 3The time-lag chaotic circuit based on the fractional order memristor is characterized in that the fractional order capacitorAnd fractional order capacitorThe device is composed of 3 resistors which are sequentially connected in series and a capacitor which is connected with each resistor in parallel.
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| CN109670221A (en) * | 2018-12-06 | 2019-04-23 | 西安理工大学 | A kind of cubic non-linearity magnetic control memristor circuit being made of fractional order capacitor |
| CN111125980A (en) * | 2019-12-12 | 2020-05-08 | 杭州电子科技大学 | Fractional order exponential type memristor circuit model |
| CN111490868A (en) * | 2020-04-10 | 2020-08-04 | 湘潭大学 | Single-scroll and double-scroll controllable chaotic circuit with break points |
| CN113078994A (en) * | 2021-04-01 | 2021-07-06 | 安徽大学 | Fractional order coupling memristor chaotic circuit |
| CN113219836A (en) * | 2021-05-19 | 2021-08-06 | 安徽大学 | Projection synchronization method of fractional order complex value memristor neural network and application of projection synchronization method |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109670221A (en) * | 2018-12-06 | 2019-04-23 | 西安理工大学 | A kind of cubic non-linearity magnetic control memristor circuit being made of fractional order capacitor |
| CN109670221B (en) * | 2018-12-06 | 2022-10-14 | 西安理工大学 | Cubic nonlinear magnetic control memristor circuit composed of fractional order capacitors |
| CN111125980A (en) * | 2019-12-12 | 2020-05-08 | 杭州电子科技大学 | Fractional order exponential type memristor circuit model |
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| CN111490868B (en) * | 2020-04-10 | 2023-04-18 | 湘潭大学 | Single-scroll and double-scroll controllable chaotic circuit with break points |
| CN113078994A (en) * | 2021-04-01 | 2021-07-06 | 安徽大学 | Fractional order coupling memristor chaotic circuit |
| CN113078994B (en) * | 2021-04-01 | 2022-05-06 | 安徽大学 | Fractional order coupling memristor chaotic circuit |
| CN113219836A (en) * | 2021-05-19 | 2021-08-06 | 安徽大学 | Projection synchronization method of fractional order complex value memristor neural network and application of projection synchronization method |
| CN113219836B (en) * | 2021-05-19 | 2022-04-08 | 安徽大学 | Projection synchronization method of fractional order complex value memristor neural network and application of projection synchronization method |
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Application publication date: 20181120 |