CN109274354A - Clock duty cycle adjuster - Google Patents
Clock duty cycle adjuster Download PDFInfo
- Publication number
- CN109274354A CN109274354A CN201811144175.4A CN201811144175A CN109274354A CN 109274354 A CN109274354 A CN 109274354A CN 201811144175 A CN201811144175 A CN 201811144175A CN 109274354 A CN109274354 A CN 109274354A
- Authority
- CN
- China
- Prior art keywords
- duty ratio
- clock
- adjusted
- pmos transistor
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
Abstract
The invention discloses a kind of clock duty cycle adjusters, comprising: dutyfactor adjustment circuit, analog voltage comparator, frequency-halving circuit, control logic circuit and duty ratio-voltage conversion circuit；The dutyfactor adjustment circuit is made of third PMOS transistor, third NMOS transistor, multiple cellular constructions being composed in series by a PMOS transistor and an electronic switch and first capacitor；The multiple cellular construction from small to large, is successively connected in parallel between supply voltage VDD and clock signal CKT output end adjusted by number；The source electrode of PMOS transistor in plurality of cellular construction is connected with supply voltage vdd terminal, and grid inputs clock signal CKIN to be adjusted, and drain electrode is connected with one end of electronic switch, and the other end of electronic switch is connected with CKT output end；First capacitor is connected between CKT output end and ground.The duty ratio of energy adjust automatically clock of the present invention is 50%.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of clock duty cycle adjuster.
Background technique
Clock duty cycle is a critically important technical indicator.Generally, 50% duty ratio most has data processing
Power is the guarantee of system steady operation.Especially while the system for carrying out data processing using rising edge and failing edge, it is desirable that tool
There is the clock signal of 50% duty ratio, otherwise will reduce the data-handling capacity of system.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of clock duty cycle adjuster, the duties of energy adjust automatically clock
Than being 50%.
In order to solve the above technical problems, clock duty cycle adjuster of the invention, comprising: dutyfactor adjustment circuit, simulation
Voltage comparator, frequency-halving circuit, control logic circuit and duty ratio-voltage conversion circuit；
The dutyfactor adjustment circuit is adjusted the clock CKIN to be adjusted of input, generates clock letter adjusted
Number CKT；
Clock CKIN to be adjusted is generated as the clock of 50% duty ratio by the frequency-halving circuit, is believed as reference clock
Number CKR；
Duty ratio-the voltage conversion circuit converts clock signal CKT adjusted, generates clock to be adjusted
Duty ratio integrated voltage signal VCT；Reference clock signal CKR is converted, reference clock duty ratio integral voltage is generated
VCR；
The analog voltage comparator is compared the voltage VCT and VCR of input, and exports comparison result CMPO；
The control logic circuit adjusts switching value according to the duty ratio that comparison result CMPO generates N-bit, controls duty
Reach adjustment target than electronic switch in adjustment circuit；Wherein, N is the integer more than or equal to 0；
For the dutyfactor adjustment circuit by third PMOS transistor, third NMOS transistor is multiple by a PMOS transistor
Cellular construction and the first capacitor composition being composed in series with an electronic switch；
Electronic switch in multiple cellular constructions is denoted as SW0 respectively ... SWn, PMOS transistor are denoted as P0 respectively ... Pn；N is
Integer more than or equal to 0, and n=N；
The source electrode of PMOS transistor PM3 is connected with supply voltage vdd terminal, and the drain electrode of PMOS transistor PM3 and NMOS are brilliant
The drain electrode of body pipe NM3 is connected, and the node of connection is used as clock signal CKT output end adjusted, NMOS transistor
The source electrode of NM3 is grounded, and the grid of PMOS transistor PM3 is connected with the grid of NMOS transistor NM3, inputs clock letter to be adjusted
Number CKIN；
The multiple cellular construction by number from small to large, be successively connected in parallel supply voltage VDD and it is adjusted when
Between clock signal CKT output end；The source electrode of PMOS transistor in plurality of cellular construction is connected with supply voltage vdd terminal
It connects, grid inputs clock signal CKIN to be adjusted, and drain electrode is connected with one end of electronic switch, the other end of electronic switch
It is connected with clock signal CKT output end adjusted；
First capacitor is connected between clock signal CKT output end and ground adjusted.
The present invention is 50% using the duty ratio of hybrid digital analog circuit structure adjust automatically clock.
Circuit structure of the invention is flexible, Design of digital, can according to duty ratio adjust demand, expanding digital bit wide and
The quantity of corresponding analog circuit reaches Adjustment precision requirement in dutyfactor adjustment circuit.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is one embodiment schematic diagram of clock duty cycle adjuster；
Fig. 2 is clock duty cycle adjustment flow chart.
Specific embodiment
Shown in Figure 1, the clock duty cycle adjuster is in the following embodiments, comprising: dutyfactor adjustment circuit,
Analog voltage comparator, frequency-halving circuit, control logic circuit and duty ratio-voltage conversion circuit.
The dutyfactor adjustment circuit is adjusted the clock signal CKIN to be adjusted of input, when generating adjusted
Clock signal CKT.
The dutyfactor adjustment circuit, comprising: PMOS transistor PM3, NMOS transistor NM3, it is multiple by a PMOS crystal
The cellular construction and a capacitor C0 that pipe and an electronic switch are composed in series.
Electronic switch in multiple cellular constructions is denoted as SW0 respectively ... SWn, PMOS transistor are denoted as P0 respectively ... Pn；N is
Integer more than or equal to 0, and n=N.
The source electrode of PMOS transistor PM3 is connected with supply voltage vdd terminal, and the drain electrode of PMOS transistor PM3 and NMOS are brilliant
The drain electrode of body pipe NM3 is connected, and the node of connection is used as clock signal CKT output end adjusted, NMOS transistor
The source electrode of NM3 is grounded, and the grid of PMOS transistor PM3 is connected with the grid of NMOS transistor NM3, inputs clock letter to be adjusted
Number CKIN.
The multiple cellular construction by number from small to large, be successively connected in parallel supply voltage VDD and it is adjusted when
Between clock signal CKT output end；The source electrode of PMOS transistor in plurality of cellular construction is connected with supply voltage vdd terminal
It connects, grid inputs clock signal CKIN to be adjusted, and drain electrode is connected with one end of electronic switch, the other end of electronic switch
It is connected with clock signal CKT output end adjusted；
Capacitor C0 is connected between clock signal CKT output end and ground adjusted.
Clock signal CKT adjusted is generated as the clock of 50% duty ratio, as reference by the frequency-halving circuit
Clock signal CKR.
Duty ratio-the voltage conversion circuit converts clock signal CKT adjusted, generates clock to be adjusted
Duty ratio integrated voltage signal VCT；Reference clock signal CKR is converted, reference clock duty ratio integral voltage letter is generated
Number VCR.
The analog voltage comparator, to the clock duty cycle integrated voltage signal VCT and reference clock to be adjusted of input
Duty ratio integrated voltage signal VCR is compared, and exports comparison result signal CMPO.
The control logic circuit adjusts switching value, control according to the duty ratio that comparison result signal CMPO generates N-bit
Electronic switch SW0~SWn reaches adjustment target in dutyfactor adjustment circuit.
Detailed process is as follows for clock signal duty cycle adjustment:
The duty ratio adjustment register reset in the control logic circuit is complete " 0 ", so that in dutyfactor adjustment circuit
Electronic switch be full-gear, setting duty ratio adjusts the value of the precedence counter of register (its value is indicated with variable k)
Value is N.The duty ratio adjustment register is N-bit, and N is the integer more than or equal to 0.
The value that duty ratio controls register is set from highest order to lowest order, checks the comparison of analog voltage comparator output
As a result the value of CMPO, if it is height, the kth position that duty ratio adjustment register is arranged is " 1 ", is otherwise provided as " 0 ".
Judging the duty ratio control register, whether everybody is fully completed setting, i.e., the count value of the described precedence counter
It whether is " 0 ", if not being fully completed setting, i.e., the count value of the described precedence counter is not equal to 0, then counts the precedence
The value of device subtracts 1, i.e. k=k-1.It then proceedes to check the value of the output CMPO of analog voltage comparator, and is configured；Until N
All positions of bit duty cycle adjustment register are provided with.
Duty ratio-the voltage conversion circuit, comprising: PMOS transistor PM1, PM2, NMOS transistor NM1, NM2, resistance
R1, R2, capacitor C1, C2.
The source electrode of PMOS transistor PM1 and the source electrode of PMOS transistor PM2 are connected with supply voltage vdd terminal, and PMOS is brilliant
The drain electrode of body pipe PM1 is connected with one end of the drain electrode of NMOS transistor NM1 and resistance R1, the other end and capacitor C1 of resistance R1
One end be connected, output end of the node of the connection as clock duty cycle integrated voltage signal VCT to be adjusted, NMOS crystal
The source electrode of pipe NM1 and the other end of capacitor C1 are grounded GND.The grid of PMOS transistor PM1 and the grid of NMOS transistor NM1 are defeated
Enter clock signal CKT adjusted.
The drain electrode of PMOS transistor PM2 is connected with one end of the drain electrode of NMOS transistor NM2 and resistance R2, resistance R2's
The other end is connected with one end of capacitor C2, and the node of the connection is as the defeated of reference clock duty ratio integrated voltage signal VCR
Outlet, the source electrode of NMOS transistor NM2 and the other end of capacitor C2 are grounded GND.The grid and NMOS crystal of PMOS transistor PM2
The grid input of pipe NM2 refers to duty cycle clock signal CKR.
The metal-oxide-semiconductor in CMOS technology is used only in the present invention, and the elemental devices such as capacitor require technique low；Using " number
Change " structure, the quantity and size of the metal-oxide-semiconductor and capacitor that adjustment can be required to use according to required Adjustment precision accomplish optimal set
Meter.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (3)
1. a kind of clock duty cycle adjuster characterized by comprising dutyfactor adjustment circuit, analog voltage comparator, two points
Frequency circuit, control logic circuit and duty ratio-voltage conversion circuit；
The dutyfactor adjustment circuit is adjusted the clock CKIN to be adjusted of input, generates clock signal adjusted
CKT；
Clock CKIN to be adjusted is generated as the clock of 50% duty ratio, as reference clock signal by the frequency-halving circuit
CKR；
Duty ratio-the voltage conversion circuit converts clock signal CKT adjusted, generates clock duty to be adjusted
Than integrated voltage signal VCT；Reference clock signal CKR is converted, reference clock duty ratio integral voltage VCR is generated；
The analog voltage comparator is compared the voltage VCT and VCR of input, and exports comparison result CMPO；
The control logic circuit adjusts switching value according to the duty ratio that comparison result CMPO generates N-bit, controls duty ratio tune
Electronic switch reaches adjustment target in whole circuit；Wherein, N is the integer more than or equal to 0；
The dutyfactor adjustment circuit, comprising: third PMOS transistor, third NMOS transistor are multiple by a PMOS transistor
The cellular construction and first capacitor being composed in series with an electronic switch；
Electronic switch in multiple cellular constructions is denoted as SW0 respectively ... SWn, PMOS transistor are denoted as P0 respectively ... Pn；N be greater than
Integer equal to 0, and n=N；
The source electrode of third PMOS transistor is connected with supply voltage vdd terminal, the drain electrode of third PMOS transistor and the 3rd NMOS
The drain electrode of transistor is connected, and the node of connection is used as clock signal CKT output end adjusted, the 3rd NMOS crystal
The source electrode of pipe is grounded, and the grid of third PMOS transistor is connected with the grid of third NMOS transistor, inputs clock to be adjusted
Signal CKIN；
The multiple cellular construction from small to large, is successively connected in supply voltage VDD in parallel and clock adjusted is believed by number
Between number CKT output end；The source electrode of PMOS transistor in plurality of cellular construction is connected with supply voltage vdd terminal,
Grid inputs clock signal CKIN to be adjusted, and drain electrode is connected with one end of electronic switch, the other end and tune of electronic switch
Clock signal CKT output end after whole is connected；
First capacitor is connected between clock signal CKT output end and ground adjusted.
2. clock duty cycle adjuster as described in claim 1, it is characterised in that: the specific mistake of clock signal duty cycle adjustment
Journey is as follows:
The duty ratio adjustment register reset in the control logic circuit is complete " 0 ", so that complete in dutyfactor adjustment circuit
Portion's electronic switch is off-state, and the duty ratio adjustment register is N-bit；The precedence meter of duty ratio adjustment register is set
The value of number device is N；
The value that duty ratio controls register is set from highest order to lowest order, checks the comparison result of analog voltage comparator output
The value of CMPO, if it is high level, it is " 1 " that the duty ratio adjustment current precedence of register, which is arranged, is otherwise provided as " 0 "；
Judging the duty ratio control register, whether everybody is fully completed setting, i.e., whether the count value of the described precedence counter
The value of the precedence counter is subtracted 1 if not being fully completed setting for " 0 ", then proceedes to check analog voltage comparator
Output CMPO value, and be configured；Until all positions of N-bit duty ratio adjustment register are provided with.
3. clock duty cycle adjuster as claimed in claim 1 or 2, it is characterised in that: the duty ratio-voltage conversion electricity
Road, comprising: two PMOS transistors, two NMOS transistors, two resistance, two capacitors；
The source electrode of first PMOS transistor and the source electrode of the second PMOS transistor are connected with supply voltage vdd terminal, the first PMOS
The drain electrode of transistor is connected with one end of the drain electrode of the first NMOS transistor and first resistor, the other end of first resistor and
One end of one capacitor is connected, output end of the node of the connection as clock duty cycle integrated voltage signal VCT to be adjusted, the
The source electrode of one NMOS transistor and the other end of capacitor are grounded GND；The grid of first PMOS transistor and the first NMOS transistor
Grid input clock signal CKT adjusted；
The drain electrode of second PMOS transistor is connected with one end of the drain electrode of the second NMOS transistor and second resistance, second resistance
The other end be connected with one end of the second capacitor, the node of the connection is as reference clock duty ratio integrated voltage signal VCR
Output end, the other end of the source electrode of the second NMOS transistor and the second capacitor is grounded GND；The grid of second PMOS transistor and
The grid input of second NMOS transistor refers to duty cycle clock signal CKR.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811144175.4A CN109274354A (en) | 2018-09-29 | 2018-09-29 | Clock duty cycle adjuster |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811144175.4A CN109274354A (en) | 2018-09-29 | 2018-09-29 | Clock duty cycle adjuster |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109274354A true CN109274354A (en) | 2019-01-25 |
Family
ID=65199149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811144175.4A Pending CN109274354A (en) | 2018-09-29 | 2018-09-29 | Clock duty cycle adjuster |
Country Status (1)
| Country | Link |
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| CN (1) | CN109274354A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115664389A (en) * | 2022-11-18 | 2023-01-31 | 合肥奎芯集成电路设计有限公司 | Clock signal duty ratio self-adaptive adjusting circuit and adjusting method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020008589A1 (en) * | 1996-11-08 | 2002-01-24 | Paul E. Lanoman | Digitally-controlled oscillator with switched-capacitor frequency selection |
| US6426660B1 (en) * | 2001-08-30 | 2002-07-30 | International Business Machines Corporation | Duty-cycle correction circuit |
| CN1722615A (en) * | 2004-06-23 | 2006-01-18 | 三星电子株式会社 | The duty-cycle correction circuit that is used for semiconductor device |
| US20080218151A1 (en) * | 2006-12-28 | 2008-09-11 | Stmicroelectronics Pvt. Ltd. | On chip duty cycle measurement module |
| CN102638246A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Duty ratio regulating circuit |
| CN106330143A (en) * | 2016-08-30 | 2017-01-11 | 灿芯半导体(上海)有限公司 | Duty cycle calibration circuit |
| CN106603040A (en) * | 2015-10-19 | 2017-04-26 | 爱思开海力士有限公司 | Duty cycle detector circuit |
| CN108134602A (en) * | 2017-12-21 | 2018-06-08 | 睿力集成电路有限公司 | Duty-ratio calibrating circuit and semiconductor memory |
-
2018
- 2018-09-29 CN CN201811144175.4A patent/CN109274354A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020008589A1 (en) * | 1996-11-08 | 2002-01-24 | Paul E. Lanoman | Digitally-controlled oscillator with switched-capacitor frequency selection |
| US6426660B1 (en) * | 2001-08-30 | 2002-07-30 | International Business Machines Corporation | Duty-cycle correction circuit |
| CN1722615A (en) * | 2004-06-23 | 2006-01-18 | 三星电子株式会社 | The duty-cycle correction circuit that is used for semiconductor device |
| US20080218151A1 (en) * | 2006-12-28 | 2008-09-11 | Stmicroelectronics Pvt. Ltd. | On chip duty cycle measurement module |
| CN102638246A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Duty ratio regulating circuit |
| CN106603040A (en) * | 2015-10-19 | 2017-04-26 | 爱思开海力士有限公司 | Duty cycle detector circuit |
| CN106330143A (en) * | 2016-08-30 | 2017-01-11 | 灿芯半导体(上海)有限公司 | Duty cycle calibration circuit |
| CN108134602A (en) * | 2017-12-21 | 2018-06-08 | 睿力集成电路有限公司 | Duty-ratio calibrating circuit and semiconductor memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115664389A (en) * | 2022-11-18 | 2023-01-31 | 合肥奎芯集成电路设计有限公司 | Clock signal duty ratio self-adaptive adjusting circuit and adjusting method |
| CN115664389B (en) * | 2022-11-18 | 2023-03-17 | 合肥奎芯集成电路设计有限公司 | Clock signal duty ratio self-adaptive adjusting circuit and adjusting method |
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Application publication date: 20190125 |
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